Circuit board

Abstract

The circuit board according to an embodiment includes: an insulating layer including a first area and a second area; a plurality of outer layer circuit patterns disposed on upper surfaces of the first area and the second area of the insulating layer; and a solder resist including a first portion disposed on the first area of the insulating layer and a second portion disposed on the second area of the insulating layer, wherein the first portion includes an upper surface at least partially having a curved surface and exposes upper surfaces of the outer layer circuit patterns disposed on the first area of the insulating layer, the second portion covers the upper surfaces of the outer layer circuit patterns disposed on the second area of the insulating layer, and at least a portion of the upper surface of the first portion is disposed lower than the upper surfaces of the outer layer circuit patterns.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a circuit board, and more particularly, to a circuit board capable of supporting and protecting an outermost circuit pattern in an opening area using a solder resist and a manufacturing method thereof. BACKGROUND

[0002] As the miniaturization, lightening and integration of electronic components are accelerated, the line width of a circuit has been refined. In particular, as the design rule of a semiconductor chip is integrated in nanometers, the circuit line width of a package substrate or a printed circuit board on which the semiconductor chip is mounted has been refined to several micrometers or less.

[0003] In order to improve the circuit integration of a printed circuit board, i.e., to reduce the circuit line width, various methods have been proposed. In order to prevent the loss of the circuit line width in an etching step of forming a pattern after plating copper, a semi-additive process (SAP) method and a modified semi-additive process (MSAP) have been proposed.

[0004] Then, an embedded trace substrate (hereinafter referred to as "ETS") method for embedding a copper foil in an insulating layer to implement a fine circuit pattern is used in the industry. In the ETS method, instead of forming a copper foil circuit on the surface of an insulating layer, a copper foil circuit is manufactured in a form embedded in an insulating layer, so there is no circuit loss due to etching, and it is advantageous to refine the circuit pitch.

[0005] Meanwhile, recently, there have been efforts to develop an improved 5G (5th-Generation) communication system or a pre-5G communication system to meet the demand for wireless data traffic. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (lower than 6 GHz, 28 GHz, 38 GHz, or higher frequencies) to implement high data transmission rates.

[0006] In addition, in order to reduce the path loss of radio waves and increase the transmission distance of radio waves in the ultra-high frequency band, integration technologies such as beamforming, massive multiple-input multiple-output (massive MIMO), and array antennas are developed in the 5G communication system. The antenna system becomes relatively large in consideration of the fact that it can consist of hundreds of active antennas of wavelengths within the band.

[0007] Since such an antenna and an AP module are patterned or mounted on a printed circuit board, low loss on the printed circuit board is very important. This means that a plurality of substrates constituting an active antenna system, i.e., an antenna substrate, an antenna feed substrate, a transceiver substrate, and a baseband substrate, should be integrated into one compact unit.

[0008] In addition, the circuit board applied to the 5G communication system as described above is manufactured in a trend of lightness and thinness and compactness, and thus the circuit pattern is also gradually refined.

[0009] However, a circuit board including a conventional fine circuit pattern has a structure in which the outermost circuit pattern provided at the outermost portion protrudes above the insulating layer, and thus there is a problem in that the outermost circuit pattern is easily collapsed. SUMMARY

[0010] TECHNICAL PROBLEM

[0011] Embodiments provide a circuit board having a new structure and a manufacturing method thereof.

[0012] In addition, embodiments provide a circuit board capable of supporting and protecting the outermost circuit pattern provided in the SR opening area using a solder resist and a manufacturing method thereof.

[0013] In addition, embodiments provide a circuit board including a solder resist exposing a circuit pattern in an SR opening area by performing an exposure and development process and a manufacturing method thereof.

[0014] In addition, embodiments provide a circuit board including a solder resist having a surface protrusion in an upward direction and a manufacturing method thereof.

[0015] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong through the following description.

[0016] TECHNICAL SOLUTION

[0017] The circuit board according to an embodiment includes an insulating layer including a first area and a second area, an outer layer circuit pattern provided on an upper surface of the first area and the second area of the insulating layer, and a solder resist including a first portion provided on the first area of the insulating layer and a second portion provided on the second area of the insulating layer, wherein the first portion of the solder resist is provided to expose an upper surface of the outer layer circuit pattern provided on the first area of the insulating layer, the second portion of the solder resist is provided to cover the upper surface of the outer layer circuit pattern provided on the second area of the insulating layer, at least a portion of the upper surface of the first portion of the solder resist is provided to be lower than the upper surface of the outer layer circuit pattern, and the upper surface of the first portion of the solder resist has a convex shape.

[0018] In addition, the first portion of the solder resist includes a highest portion having a highest height of the upper surface of the first portion of the solder resist and a lowest portion having a lowest height of the upper surface of the first portion of the solder resist, and wherein the lowest portion is provided closer to the outer layer circuit pattern than the highest portion.

[0019] Further, the highest portion is located in a central region of an upper surface of the solder resist provided between adjacent outer layer circuit patterns among the plurality of outer layer circuit patterns, the lowest portion is located in an edge region of the upper surface of the solder resist provided between the adjacent outer layer circuit patterns, and wherein the height of the upper surface of the solder resist between the adjacent outer layer circuit patterns decreases from the central region toward the edge region.

[0020] Further, the height of the highest portion is higher than the height of the outer layer circuit pattern, and the height of the lowest portion is lower than the height of the outer layer circuit pattern.

[0021] Further, the height of the lowest portion satisfies a range of 70% to 95% of the height of the outer layer circuit pattern, and the height of the highest portion satisfies a range of 102% to 120% of the height of the outer layer circuit pattern.

[0022] Further, the height of the lowest portion satisfies a range of 80% to 97% of the height of the highest portion.

[0023] Further, the second portion of the solder resist includes: a 2-1 portion that overlaps the outer layer circuit pattern in a vertical direction; and a 2-2 portion that does not overlap the outer layer circuit pattern in the vertical direction, and the height of the 2-1 portion is lower than the height of the 2-2 portion.

[0024] Further, the upper surface of the 2-1 portion of the solder resist has a concave shape, and the upper surface of the 2-2 portion of the solder resist has a convex shape.

[0025] Further, the insulating layer includes a plurality of layers, and the outer layer circuit pattern is provided to protrude from a surface of an uppermost insulating layer or a lowermost insulating layer of the plurality of layers.

[0026] Further, the circuit board further includes a primer layer provided between the upper surface of the insulating layer and the lower surface of the solder resist or the lower surface of the outer layer circuit pattern.

[0027] On the other hand, the manufacturing method of the circuit board according to the embodiment includes: manufacturing an inner layer substrate; forming an uppermost insulating layer on the inner layer substrate, the uppermost insulating layer having a primer layer provided on an upper surface; forming an outer layer circuit pattern on the primer layer of the uppermost insulating layer; forming a solder resist layer on the primer layer and the outer layer circuit pattern; and performing partial exposure and development on the solder resist layer to form a solder resist including a first portion and a second portion, wherein the solder resist layer includes the first portion provided in a region vertically overlapping the outer layer circuit pattern and formed on the outer layer circuit pattern, and the second portion provided in a region not vertically overlapping the outer layer circuit pattern and formed on the primer layer, and wherein the height of the second portion is higher than the height of the first portion.

[0028] Further, the insulating layer includes a first region in which the first portion of the solder resist is disposed and a second region in which the second portion of the solder resist is disposed, the first portion of the solder resist is disposed to expose an upper surface of the outer layer circuit pattern disposed on the first region of the insulating layer, the second portion of the solder resist is disposed to cover the upper surface of the outer layer circuit pattern disposed on the second region of the insulating layer, at least a portion of the upper surface of the first portion of the solder resist is disposed lower than the upper surface of the outer layer circuit pattern, and the upper surface of the first portion of the solder resist has a convex shape.

[0029] Further, the first portion of the solder resist includes a highest portion having a highest height of the upper surface of the first portion of the solder resist and a lowest portion having a lowest height of the upper surface of the first portion of the solder resist, and wherein the lowest portion is disposed closer to the outer layer circuit pattern than the highest portion.

[0030] Further, the highest portion is located at a central region of the upper surface of the solder resist disposed between adjacent outer layer circuit patterns of the plurality of outer layer circuit patterns, the lowest portion is located at an edge region of the upper surface of the solder resist disposed between the adjacent outer layer circuit patterns, and wherein a height of the upper surface of the solder resist between the adjacent outer layer circuit patterns decreases from the central region to the edge region.

[0031] Further, a height of the highest portion is higher than a height of the outer layer circuit pattern, and a height of the lowest portion is lower than the height of the outer layer circuit pattern.

[0032] Further, the height of the lowest portion satisfies a range of 70% to 95% of the height of the outer layer circuit pattern, and the height of the highest portion satisfies a range of 102% to 120% of the height of the outer layer circuit pattern.

[0033] Further, the height of the lowest portion satisfies a range of 80% to 97% of the height of the highest portion.

[0034] Further, the second portion of the solder resist includes a 2-1 portion overlapping the outer layer circuit pattern in a vertical direction and a 2-2 portion not overlapping the outer layer circuit pattern in the vertical direction, and a height of the 2-1 portion is lower than a height of the 2-2 portion.

[0035] Further, an upper surface of the 2-1 portion of the solder resist has a concave shape, and an upper surface of the 2-2 portion of the solder resist has a convex shape.

[0036] Advantageous Effects

[0037] The circuit board in the embodiment is a multi-layer structure having eight or more layers and includes an outer layer circuit pattern disposed on an outermost insulating layer among the plurality of layers and protruding above a surface of the outer insulating layer. In this case, the outer layer circuit pattern includes a first outer layer circuit pattern disposed in a first region that is an opening region in which solder resist is not disposed and a second outer layer circuit pattern located in a second region in which the solder resist is disposed. In this case, the second outer layer circuit pattern can be supported and protected by the solder resist, but the first outer layer circuit pattern does not have a support layer capable of supporting the first outer layer circuit pattern, and thus there is a problem in that the first outer layer circuit pattern can easily collapse due to various factors.

[0038] Accordingly, the embodiment allows all of the solder resist in the first region to remain without being removed, and thus the first outer layer circuit pattern can be supported and protected by the solder resist. Accordingly, the embodiment can solve a problem such as collapse or rubbing of the first outer layer circuit pattern in the first region by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, the embodiment can solve a problem such as collapse or rubbing of a trace of the first outer layer circuit pattern in the first region, thereby improving product reliability.

[0039] Meanwhile, the solder resist of the embodiment includes a first portion disposed in the first region and a second portion disposed in the second region. In this case, an upper surface of the first portion of the embodiment can have a convex shape in an upward direction. For example, an outer region of the upper surface of the first portion of the solder resist can have a fourth height, and an inner region of the upper surface of the first portion of the solder resist can have a fifth height that is greater than the fourth height. That is, the upper surface of the first portion of the solder resist can include a highest portion having the highest height and a lowest portion having the lowest height. In addition, the lowest portion can be disposed closer to the outer layer circuit pattern than the highest portion. Accordingly, in the embodiment, the upper surface of the first portion of the solder resist can have a convex shape, and thus the surface area of the first portion of the solder resist can be increased. Accordingly, a contact surface with another layer (for example, a molding layer) disposed on the first portion is increased, thereby improving bonding strength. In addition, the height of the lowest portion is less than the height of the first outer layer circuit pattern. Accordingly, the embodiment can prevent a portion of the first portion of the solder resist from remaining on a surface of the first outer layer circuit pattern, thereby improving reliability. In addition, in the embodiment, the height of the highest portion of the first portion of the solder resist is greater than the height of the first outer layer circuit pattern. Accordingly, the embodiment can allow a dam function of an adhesive member to be implemented by the first portion of the solder resist, thereby improving reliability.

[0040] Further, the circuit board of the embodiment can be applied to a 5G communication system, and thus, transmission loss of a high frequency can be minimized, thereby further improving reliability. Specifically, the circuit board of the embodiment can be used at a high frequency and can reduce wave loss. BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a view illustrating a circuit board manufactured by an SAP method according to a comparative example.

[0042] Figure 2 FIG. 2 is a view illustrating a circuit board manufactured by an ETS method in the comparative example.

[0043] Figure 3 FIG. 3 is a view illustrating a circuit board according to an embodiment.

[0044] Figure 4a FIG. 4 is an enlarged view of a region B of FIG. 3. Figure 3

[0045] Figure 4b FIG. 5 is an enlarged view of a region C of FIG. 3. Figure 4a

[0046] Figure 4c FIG. 6 is a view illustrating various modified examples of a protective layer of the embodiment. Figure 4d

[0047] FIG. 7 is a view illustrating a first region and a second region according to the embodiment. Figure 5

[0048] FIG. 8 is a view illustrating a height difference of a solder resist in the second region according to the embodiment. Figure 6

[0049] FIG. 9 is a view illustrating a manufacturing method of a circuit board according to the embodiment in a process sequence. Figures 7 to 14 DETAILED DESCRIPTION

[0050] Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are denoted by the same reference numerals regardless of the drawings, and repetitive description thereof will be omitted. The component suffixes "module" and "part" used in the following description are given or mixed together only in consideration of easiness in creating the specification, and they have no meanings or effects of distinguishing each other by themselves. Further, in describing the embodiments disclosed in the present specification, when it is determined that a detailed description of the related known technology unnecessarily obscures the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. Further, the drawings are only for the convenience of understanding the embodiments disclosed in the present specification, and the technical scope disclosed in the present specification is not limited by the drawings, and it should be understood to include all modifications, equivalents, and substitutions falling within the spirit and scope of the present invention.

[0051] ​​​It should be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one element from another.

[0052] It should be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0053] As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] It should be understood that the terms “comprise,” “include,” or “have,” specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof in the specification, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0055] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0056] Before describing the embodiments, a comparative example compared with the embodiments will be described.

[0057] FIG. 1 is a view illustrating a circuit board according to a comparative example.

[0058] Referring to 1(a), the circuit board according to the comparative example includes a circuit pattern manufactured by a general SAP method.

[0059] Specifically, the circuit board includes an insulating layer 10, a circuit pattern 20, and a protective layer 30.

[0060] The circuit pattern 20 is disposed on the upper and lower surfaces of the insulating layer 10, respectively.

[0061] In this case, at least one circuit pattern 20 disposed on the surface of the insulating layer 10 includes a fine circuit pattern.

[0062] In FIG. 1, the circuit pattern 20 disposed on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes a trace 21 that is a signal transmission wiring and a pad 22 for mounting a chip or the like.

[0063] In this case, in the embodiments, since a support layer using a solder resist is formed to protect the fine circuit pattern, the structure in a region in which the fine circuit pattern is formed in the comparative example will be described.

[0064] In addition, the protective layer 30 for protecting the circuit pattern 20 is disposed on the surface of the insulating layer 10.

[0065] In this case, the upper region of the insulating layer 10 includes a first region provided with the protective layer 30 and a second region which is an open region where the protective layer 30 is not provided.

[0066] Therefore, a part of the circuit pattern 20 provided on the upper surface of the insulating layer 10 is covered by the protective layer 30, and the remaining part is not covered by the protective layer 30 and is exposed to the outside.

[0067] In this case, the trace 21 and the pad 22 corresponding to the fine circuit pattern described above are provided in the second region which is the open region of the protective layer 30.

[0068] For example, at least one of the trace 21 and the pad 22 is formed with a width / interval of 15 μm / 15 μm or less.

[0069] In this case, when the circuit pattern formed in the open region of the protective layer 30 is a pattern with a width exceeding 15 μm, not a fine circuit pattern, the circuit pattern can resist external impact.

[0070] However, as the circuit pattern is gradually fine, the width and interval of the trace 21 and the pad 22 of the fine circuit pattern which is the outermost layer are gradually reduced, as shown in FIG. 1(b), and thus, when the fine circuit pattern protruding above the upper surface of the insulating layer 10 is provided in the second region which is the open region of the protective layer, there is a problem in that the fine circuit pattern is easily collapsed due to external impact.

[0071] That is, as shown in B of FIG. 1(b), the trace 21 corresponding to the fine circuit pattern of the outermost layer has an extremely fine pattern shape, and thus, even a small external impact can easily cause a collapse or rubbing problem.

[0072] Meanwhile, recently, a fine circuit pattern provided in the open region of the protective layer while having a structure buried in the insulating layer is formed by using an ETS method.

[0073] Figure 2 is a view showing a circuit board manufactured by an ETS method in a comparative example.

[0074] Referring to Figure 2 , in detail, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0075] The circuit pattern 20A is provided on the upper surface and the lower surface of the insulating layer 10A, respectively.

[0076] In this case, at least one of the circuit patterns 20A provided on the surface of the insulating layer 10A includes a fine circuit pattern.

[0077] Here, when the circuit pattern is formed by the ETS method, the first formed circuit pattern has a structure buried in the insulating layer 10A. Therefore, when the first formed circuit pattern is formed as a fine circuit pattern, even in the comparative example, the fine circuit pattern can have a structure in which the fine circuit pattern is buried in the insulating layer 10A.

[0078] That is, the circuit board manufactured by the ETS method includes a fine circuit pattern having a structure buried in the surface of the insulating layer 10A. That is, the fine circuit pattern includes a trace 21A as a signal transmission line and a pad 22A for mounting a chip or the like.

[0079] Further, when the circuit board is manufactured by the above-described ETS method, since the fine circuit pattern has a structure buried in the insulating layer, the fine circuit pattern can be protected from external impact.

[0080] In this case, for Figure 2 There is no big problem in manufacturing the circuit board by the ETS method with respect to the substrate having a two-layer structure (based on the number of layers of the circuit pattern) as shown in FIG. 1. However, in the case of manufacturing a circuit board having 8 layers or more, particularly 10 layers or more, by the ETS method, a delivery period of the circuit board takes at least 2 months or more, and thus there is a problem in that productivity is reduced.

[0081] Further, in order to manufacture a fine circuit pattern having a buried structure by the ETS method, the fine circuit pattern should be first formed in the manufacturing process of a multilayer circuit board. Further, recently, in order to be applied to an AP module having high integration / high specification or the like, a circuit board having eight to ten layers is required. In this case, in a process in which the fine circuit pattern is first formed during the ETS process and then a multilayer lamination process is performed, damage to the fine circuit pattern occurs due to thermal stress or the like, and thus there is a problem in that it is difficult to normally implement the fine circuit pattern.

[0082] Further, when the circuit board is manufactured by the ETS method, an ETS core layer needs to be separately provided. In this case, when the circuit board is manufactured by the ETS method, an additional process is required to finally remove the ETS core layer.

[0083] Further, when the circuit board is manufactured by the ETS method, there is a problem in that yield is reduced due to accumulated tolerances when a plurality of layers are laminated more than a certain number of times, and thus product costs increase, and there is a problem in that, when the lamination process is performed on both surfaces around the ETS core layer, respectively, pattern damage increases due to stress.

[0084] Furthermore, with the development of 5G technology in recent years, there has been increasing interest in circuit boards that reflect this. In this context, for the application of 5G technology, the circuit board should have a high degree of multilayer structure, therefore, the circuit pattern should be finely detailed. However, in the comparative example, although fine patterns can be formed, there is a problem that the fine patterns cannot be stably protected.

[0085] Therefore, the embodiments aim to provide a new type of circuit board and its control method that can solve the reliability problem of fine patterns set on the outermost layer.

[0086] Figure 3 This is a view showing a circuit board according to an embodiment. Figure 4a yes Figure 3 A magnified view of region B. Figure 4b yes Figure 4a A magnified view of region C. Figure 4c and Figure 4d This is a view illustrating various examples of modifications to the protective layer of the embodiment. Figure 5 This is a view showing the first and second regions according to an embodiment. Figure 6 This is a view showing the height difference of the solder resist in the second region according to an embodiment.

[0087] exist Figure 3 Prior to the description in Figure 4, the circuit board according to the embodiment may have a multi-layer structure. Preferably, the circuit board according to the embodiment may have a structure of ten or more layers based on the number of layers in the circuit pattern. However, this is merely an example and the embodiment is not limited thereto. That is, the number of layers in the circuit board in the embodiment may be less than ten, or the number of layers in the circuit board may be greater than ten.

[0088] However, the circuit board in the embodiment is designed to address the problems of the ETS method in the comparative example. In this case, the ETS method in the comparative example has many problems when manufacturing circuit boards with eight or more layers; therefore, for comparison, the embodiment is described as having a ten-layer structure.

[0089] Reference Figure 3 , Figure 4a and Figure 4b The circuit board 100 includes an insulating layer 110.

[0090] Preferably, the circuit board 100 may include first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118 and 119 to achieve a ten-layer structure.

[0091] In this case, the first, second, third, fourth, fifth, sixth, and seventh insulating layers 111, 112, 113, 114, 115, 116, and 117 of the insulating layer 110 can be inner insulating layers disposed inside the stacked insulating layer structure, the eighth insulating layer 118 can be an uppermost insulating layer (a first outermost insulating layer) disposed on the inner insulating layers, and the ninth insulating layer 119 can be a lowermost insulating layer (a second outermost insulating layer) disposed below the inner insulating layers.

[0092] The first insulating layer 111 can be a core insulating layer disposed at the center of the stacked structure of the insulating layer 110. The second, fourth, sixth, and eighth insulating layers 112, 114, 116, and 118 can be upper insulating layers disposed in order on the first insulating layer 111. In addition, the third, fifth, seventh, and ninth insulating layers 113, 115, 117, and 119 can be lower insulating layers disposed in order below the first insulating layer 111.

[0093] The insulating layer 110 can be a substrate on which an electronic circuit capable of changing a wiring is formed, and can include all of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming a circuit pattern on a surface thereof.

[0094] For example, the insulating layer 110 can be rigid or flexible. For example, the insulating layer 110 can include glass or plastic. Specifically, the insulating layer 110 can include chemically tempered / half-tempered glass (e.g., soda-lime glass or alumino-silicate glass, etc.), or tempered or flexible plastic (e.g., polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), and polycarbonate (PC), etc.), or sapphire.

[0095] In addition, the insulating layer 110 can include an optically isotropic film. As an example, the insulating layer 110 can include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic PC, an optically isotropic polymethyl methacrylate (PMMA), etc.

[0096] In addition, at least one of the insulating layer 110 can be partially bent while having a curved surface. That is, at least one of the insulating layer 110 can partially have a flat surface and can be partially bent while having a curved surface. Specifically, an end portion of at least one of the insulating layer 110 can be bent while having a curved surface, or can be bent or folded while having a surface with a random curvature.

[0097] Also, at least one of the insulation layers 110 can be a flexible substrate having flexibility. Also, at least one of the insulation layers 110 can be a curved or bent substrate. In this case, at least one of the insulation layers 110 can form a wiring layout of electrical wiring for connecting circuit elements based on a circuit design, and an electrical conductor can be disposed on the insulation material. Also, electronic components can be mounted on at least one of the insulation layers 110, and the insulation layer 110 can form wiring configured to connect the electronic components to form a circuit, and can mechanically fix the components in addition to electrically connecting the components.

[0098] The circuit pattern can be disposed on a surface of the insulation layer 110.

[0099] That is, the circuit pattern can be disposed on each surface of the first to ninth insulation layers 111, 112, 113, 114, 115, 116, 117, 118, and 119 constituting the insulation layer 110.

[0100] Here, the circuit pattern can include an inner layer circuit pattern 120 and outer layer circuit patterns 130 and 140. The inner layer circuit pattern 120 can be a circuit pattern disposed inside the insulation layer 110 in the stacked structure of the circuit board, and the outer layer circuit patterns 130 and 140 can be circuit patterns disposed at the outermost side of the insulation layer 110 in the stacked structure of the circuit board.

[0101] The inner layer circuit pattern 120 can include a first circuit pattern 121, a second circuit pattern 122, a third circuit pattern 123, a fourth circuit pattern 124, a fifth circuit pattern 125, a sixth circuit pattern 126, and a seventh circuit pattern 127.

[0102] The first circuit pattern 121 can be disposed on the upper surface of the first insulating layer 111, and thus the first circuit pattern 121 can be covered by the second insulating layer 112. The second circuit pattern 122 can be disposed on the lower surface of the first insulating layer 111, and thus the second circuit pattern 122 can be covered by the third insulating layer 113. The third circuit pattern 123 can be disposed on the upper surface of the second insulating layer 112, and thus the third circuit pattern 123 can be covered by the fourth insulating layer 114. The fourth circuit pattern 124 can be disposed on the lower surface of the third insulating layer 113, and thus the fourth circuit pattern 124 can be covered by the fifth insulating layer 115. The fifth circuit pattern 125 can be disposed on the upper surface of the fourth insulating layer 114, and thus the fifth circuit pattern 125 can be covered by the sixth insulating layer 116. The sixth circuit pattern 126 can be disposed on the lower surface of the fifth insulating layer 115, and thus the sixth circuit pattern 126 can be covered by the seventh insulating layer 117. The seventh circuit pattern 127 can be disposed on the upper surface of the sixth insulating layer 116, and thus the seventh circuit pattern 127 can be covered by the eighth insulating layer 118. The eighth circuit pattern 128 can be disposed on the lower surface of the seventh insulating layer 117, and thus the eighth circuit pattern 128 can be covered by the ninth insulating layer 119.

[0103] An outer circuit pattern can be disposed on the surface of the outermost insulating layer disposed at the outermost side of the insulating layers 110. Preferably, the outer circuit pattern can include a lower outer circuit pattern 130 disposed on the lower surface of the ninth insulating layer 119 disposed at the lowermost portion of the insulating layers 110.

[0104] Further, the outer circuit pattern can include an upper outer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 disposed on the uppermost portion of the insulating layers 110.

[0105] In this case, at least one of the lower outer circuit pattern 130 and the upper outer circuit pattern 140 can be formed to protrude upward from the surface of the insulating layer. Preferably, the lower outer circuit pattern 130 can be formed to protrude downward from the lower surface of the ninth insulating layer 119. Further, the upper outer circuit pattern 140 can be formed to protrude upward from the upper surface of the eighth insulating layer 118.

[0106] That is, the upper surface of the lower outer circuit pattern 130 can be on the same plane as the lower surface of the ninth insulating layer 119. Further, the lower surface of the upper outer circuit pattern 140 can be on the same plane as the upper surface of a primer layer 150 disposed on the upper surface of the eighth insulating layer 118.

[0107] In other words, the primer layer 150 can be disposed on the upper surface of the eighth insulating layer 118 and the upper outer circuit pattern 140.

[0108] That is, the upper outer layer circuit pattern 140 can include a fine circuit pattern. Preferably, the upper outer layer circuit pattern 140 can be a fine circuit pattern having a line width of 10 μm or less and a space between patterns of 10 μm or less. Thus, when the upper outer layer circuit pattern 140 is directly disposed on the eighth insulating layer 118, the contact area between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 is small, and thus a case where the upper outer layer circuit pattern 140 is separated from the eighth insulating layer 118 can occur.

[0109] Thus, in the embodiment, the primer layer 150 is disposed between the upper outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can improve the bonding force between the upper outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can be disposed to completely cover the upper surface of the eighth insulating layer 118. Further, the upper outer layer circuit pattern 140 can be partially disposed on the primer layer 150. Thus, the upper surface of the primer layer 150 in the embodiment can include a first portion in contact with the upper outer layer circuit pattern 140 and a second portion in contact with the lower surface of the solder resist 160 described later. That is, when the upper outer layer circuit pattern 140 is formed by the SAP process, the primer layer 150 can be used to strengthen the bonding force between the eighth insulating layer 118 and the upper outer layer circuit pattern 140. Such a primer layer 150 can include a urethane-based resin, an acrylic resin, or a silicone-based resin, but the embodiment is not limited thereto.

[0110] Meanwhile, Figure 3 It is illustrated in FIG. 9 that the primer layer is not disposed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130, but the primer layer can also be formed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130. However, the lower outer layer circuit pattern 130 can not be a fine circuit pattern, and thus the primer layer between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 can be selectively omitted.

[0111] Thus, when the fine circuit pattern is disposed on the inner layer, since the circuit pattern is covered by at least one of the insulating layers 110, the primer layer can be omitted. On the other hand, in the embodiment, when the fine circuit pattern is disposed on the outermost layer, since there is no insulating layer covering the fine circuit pattern, the primer layer 150 is disposed to improve the bonding force between the fine circuit pattern and the insulating layer.

[0112] Hereinafter, it will be described that the upper outer layer circuit pattern 140 is formed of a fine circuit pattern. However, the embodiment is not limited thereto, and the lower outer layer circuit pattern 130 can also be formed of a fine circuit pattern. Obviously, the structure for improving reliability, such as strengthening the bonding force and preventing the upper outer layer circuit pattern 140 described later from collapsing, can also be applied to the lower outer layer circuit pattern 130.

[0113] The inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be wirings that transmit electrical signals and can be formed of a metal material having high electrical conductivity. To this end, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding force. Preferably, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be formed of copper (Cu) having high electrical conductivity and lower cost.

[0114] At least one of the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be formed through a general process of manufacturing a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), etc., a detailed description of which will be omitted here.

[0115] Preferably, the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are outermost circuit patterns disposed at the outermost side of the circuit board, and thus they can be formed through an SAP (semi-additive process) method.

[0116] Meanwhile, a via V can be disposed in the insulating layer 110. The via V is disposed in each insulating layer, and thus the via V can be used to electrically connect circuit patterns disposed in different layers to each other.

[0117] A first via V1 can be disposed in the first insulating layer 111. The first via V1 can electrically connect a first circuit pattern 121 disposed on an upper surface of the first insulating layer 111 to a second circuit pattern 122 disposed on a lower surface of the first insulating layer 111.

[0118] A second via V2 can be disposed in the second insulating layer 112. The second via V2 can electrically connect the first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 to a third circuit pattern 123 disposed on an upper surface of the second insulating layer 112.

[0119] A third via V3 can be disposed in the third insulating layer 113. The third via V3 can electrically connect the second circuit pattern 122 disposed on the lower surface of the first insulating layer 111 to a fourth circuit pattern 124 disposed on a lower surface of the third insulating layer 113.

[0120] A fourth via V4 can be disposed in the fourth insulating layer 114. The fourth via V4 can electrically connect the third circuit pattern 123 disposed on the upper surface of the second insulating layer 112 with the fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114.

[0121] A fifth via V5 can be disposed in the fifth insulating layer 115. The fifth via V5 can electrically connect the fourth circuit pattern 124 disposed on the lower surface of the third insulating layer 113 with the sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115.

[0122] A sixth via V6 can be disposed in the sixth insulating layer 116. The sixth via V6 can electrically connect the fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114 with the seventh circuit pattern 127 disposed on the upper surface of the sixth insulating layer 116.

[0123] A seventh via V7 can be disposed in the seventh insulating layer 117. The seventh via V7 can electrically connect the sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115 with the eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117.

[0124] An eighth via V8 can be disposed in the eighth insulating layer 118. The eighth via V8 can electrically connect the seventh circuit pattern 127 disposed on the upper surface of the sixth insulating layer 116 with the upper outer layer circuit pattern 140 disposed on the upper surface of the primer layer 150.

[0125] A ninth via V9 can be disposed in the ninth insulating layer 119. The ninth via V9 can electrically connect the eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117 with the lower outer layer circuit pattern 130 disposed on the lower surface of the ninth insulating layer 119.

[0126] The above-described via V can be formed by filling the inside of a through-hole formed in each insulating layer with a metal material.

[0127] The through-hole can be formed by any one of mechanical processing, laser processing, and chemical processing. When the through-hole is formed by mechanical processing, methods such as milling, drilling, and wiring can be used, when formed by laser processing, UV or CO2 laser methods can be used, and when the through-hole is formed by chemical processing, the insulating layer 110 can be opened using chemicals including aminosilane, ketone, etc.

[0128] Meanwhile, laser processing is a cutting method that concentrates light energy on a surface to melt and evaporate part of the material to form a desired shape. Complex molding formed by a computer program can be easily processed, and composite materials that are difficult to cut by other methods can be processed.

[0129] Further, the laser processing can have a cutting diameter of at least 0.005 mm, and can process a wide range of thicknesses.

[0130] It is preferable to use a yttrium aluminum garnet (YAG) laser or a CO2 laser or an ultraviolet (UV) laser as a laser processing drill. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO2 laser is a laser that can only process the insulating layer.

[0131] When the via hole is formed, the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be formed by filling the inside of the via hole with a conductive material. The metal material forming the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material can be filled by any one or a combination of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0132] Meanwhile, a protective layer can be disposed at the outermost side of the circuit board 100. Preferably, a first protective layer 160 can be disposed on the eighth insulating layer 118 (preferably, on the primer layer 150). Further, a second protective layer 175 can be disposed under the ninth insulating layer 119.

[0133] The first protective layer 160 and the second protective layer 175 can be formed of at least one layer using any one or more of a solder resist (SR), an oxide, and Au. Preferably, the first protective layer 160 and the second protective layer 175 can be a solder resist.

[0134] Meanwhile, the first protective layer 160 is disposed on the primer layer 150. The first protective layer 160 can function to support the upper outer layer circuit pattern 140 disposed on the primer layer 150 and protect the surface of the upper outer layer circuit pattern 140.

[0135] That is, the first protective layer 160 can partially overlap the upper outer layer circuit pattern 140 disposed on the primer layer 150. The area of the first protective layer 160 can be smaller than the area of the eighth insulating layer 118. The area of the first protective layer 160 can be smaller than the area of the primer layer 150. The first protective layer 160 is partially or entirely disposed on the primer layer 150 and the upper outer layer circuit pattern 140, and thus the first protective layer 160 can include an open area that exposes the surface of the upper outer layer circuit pattern 140.

[0136] Specifically, the first protective layer 160 includes a hole-shaped open area. That is, the open area of the first protective layer 160 can vertically overlap the first area R1 to expose the first area R1.

[0137] The first region R1 can be a region of the undercoat layer 150 and an upper region of the upper outer layer circuit pattern 140 in which the first protective layer 160 is not disposed (i.e., an opening region of the first protective layer).

[0138] That is, the first region R1 can be a region in which the first protective layer 160 is not disposed to electrically connect the upper outer layer circuit pattern 140 to a component such as a chip. Accordingly, the upper outer layer circuit pattern 140 disposed on the first region R1 can be exposed to the outside in a state in which a protective layer protecting the same is not present.

[0139] In detail, the upper outer layer circuit pattern 140 includes a device mounting pad on which a chip device is mounted, a core pad or a BGA pad serving as a die to be connected to an external board, a trace as a signal transmission wiring, and is disposed on the first region R1. Further, the first protective layer 160 has an opening region exposing a surface of the upper outer layer circuit pattern 140 corresponding to the device mounting pad, the core pad, and the BGA pad in the first region R1.

[0140] That is, the circuit board includes the first region R1 and a second region R2. The first region R1 is an opening region in which a surface of the upper outer layer circuit pattern 140 should be exposed through the first protective layer 160, and the second region R2 can be a buried region in which the surface of the upper outer layer circuit pattern 140 is covered by the first protective layer 160.

[0141] The first region R1 is a region of the upper outer layer circuit pattern 140 in which a first pad 142 electrically connected to a component such as a chip, a trace 141, and a second pad (not shown) corresponding to a core pad or a BGA pad serving as a die to be bonded to an external board are present.

[0142] Further, the upper outer layer circuit pattern 140 disposed in the first region R1 as described above can have a reliability problem such as collapse or abrasion due to various factors. Further, the trace 141 of the upper outer layer circuit pattern 140 is a fine circuit pattern, and thus the upper outer layer circuit pattern 140 has a line width of 10 μm or less and a pitch of 10 μm or less, and is disposed on the undercoat layer 150. Accordingly, the trace 141 disposed on the first region R1 can have a problem of being easily collapsed or abraded due to various small external impacts.

[0143] Accordingly, in the embodiment, in order to improve the reliability of the upper outer layer circuit pattern 140 disposed on the first region R1, the first protective layer 160 is formed on the undercoat layer 150 corresponding to the first region R1.

[0144] That is, the first protective layer 160 can be disposed in a region of the upper surface of the primer layer 150 in which the upper outer circuit pattern 140 is not disposed. For example, the first protective layer 160 can be disposed on the upper surface of the primer layer 150, and thus the first protective layer 160 can be disposed between the upper outer circuit patterns 140 on the first region R1.

[0145] In this case, the upper outer circuit pattern 140 includes a first outer circuit pattern formed in the first region R1 and a second outer circuit pattern formed in the second region R2.

[0146] Further, the upper surface of the primer layer 150 can include a first upper surface corresponding to the first region R1 and a second upper surface corresponding to the second region R2.

[0147] In this case, the first protective layer 160 can be disposed entirely on the primer layer 150 without dividing the first region R1 and the second region R2. That is, the first protective layer 160 can be disposed in a region between the first outer circuit patterns and a region between the second outer circuit patterns, respectively.

[0148] Accordingly, the first protective layer 160 includes a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0149] In this case, the first protective layer 160 can have different heights with respect to each region.

[0150] In the first region R1, the surface of the upper outer circuit pattern 140 should be exposed to the outside, and in the second region R2, the surface of the upper outer circuit pattern 140 should be covered with a protective layer.

[0151] The first protective layer 160 can include a first portion disposed in the first region R1 and a second portion disposed in the second region R2. Further, the first portion and the second portion can have different heights.

[0152] For example, the upper surface of the first portion disposed in the first region R1 can be disposed lower than the upper surface of the second portion disposed in the second region R2.

[0153] Further, the upper surface of the second portion can be disposed higher than the upper surface of the first portion.

[0154] In this case, the upper surface of the first protective layer 160 can have a curved line.

[0155] For example, the upper surface of the first protective layer 160 can have a shape concave toward the downward direction in a region vertically overlapping the upper outer layer circuit pattern 140. For example, the upper surface of the first protective layer 160 can have a shape convex toward the upward direction in a region not vertically overlapping the upper outer layer circuit pattern 140.

[0156] In other words, the height of the upper surface of the first protective layer 160 in the region overlapping the upper outer layer circuit pattern 140 can be less than the height in the region not overlapping the upper outer layer circuit pattern 140.

[0157] In this case, the first protective layer 160 includes a first portion disposed in the first region R1 and a second portion disposed in the second region R2. Also, the first portion of the first protective layer 160 exposes the first outer layer circuit pattern. Accordingly, the first portion of the first protective layer 160 can be selectively disposed in a region not vertically overlapping the first outer layer circuit pattern in the vertical direction. Accordingly, the first portion of the first protective layer 160 can have a shape in which the upper surface is convex toward the upward direction. For example, the first portion of the first protective layer 160 can be disposed between a plurality of adjacent first outer layer circuit patterns among the plurality of first outer layer circuit patterns.

[0158] Meanwhile, the second portion of the first protective layer 160 covers the second outer layer circuit pattern. Accordingly, the second portion of the first protective layer 160 includes a 2-1 portion disposed in a region vertically overlapping the second outer layer circuit pattern 140 and a 2-2 portion other than the 2-1 portion. Also, the 2-1 portion of the first protective layer 160 can have a shape concave toward the downward direction. Also, the 2-2 portion of the first protective layer 160 can have a shape convex toward the upward direction.

[0159] Hereinafter, the first protective layer 160 will be described in detail.

[0160] The first protective layer 160 can be disposed on the primer layer 150. The first protective layer 160 is a solder resist.

[0161] The first protective layer 160 can be disposed between the upper outer layer circuit patterns 140 on the primer layer 150. That is, the upper outer layer circuit patterns 140 are disposed at regular intervals on the primer layer 150. Also, the first protective layer 160 can be disposed on a region of the upper surface of the primer layer 150 on which the upper outer layer circuit pattern 140 is not disposed. Also, the first protective layer 160 can be selectively disposed on the upper outer layer circuit pattern 140.

[0162] Hereinafter, the first protective layer 160 will be described as a solder resist 160.

[0163] The solder resist 160 can be disposed on an area of the upper surface of the primer layer 150 on which the upper outer circuit pattern 140 is not disposed.

[0164] Accordingly, the lower surface of the solder resist 160 can directly contact the upper surface of the primer layer 150. Also, the solder resist 160 can have a structure directly contacting the upper outer circuit pattern 140.

[0165] For example, the first portion of the solder resist 160 disposed in the first area R1 can directly contact a portion of the side surface of the upper outer circuit pattern 140.

[0166] Also, the second portion of the solder resist 160 disposed in the second area R2 can directly contact the side surface of the upper outer circuit pattern 140. Also, the second portion of the solder resist 160 disposed in the second area R2 can directly contact the upper surface of the upper outer circuit pattern 140. That is, the second portion of the solder resist 160 disposed in the second area R2 protrudes above the upper surface of the upper outer circuit pattern 140 by a predetermined height, and the second portion of the solder resist 160 can be disposed to cover the upper outer circuit pattern 140. In detail, the second portion of the solder resist 160 disposed in the second area R2 can be disposed to surround the side surface and the upper surface of the upper outer circuit pattern 140.

[0167] In this case, the solder resist 160 can have different heights for each portion. Here, the height of each portion of the solder resist 160 can be determined by the height of the upper outer circuit pattern 140.

[0168] The upper outer circuit pattern 140 can be disposed on the insulating layer 110 at a first height H1. In this case, the insulating layer 110 can refer to an insulating layer disposed at the uppermost side of a plurality of insulating layers. However, hereinafter, for convenience of description, it will be described as the insulating layer 110. Meanwhile, the primer layer 150 can be disposed between the insulating layer 110 and the upper outer circuit pattern 140. In this case, the upper outer circuit pattern 140 can be disposed on the primer layer 150 at the first height H1. Also, the "height" described below can correspond to "thickness".

[0169] The first height H1 of the upper outer circuit pattern 140 can be 12 µm ± 2 µm. For example, the first height H1 of the upper outer circuit pattern 140 can be in the range of 10 µm to 14 µm.

[0170] The second portion of the solder resist 160 can be disposed on the upper outer circuit pattern 140 at a predetermined height. In this case, the second portion of the solder resist 160 can have different heights according to the position. That is, the upper surface of the second portion of the solder resist 160 can be a curved surface, a circular surface, or a concave-convex surface rather than a flat surface.

[0171] In this case, the second portion of the solder resist 160 is disposed to cover the upper outer layer circuit pattern 140 to stably protect the upper outer layer circuit pattern 140. In this case, the height of the second portion of the solder resist 160 can be 7 μm to 17 μm. When the height of the second portion of the solder resist 160 is less than 7 μm, the upper outer layer circuit pattern 140 buried in the second portion of the solder resist 160 cannot be stably protected from various factors. In addition, when the height of the second portion of the solder resist 160 is greater than 17 μm, the overall thickness of the circuit board can increase. In addition, when the height of the second portion is greater than 17 μm, the manufacturing cost of the circuit board can increase.

[0172] In this case, as described above, the second portion of the solder resist 160 includes a 2-1 portion and a 2-2 portion. In this case, the highest portion 160-2 of the 2-1 portion of the solder resist 160 can have a second height H2. In addition, the lowest portion 160-1 of the 2-2 portion of the solder resist 160 can have a third height H3. In this case, each of the second height H2 and the third height H3 can be in the range of 7 μm to 17 μm.

[0173] Meanwhile, the difference ΔH between the second height H2 and the third height H3 can be in the range of 1 μm to 7 μm. For example, the third height H3 can be in the range between 80% and 97% of the second height H2. For example, the third height H3 can be in the range between 85% and 95% of the second height H2. The third height H3 can be in the range between 88% and 92% of the second height H2.

[0174] Meanwhile, the first portion of the solder resist 160 can be disposed in the first area R1. Preferably, the first portion of the solder resist 160 can be disposed between the first outer layer circuit patterns located in the first area R1 of the upper outer layer circuit pattern 140.

[0175] In this case, the upper surface of the first portion of the solder resist 160 can have a convex shape toward the upward direction. That is, as Figure 4bAs illustrated, a portion of the upper surface of the first portion of the solder resist 160 can be disposed higher than the upper surface of the first outer layer circuit pattern. Also, a portion of the upper surface of the solder resist 160 can be disposed lower than the upper surface of the first outer layer circuit pattern. For example, the lowest portion of the upper surface of the first portion of the solder resist 160 can have a fourth height H4 that is less than the first height H1. For example, the highest portion of the upper surface of the first portion of the solder resist 160 can have a fifth height H5 that is greater than the first height H1. In this case, the fourth height H4 can be 70% to 95% of the first height H1. For example, the fourth height H4 can be 75% to 90% of the first height H1. In this case, the fourth height H4 can be 75% to 88% of the first height H1. When the fourth height H4 is less than 70% of the first height H1, the first outer layer circuit pattern can not be stably supported by the first portion. When the fourth height H4 is greater than 95% of the first height H1, a portion of the solder resist can remain on the surface of the first outer layer circuit pattern, and thus a reliability problem can occur.

[0176] Meanwhile, the fifth height H5 can be 102% to 120% of the first height H1. The fifth height H5 can be 105% to 118% of the first height H1. The fifth height H5 can be 108% to 115% of the first height H1. When the fifth height H5 is less than 102% of the first height H1, a dam function of the first portion, which will be described later, cannot be implemented. Also, when the fifth height H5 is greater than 120% of the first height H1, the fourth height H4 increases. Thus, the solder resist 160 can remain on the surface of the first outer layer circuit pattern, and thus a reliability problem can occur. Meanwhile, the fourth height H4 can be a height of a portion of the upper surface of the first portion of the solder resist 160 located in the edge region. For example, the fourth height H4 can be a height of an edge portion of the first portion of the solder resist 160. That is, the height of the upper surface of the first portion of the solder resist 160 can decrease as it approaches the first outer layer circuit pattern, and the height of the upper surface of the first portion of the solder resist 160 can increase as the distance from the first outer layer circuit pattern increases. Thus, the solder resist 160 can have the highest fifth height H5 in a central region of the upper surface of the first portion, but is not limited thereto. However, the lowest portion of the second portion of the solder resist 160 having the fourth height H4 can be disposed adjacent to the first outer layer circuit pattern compared to the highest portion.

[0177] Meanwhile, a difference between the fourth height H4 and the fifth height H5 can have a range of 1 µm to 7 µm. For example, the fourth height H4 can have a range of 80% to 97% of the fifth height H5. For example, the fourth height H4 can have a range of 85% to 95% of the fifth height H5. The fourth height H4 can have a range of 88% to 92% of the fifth height H5.

[0178] Meanwhile, the photo resist film can be used as the solder resist 160. The solder resist 160 can have a structure in which a resin and a filler are mixed.

[0179] For example, the solder resist 160 can include a filler such as BaSO4, SiO2, or talc, and the content of the filler can be in the range of 20 to 35 wt%.

[0180] In this case, when the content of the filler included in the solder resist 160 is less than 20 wt%, the upper outer layer circuit pattern 140 can not be stably protected by the solder resist 160. Also, when the content of the filler included in the solder resist 160 is more than 35 wt%, part of the filler can remain on the upper outer layer circuit pattern 140 in a developing process of the solder resist 160, and thus, a reliability problem occurs or a process of removing the filler must be additionally performed.

[0181] Meanwhile, the upper surface of the second portion of the solder resist 160 in the embodiment is a portion that is not exposed and developed.

[0182] Also, the upper surface of the first portion of the solder resist 160 is a portion that is exposed and developed.

[0183] Thus, part of the filler can be exposed to the upper surface of the first portion of the solder resist 160. However, the filler can not be directly exposed to the upper surface of the second portion of the solder resist 160.

[0184] Thus, the surface roughness of the first portion of the solder resist 160 can be different from the surface roughness of the second portion of the solder resist 160. For example, the surface roughness of the first portion can be greater than the surface roughness of the second portion of the solder resist 160.

[0185] Meanwhile, as described above, the first outer layer circuit pattern includes a pad. Also, an adhesive member such as a solder ball for device mounting is disposed on the pad. In this case, in the embodiment, part of the upper surface of the first portion of the solder resist 160 is disposed higher than the upper surface of the first outer layer circuit pattern. Thus, the first portion of the solder resist 160 can function to support the first outer layer circuit pattern disposed in the first area, and the first portion of the solder resist 160 can function as a dam to fix the position of the adhesive member disposed in the first outer layer circuit pattern.

[0186] Meanwhile, as Figure 4c indicated, the height of the highest portion and the lowest portion of the solder resist 160a can be selectively changed.

[0187] That is, the height of the lowest portion of the solder resist 160a can have a 4' height H4' equal to the height H1 of the first outer layer circuit pattern. Also, the height of the highest portion of the solder resist 160a can have a 5' height H5' greater than the height H1 of the first outer layer circuit pattern. However, since the height of the lowest portion is equal to the first height H1 as described above, the solder resist can remain on the first outer layer circuit pattern, and thus an additional process of removing the solder resist can be required.

[0188] As shown in FIG. 1A, the height of the highest portion of the solder resist 160a can be selectively changed. Figure 4d

[0189] That is, the height of the lowest portion of the solder resist 160b can have a 4" height H4" less than the height H1 of the first outer layer circuit pattern. Also, the height of the highest portion of the solder resist 160b can have a 5" height H5" less than the height H1 of the first outer layer circuit pattern. However, as described above, when the 5" height H5" of the highest portion is less than the first height H1, the 4" height H4" is also correspondingly reduced, and thus a problem can occur in the support function in the embodiment. In addition, as described above, when the 5" height H5" of the highest portion is less than the first height H1, the dam function of the adhesive member provided on the first outer layer circuit pattern cannot be achieved, and thus a reliability problem can occur because the position of the adhesive member is changed in the state in which the adhesive member is provided.

[0190] Thus, in the embodiment, as shown in FIG. 1B, the height of the highest portion of the solder resist 160 is greater than the height of the first outer layer circuit pattern, and the height of the lowest portion of the solder resist 160 is less than the height of the first outer layer circuit pattern. Figure 4b

[0191] The circuit board in the embodiment is a multi-layered circuit board having eight or more layers and includes an outer layer circuit pattern provided on an outermost insulating layer among the multi-layers and protruding above the surface of the outer insulating layer. In this case, the outer layer circuit pattern includes a first outer layer circuit pattern provided in a first area which is an open area in which the solder resist is not provided, and a second outer layer circuit pattern located in a second area in which the solder resist is provided. In this case, the second outer layer circuit pattern can be supported and protected by the solder resist, but the first outer layer circuit pattern does not have a support layer capable of supporting the first outer layer circuit pattern, and thus there is a problem in that the first outer layer circuit pattern can easily collapse due to various factors.

[0192] ​​Accordingly, the embodiment allows a portion of the solder resist in the first area to remain without being removed, and thus is able to support and protect the first outer layer circuit pattern by the solder resist. Accordingly, the embodiment is able to solve a problem such as collapse or rubbing of the first outer layer circuit pattern in the first area by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, the embodiment is able to solve a problem such as collapse or rubbing of a trace of the first outer layer circuit pattern in the first area, thereby improving product reliability.

[0193] Meanwhile, the solder resist of the embodiment includes a first portion disposed in the first area and a second portion disposed in the second area. In this case, the upper surface of the first portion of the embodiment can have a convex shape in the upward direction. For example, an outer region of the upper surface of the first portion of the solder resist can have a fourth height, and an inner region of the upper surface of the first portion of the solder resist can have a fifth height greater than the fourth height. That is, the upper surface of the first portion of the solder resist can include a highest portion having the highest height and a lowest portion having the lowest height. Further, the lowest portion can be disposed closer to the outer layer circuit pattern than the highest portion. Accordingly, in the embodiment, the upper surface of the first portion of the solder resist can have a convex shape, and thus the surface area of the first portion of the solder resist can be increased. Accordingly, the contact surface with another layer (e.g., a molding layer) disposed on the first portion is increased, thereby improving the bonding strength. Further, the height of the lowest portion is less than the height of the first outer layer circuit pattern. Accordingly, the embodiment can prevent a portion of the first portion of the solder resist from remaining on the surface of the first outer layer circuit pattern, thereby improving reliability. Further, in the embodiment, the height of the highest portion of the first portion of the solder resist is greater than the height of the first outer layer circuit pattern. Accordingly, the embodiment can allow the dam function of the adhesive member to be implemented by the first portion of the solder resist, thereby improving reliability.

[0194] Further, the circuit board of the embodiment can be applied to a 5G communication system, and thus transmission loss of a high frequency can be minimized, thereby further improving reliability. In particular, the circuit board of the embodiment can be used at a high frequency and can reduce wave loss.

[0195] Meanwhile, in the embodiment, when the solder resist 160 is formed as described above, a portion of the solder resist 160 can be removed from the first area R1 using various methods. For example, a portion of the solder resist 160 can be removed by a physical process or a chemical process. For example, the solder resist 160 can be removed by a process such as plasma or blasting.

[0196] However, when the solder resist 160 is removed through a physical process or a chemical process, the upper outer layer circuit pattern 140 is also removed in the course of the physical process or the chemical process, such that the upper outer layer circuit pattern 140 is deformed. For example, a cross-section of the upper outer layer circuit pattern 140 can have a triangular shape because a portion thereof is removed together during the removal of the solder resist 160. In addition, when an upper portion of the upper outer layer circuit pattern 140 has a triangular shape, an adhesive member such as a solder ball cannot be stably seated on the upper outer layer circuit pattern 140, which can cause a reliability problem. In addition, expensive equipment is required to remove the protective layer through a physical or chemical process, which can increase manufacturing costs.

[0197] On the other hand, in an embodiment, the solder resist 160 can be removed by applying a thinning process using an exposure and development process to have a desired height for each region. In addition, in the exposure and development process, the upper outer layer circuit pattern 140 does not undergo deformation, and a cross-sectional shape of the upper outer layer circuit pattern 140 can maintain a rectangular shape.

[0198] Figures 7 to 14 FIG. 1 is a view showing a manufacturing method of a circuit board according to an embodiment, shown in a process order.

[0199] Referring to Figure 7 In an embodiment, first, a process for manufacturing an inner layer substrate 100-1 of an inner portion of the circuit board 100 can be performed.

[0200] The process for manufacturing the inner layer substrate 100-1 will be briefly described.

[0201] The inner layer substrate 100-1 can include one insulating layer, or alternatively, can include a plurality of insulating layers.

[0202] Figure 7 It is shown in FIG. 1 that the inner layer substrate 100-1 has an insulating layer structure including seven layers, but embodiments are not limited thereto. For example, the inner layer substrate 100-1 can include less than seven layers or more than seven layers of insulating layers.

[0203] The inner layer substrate 100-1 can include the remaining insulating layers except for the insulating layer disposed on the outermost layer of the circuit board 100. For example, the inner layer substrate 100-1 can include the insulating layer disposed on the uppermost portion of the circuit board 100 and the remaining insulating layers except for the insulating layer disposed on the lowermost portion of the circuit board 100.

[0204] The manufacturing process of the inner layer substrate 100-1 will be briefly described. First, a first insulating layer 111 is prepared.

[0205] Then, when the first insulating layer 111 is prepared, the first via V1 is formed in the first insulating layer 111, and the first circuit pattern 121 and the second circuit pattern 122 are formed on the upper and lower surfaces of the first insulating layer 111, respectively.

[0206] After that, the second insulating layer 112 is formed on the first insulating layer 111, and the third insulating layer 113 is formed below the first insulating layer 111.

[0207] Next, the second via V2 is formed in the second insulating layer 112, and the third circuit pattern 123 is formed on the upper surface of the second insulating layer 112. In addition, the third via V3 is formed in the third insulating layer 113, and the fourth circuit pattern 124 is formed below the lower surface of the third insulating layer 113.

[0208] After that, the fourth insulating layer 114 is formed on the second insulating layer 112, and the fifth insulating layer 115 is formed below the third insulating layer 113.

[0209] Next, the fourth via V4 is formed in the fourth insulating layer 114, and the fifth circuit pattern 125 is formed on the upper surface of the fourth insulating layer 114. In addition, the fifth via V5 is formed in the fifth insulating layer 115, and the sixth circuit pattern 126 is formed below the lower surface of the fifth insulating layer 115.

[0210] After that, the sixth insulating layer 116 is formed on the fourth insulating layer 114, and the seventh insulating layer 117 is formed below the fifth insulating layer 115.

[0211] Next, the sixth via V6 is formed in the sixth insulating layer 116, and the seventh circuit pattern 127 is formed on the upper surface of the sixth insulating layer 116. In addition, the seventh via V7 is formed in the seventh insulating layer 117, and the eighth circuit pattern 128 is formed below the lower surface of the seventh insulating layer 117.

[0212] Since the process of manufacturing the inner layer substrate 100-1 is a well-known technology in the technical field to which the present application pertains, a detailed description thereof will be omitted.

[0213] Referring to Figure 8 When the inner layer substrate 100-1 is manufactured, the eighth insulating layer 118 corresponding to the first outermost insulating layer is formed on the upper surface of the inner layer substrate 100-1. In addition, the ninth insulating layer 119 corresponding to the second outermost insulating layer is formed below the lower surface of the inner layer substrate 100-1.

[0214] In this case, when the eighth insulating layer 118 and the ninth insulating layer 119 are stacked, the primer layer 150 can be disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, respectively, and the metal layer 155 can be disposed on the primer layer 150. The metal layer 155 can be used to planarize the eighth insulating layer 118 and the ninth insulating layer 119 to have a uniform height. For example, the metal layer 155 can be disposed to improve the stacking reliability of the eighth insulating layer 118 and the ninth insulating layer 119.

[0215] The primer layer 150 can be used to increase the bonding force between the lower outer circuit pattern 130 and the upper outer circuit pattern 140 disposed above and below the eighth insulating layer 118 and the ninth insulating layer 119, respectively. That is, when the lower outer circuit pattern 130 and the upper outer circuit pattern 140 are disposed without the primer layer 150, the bonding force between the eighth insulating layer 118 and the upper outer circuit pattern 140 is low, and thus they can be separated from each other.

[0216] Meanwhile, Figure 8 The primer layer 150 is shown to be disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, respectively, but embodiments are not limited thereto. For example, the primer layer 150 can be selectively disposed on the surface of the insulating layer on which the fine circuit pattern is to be disposed. That is, in the case where only the lower outer circuit pattern 130 is a fine circuit pattern, the primer layer 150 can be disposed only on the lower surface of the ninth insulating layer 119. Further, in the case where only the upper outer circuit pattern 140 is a fine circuit pattern, the primer layer 150 can be disposed only on the upper surface of the eighth insulating layer 118. In addition, when both the lower outer circuit pattern 130 and the upper outer circuit pattern 140 are fine circuit patterns, the primer layer 150 can be disposed on both the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119.

[0217] Referring to Figure 9 When the eighth insulating layer 118 and the ninth insulating layer 119 are disposed, the via hole VH is formed in the eighth insulating layer 118 and the ninth insulating layer 119, respectively. In this case, the via hole VH can be formed in the primer layer 150 and the metal layer 155, respectively, as well as in the eighth insulating layer 118 and the ninth insulating layer 119, respectively.

[0218] Next, referring to Figure 10 When the via hole VH is formed, an etching process of removing the metal layer 155 disposed on the primer layer 150 can be performed. For example, after the via hole VH is formed, a flash etching process can be performed to remove the metal layer 155, and thus a process for exposing the surface of the primer layer 150 can be performed.

[0219] Next, referring to Figure 11A via V forming process for filling the via hole VH can be performed, so that the upper outer layer circuit pattern 140 can be formed on the upper surface of the eighth insulating layer 118, and the lower outer layer circuit pattern 130 can be formed on the lower surface of the ninth insulating layer 119. In this case, in the embodiment, it is shown that the lower outer layer circuit pattern 130 is a general circuit pattern rather than a fine circuit pattern, but the embodiment is not limited thereto, and the lower outer layer circuit pattern 130 as well as the second outer layer circuit pattern can be a fine circuit pattern. Thus, when the lower outer layer circuit pattern 130 is a general circuit pattern, the primer layer 150 between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 can be omitted.

[0220] The upper outer layer circuit pattern 140 is disposed on the upper surface of the eighth insulating layer 118. In this case, the upper outer layer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 includes a portion disposed in the opening region R1 of the first protective layer 160 and a portion disposed in the arrangement region R3 of the first protective layer 160. Further, a trace and a pad as a wiring for signal transmission can be disposed in each of the regions R1 and R2.

[0221] In detail, the trace 141 and the first pad 142 can be disposed in the first region R1. The first pad 142 can be a mounting pad on which a device is mounted. Further, a second pad (not shown) can be disposed in the first region R1. The second pad can be a BGA pad or a core pad. In particular, the second pad can have a width greater than that of the first pad 142.

[0222] Next, in the embodiment, the solder resist 160 (first protective layer) is disposed on the primer layer 150 to cover the upper outer layer circuit pattern 140. In this case, the solder resist layer can be disposed in both the first region R1 and the second region R2, and can be formed to have a height greater than that of the upper outer layer circuit pattern 140.

[0223] In detail, the upper outer layer circuit pattern 140 can be disposed on the insulating layer 110 at a first height H1. In this case, the insulating layer 110 can refer to an insulating layer disposed on the uppermost side of a plurality of insulating layers. However, hereinafter, for convenience of description, it will be described as the insulating layer 110. Meanwhile, the primer layer 150 can be disposed between the insulating layer 110 and the upper outer layer circuit pattern 140. In this case, the upper outer layer circuit pattern 140 can be disposed on the primer layer 150 at the first height H1. Further, the "height" described below can correspond to "thickness".

[0224] The first height H1 of the upper outer layer circuit pattern 140 can be 12 µm ± 2 µm. For example, the first height H1 of the upper outer layer circuit pattern 140 can be in the range of 10 µm to 14 µm.

[0225] The solder resist 160 can be disposed on the upper outer layer circuit pattern 140 at a predetermined height.

[0226] In this case, the solder resist 160 is disposed to cover the upper outer layer circuit pattern 140 to stably protect the upper outer layer circuit pattern 140. In this case, the height of the solder resist 160 can be 7 μm to 17 μm. When the height of the solder resist 160 is less than 7 μm, the upper outer layer circuit pattern 140 buried in the solder resist 160 cannot be stably protected from various factors. Also, when the height of the solder resist 160 is greater than 17 μm, the overall thickness of the circuit board can increase. Also, when the height of the solder resist 160 is greater than 17 μm, the manufacturing cost of the circuit board can increase.

[0227] Meanwhile, the solder resist 160 can have different heights according to positions.

[0228] That is, the solder resist 160 can be divided into a first portion disposed on the upper outer layer circuit pattern 140 and a second portion disposed on the primer layer 150. The upper surface of the first portion of the solder resist 160 can have a shape different from that of the upper surface of the second portion of the solder resist 160. For example, the upper surface of the first portion of the solder resist 160 can have a concave shape. However, embodiments are not limited thereto, and the upper surface of the first portion of the solder resist 160 can have a flat shape. For example, the upper surface of the second portion of the solder resist 160 can have a convex shape. That is, the upper surface of the second portion of the solder resist 160 can be disposed to be higher than the upper surface of the first portion of the solder resist 160.

[0229] In this case, the highest portion of the second portion of the solder resist 160 can have a second height H2. Also, the lowest portion of the first portion of the solder resist 160 can have a third height H3. In this case, each of the second height H2 and the third height H3 can be in the range of 7 μm to 17 μm.

[0230] Meanwhile, the difference ΔH between the second height H2 and the third height H3 can be in the range of 1 μm to 7 μm. For example, the third height H3 can be in the range of 80% to 97% of the second height H2. For example, the third height H3 can be in the range of 85% to 95% of the second height H2. The third height H3 can be in the range of 88% to 92% of the second height H2.

[0231] That is, the solder resist 160 includes a negative photoresist (negative PR). Also, the negative photoresist has a specific swelling phenomenon according to the environment.

[0232] For example, after the lamination process, the shape of the upper surface of the solder resist 160 can be controlled depending on the environment and the exposure time. That is, in the embodiment, after the lamination process of the solder resist 160, the degree of moisture absorption of the negative photoresist can be adjusted by controlling the environment and the exposure time to change the upper surface of the solder resist 160 into a desired shape.

[0233] At this time, the absorbed moisture in the solder resist 160 is concentrated between the circuit patterns due to the inherent high surface tension (capillary effect). For example, the absorbed moisture is more concentrated in the region where the upper outer layer circuit pattern 140 is not provided than in the region where the upper outer layer circuit pattern 140 is provided. Accordingly, the solder resist 160 has a flat shape or a concave shape in the region where the upper outer layer circuit pattern 140 is provided, and the region where the upper outer layer circuit pattern 140 is not provided has a convex shape due to the swelling phenomenon.

[0234] Next, referring to FIG. 6, a process of exposing the solder resist 160 will be described. Figure 12 In the embodiment, the exposure process can be performed. The exposure process can be performed to thin a specific region of the solder resist 160.

[0235] The exposure can be performed only on the second region R2 of the first region R1 and the second region R2 of the solder resist 160.

[0236] Here, the exposed portion is cured without being thinned in a subsequent development process.

[0237] Next, referring to FIG. 6, a process of exposing the solder resist 160 will be described. Figure 13 The development process can be performed on the uncured portion in the exposure process. In this case, the solder resist 160 formed in the developed portion can have a height exposing the upper outer layer circuit pattern 140.

[0238] The development process can include a process of thinning the unexposed region using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0239] As the above processes are performed, the solder resist 160 of the embodiment has a first portion provided in the thinned first region R1 and a second portion provided in the second region R2 which is not thinned. As described above, the second portion of the solder resist 160 has a height difference between the region where the upper outer layer circuit pattern 140 is provided and the region where the upper outer layer circuit pattern 140 is not provided due to swelling. That is, the upper surface of the second portion of the solder resist 160 has a concave shape in the region where the upper outer layer circuit pattern 140 is provided, and the upper surface of the second portion of the solder resist 160 has a convex shape in the region where the upper outer layer circuit pattern 140 is not provided.

[0240] Meanwhile, in the embodiment, as Figure 14As shown, a further process can be performed on the upper surface of the second portion of the solder resist 160. For example, the upper surface of the second portion of the solder resist 160 has different heights depending on the position, and a process of planarizing the same can be additionally performed. For example, in an embodiment, a process of polishing the upper surface of the second portion of the solder resist 160 to planarize the second portion of the solder resist 160 can be performed.

[0241] The circuit board in the embodiment is a multi-layer structure having eight or more layers and includes an outer layer circuit pattern disposed on an outermost insulating layer among the multi-layers and protruding above a surface of the outer insulating layer. In this case, the outer layer circuit pattern includes a first outer layer circuit pattern disposed in a first area which is an opening area where no solder resist is disposed, and a second outer layer circuit pattern in a second area where the solder resist is disposed. In this case, the second outer layer circuit pattern can be supported and protected by the solder resist, but the first outer layer circuit pattern has no support layer capable of supporting the first outer layer circuit pattern, and thus there is a problem that the first outer layer circuit pattern can be easily collapsed due to various factors.

[0242] Accordingly, the embodiment allows all of the solder resist in the first area to remain without being removed, and thus the first outer layer circuit pattern can be supported and protected by the solder resist. According to this, the embodiment can solve a problem such as collapse or rubbing of the first outer layer circuit pattern in the first area by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, the embodiment can solve a problem such as collapse or rubbing of a trace of the first outer layer circuit pattern in the first area, thereby improving product reliability.

[0243] Meanwhile, the solder resist in this embodiment includes a first portion disposed in a first region and a second portion disposed in a second region. In this case, the upper surface of the first portion of the embodiment may have a convex shape in the upward direction. For example, the outer region of the upper surface of the first portion of the solder resist may have a fourth height, and the inner region of the upper surface of the first portion of the solder resist may have a fifth height greater than the fourth height. That is, the upper surface of the first portion of the solder resist may include a highest portion with a highest height and a lowest portion with a lowest height. Furthermore, the lowest portion may be configured to be closer to the outer layer circuit pattern than the highest portion. Therefore, in this embodiment, the upper surface of the first portion of the solder resist may have a convex shape, thereby increasing the surface area of ​​the first portion of the solder resist. Therefore, the contact surface with the layer (e.g., a molding layer) additionally disposed on the first portion is increased, thereby improving the bonding strength. Furthermore, the height of the lowest portion is less than the height of the first outer layer circuit pattern. Therefore, this embodiment can prevent a portion of the first portion of the solder resist from remaining on the surface of the first outer layer circuit pattern, thereby improving reliability. Furthermore, in this embodiment, the height of the highest portion of the first portion of the solder resist is greater than the height of the first outer layer circuit pattern. Therefore, the embodiments may allow the dam function of the bonded component to be achieved through the first part of the solder resist, thereby improving reliability.

[0244] Furthermore, the circuit board of the embodiment can be applied to 5G communication systems, thus minimizing high-frequency transmission losses and further improving reliability. Specifically, the circuit board of the embodiment can be used at high frequencies and can reduce wave loss.

[0245] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, those skilled in the art can combine or modify the features, structures, and effects described in the various embodiments for other embodiments. Therefore, it should be understood that the content related to such combinations and modifications is included within the scope of the embodiments.

[0246] The embodiments have been mainly described above; however, these embodiments are merely examples and do not limit the scope of the embodiments. Those skilled in the art will understand that several variations and applications not mentioned above can be made without departing from the essential characteristics of the embodiments. For example, the various components specifically represented in the embodiments may be changed. Furthermore, it should be understood that differences related to such variations and applications are included within the scope of the embodiments defined by the appended claims.

Claims

1. A circuit board, comprising: Insulating layer; A circuit pattern is disposed on the insulating layer; as well as A protective layer is disposed on the circuit pattern. The protective layer comprises a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The circuit pattern includes: A first pattern portion, the first pattern portion extending through the first portion of the protective layer and exposed to the outside of the protective layer; and The second pattern portion is embedded in the second portion of the protective layer. The upper surface of the second portion of the protective layer includes a plurality of protrusions and recesses disposed between the protrusions. The plurality of protrusions and the recesses are located at a position higher than the upper surface of the second pattern portion. Wherein, the lowest end of the recess overlaps with the circuit pattern in the vertical direction, and The uppermost end of each of the plurality of protrusions overlaps with the spacing region between the plurality of patterns in the second pattern portion in the vertical direction.

2. The circuit board according to claim 1, wherein, The second portion of the protective layer has a concave portion and a plurality of convex portions having curved surfaces.

3. The circuit board according to claim 1, wherein, The insulating layer includes: A first region overlaps with the first pattern portion in the vertical direction; and The second region overlaps with the second pattern portion in the vertical direction. The first portion of the protective layer is disposed between the plurality of patterns of the first pattern portion and does not contact the upper surface of the plurality of patterns of the first pattern portion.

4. The circuit board according to claim 3, wherein, The upper surface of the first portion of the protective layer includes a plurality of protrusions disposed between the plurality of patterns in the first pattern portion.

5. The circuit board according to claim 4, wherein, The uppermost end of the first portion of the protective layer is located lower than the upper surface of the plurality of patterns of the first pattern portion.

6. The circuit board according to claim 4, wherein, The uppermost portion of the plurality of protrusions in the second portion of the protective layer does not overlap with the plurality of patterns in the second pattern portion in the vertical direction.

7. The circuit board according to claim 6, wherein, The height of the lowest portion of the concave part of the second part is in the range of 80% to 97% of the height of the uppermost portion of the convex part of the second part.

8. The circuit board according to claim 7, wherein, The difference between the height of the uppermost part of the protrusion of the second part and the height of the lowermost part of the concave part of the second part is 1 μm to 7 μm.

9. The circuit board according to claim 1, further comprising: A primer layer is disposed on the insulating layer, and The insulating layer does not contact the circuit pattern or the protective layer.

10. The circuit board according to claim 9, further comprising: Vias are configured to penetrate the primer layer and the insulating layer and connect to the circuit pattern.

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