Voltage Source Circuit

Abstract

The present invention discloses a voltage source circuit, comprising: a first NMOS tube, a first pull-down path connected between the source and the ground, a gate outputting a driving voltage, the first pull-down path having a plurality of MOS transistors connected by diodes; the gate of the first NMOS tube is connected to the drain and connected to the first current source; a driving tube composed of a second NMOS tube, the gate is connected to the driving voltage, the source is the output end of the output voltage, and a second pull-down path mirrored with the first pull-down circuit is connected between the source and the ground. The negative feedback path comprises: a sampling tube, a sampling source-drain current of the driving tube; a first mirror circuit, providing a second input current input to the drain of the first NMOS tube; the source-drain current of the first NMOS tube is formed by the superposition of the first input current and the second input current, and when the load current increases, the second input current also increases and causes the driving voltage to increase, thereby preventing the output voltage from decreasing. The present invention can prevent the output voltage from decreasing as the load current increases.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a voltage source circuit. Background Art

[0002] like Figure 1 As shown, it is a circuit diagram of an existing voltage source circuit, wherein a current source provides a current I1, and the current source is connected to a power supply voltage VCC. The current I1 flows through an NMOS tube NM100, a PMOS tube PM100, and an NMOS tube NM102 and is grounded to VSS, wherein the NMOS tube NM100 is a native NMOS tube, and a clamp voltage generated at a node ndr is Vgs_n+Vgs_p+Vgs_nz.

[0003] Wherein, Vgs_n represents the gate-source voltage of the diode-connected NMOS tube NM102, Vgs_p represents the gate-source voltage of the diode-connected PMOS tube PM100, and Vgs_n represents the gate-source voltage of the diode-connected intrinsic NMOS tube NM100.

[0004] The NMOS tube NM101 composed of native NMOS tubes is a driving tube, which is usually very large in size. The gate of the NMOS tube NM103 is connected to the gate of the NMOS tube NM102, that is, the node nbias. The NMOS tube NM103 will mirror the current of the NMOS tube NM102 as the internal load current of the NMOS tube NM101, and the generated output voltage VDD is Vgs_n+Vgs_p+Vgs_nz-Vgs_nzp, where Vgs_nzp represents the gate-source voltage of the intrinsic NMOS tube NM101 connected by a diode.

[0005] Figure 1 The voltage source shown is an open-loop structure. When the output voltage VDD is overloaded, that is, when the load current of the external load is large, the clamping voltage is used as a driving voltage to drive the NMOS tube NM101. Since the driving voltage at the node ndr remains unchanged, when the load current is large, the NMOS tube NM101 requires a larger Vgs, so the output voltage VDD will be pulled down. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a voltage source circuit which can prevent the output voltage from decreasing as the load current increases.

[0007] In order to solve the above technical problems, the voltage source circuit provided by the present invention comprises:

[0008] A first NMOS transistor, wherein a first pull-down path is connected between a source of the first NMOS transistor and a ground, and a gate of the first NMOS transistor outputs a driving voltage.

[0009] The first pull-down path has a plurality of diode-connected MOS transistors; the gate of the first NMOS transistor is connected to the drain, the drain of the first NMOS transistor is connected to a first current source, and the first current source provides a first input current of a fixed magnitude.

[0010] A driving tube composed of a second NMOS tube, wherein the gate of the driving tube is connected to the driving voltage, the source of the driving tube is the output end of the output voltage; the drain of the driving tube is connected to the power supply voltage; a second pull-down path is connected between the source of the driving tube and the ground, and the second pull-down path and the first pull-down path are mirror images of each other; the output voltage is used to provide an external load, and the source-drain current of the driving tube increases with the increase of the load current.

[0011] Negative feedback paths include:

[0012] A sampling tube, wherein the source-drain current of the sampling tube is a sampling current, and the sampling current is a mirror current of the source-drain current of the driving tube.

[0013] A first mirror circuit, wherein the first mirror circuit provides a second input current, the second input current is a mirror current of the sampling current, and the second input current is input to the drain of the first NMOS tube;

[0014] The source-drain current of the first NMOS tube is formed by the superposition of the first input current and the second input current; when the load current increases, the second input current also increases, so that the source-drain current of the first NMOS tube also increases and the gate-source voltage of the first NMOS tube increases, thereby increasing the driving voltage output by the gate of the first NMOS tube, thereby improving the driving ability of the driving tube and preventing the output voltage from decreasing as the load current increases.

[0015] A further improvement is that the negative feedback path also includes a second mirror circuit; the second mirror circuit provides a third extraction current, the third extraction current is a mirror current of the sampling current, and the third extraction current is connected to the source of the first NMOS tube.

[0016] A further improvement is that the first pull-down path includes a fourth NMOS transistor and a first PMOS transistor.

[0017] The source of the fourth NMOS tube is grounded, and the source of the first PMOS tube is connected to the source of the first NMOS tube.

[0018] The gate and drain of the fourth NMOS tube are connected to the gate and drain of the first PMOS tube.

[0019] A further improvement is that the second pull-down path includes a fifth NMOS tube, the source of the fifth NMOS tube is grounded, and the drain of the fifth NMOS tube is connected to the source of the second NMOS tube;

[0020] The gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube.

[0021] A further improvement is that the sampling tube includes a third NMOS tube;

[0022] The source of the third NMOS tube is connected to the source of the second NMOS tube;

[0023] The gate of the third NMOS tube is connected to the gate of the second NMOS tube.

[0024] A further improvement is that the first mirror circuit includes a second PMOS transistor and a third PMOS transistor.

[0025] The drain and gate of the second PMOS tube and the gate of the third PMOS tube are all connected to the drain of the third NMOS tube.

[0026] The source of the second PMOS tube and the source of the third PMOS tube are both connected to a power supply voltage.

[0027] The source of the third PMOS tube is connected to the drain of the first NMOS tube.

[0028] The source-drain current of the second PMOS tube is equal to the sampling current, and the source-drain current of the third PMOS tube is the second input current.

[0029] A further improvement is that the second mirror circuit includes a fourth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor.

[0030] The gate of the fourth PMOS tube is connected to the gate of the second PMOS tube.

[0031] The source of the fourth PMOS tube is connected to the power supply voltage.

[0032] The drain of the fourth PMOS tube, the drain and gate of the sixth NMOS tube, and the gate of the seventh NMOS tube are connected together.

[0033] The source of the sixth NMOS tube and the source of the seventh NMOS tube are both grounded.

[0034] The drain of the seventh NMOS tube is connected to the source of the first NMOS tube.

[0035] The source-drain current of the fourth PMOS tube is a mirror current of the sampling current and is equal to the source-drain current of the sixth NMOS tube.

[0036] The source-drain current of the seventh NMOS tube is the third extraction current and is a mirror current of the source-drain current of the sixth NMOS tube.

[0037] A further improvement is that the magnitude of the third extracted current is set to be less than or equal to the second input current, so that the current of the first pull-down path is greater than or equal to the first input current.

[0038] A further improvement is that a compensation capacitor is connected between the gate of the second NMOS tube and the ground.

[0039] A further improvement is that the second NMOS tube adopts an intrinsic NMOS tube.

[0040] A further improvement is that the first NMOS tube is an intrinsic NMOS tube.

[0041] A further improvement is that the channel size of the second NMOS transistor is larger than the channel size of the first NMOS transistor.

[0042] A further improvement is that the output voltage is below several volts.

[0043] A further improvement is that the maximum value of the load current reaches hundreds of microamperes.

[0044] The present invention can adopt the load current in real time by setting a sampling tube to sample the source-drain current of the driving tube. The driving voltage of the driving tube can be increased by feedback of the obtained sampling current. After the driving voltage is increased, since the source-drain current of the driving tube is determined by the difference between the driving voltage connected to the gate and the output voltage output by the source, that is, the gate-source voltage, when the driving voltage is increased, the gate-source voltage of the driving tube can be increased under the condition that the output voltage does not decrease, so that the output voltage does not decrease when the source-drain current of the driving tube increases due to the increase of the load current. Therefore, the present invention can prevent the output voltage from decreasing as the load current increases, thereby improving the driving capability for large load currents. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0046] Figure 1 is a circuit diagram of an existing voltage source circuit;

[0047] Figure 2 is a circuit diagram of a voltage source circuit according to an embodiment of the present invention;

[0048] Figure 31 is a curve showing the change of the output voltage of the embodiment of the present invention and the existing voltage source circuit with the load current. DETAILED DESCRIPTION

[0049] like Figure 2 , which is a circuit diagram of a voltage source circuit according to an embodiment of the present invention; the voltage source circuit according to an embodiment of the present invention comprises:

[0050] A first NMOS transistor NM0, a first pull-down path 102 is connected between the source of the first NMOS transistor NM0 and the ground VSS, and a gate of the first NMOS transistor NM0 outputs a driving voltage. Figure 2 In the embodiment, the node outputting the driving voltage is the node ndr.

[0051] The first pull-down path 102 has a plurality of diode-connected MOS transistors; the gate of the first NMOS transistor NM0 is connected to the drain, the drain of the first NMOS transistor NM0 is connected to the first current source 106, and the first current source 106 provides a first input current I1 of a fixed magnitude.

[0052] In the embodiment of the present invention, the second NMOS transistor NM1 is an intrinsic NMOS transistor.

[0053] The first NMOS transistor NM0 is an intrinsic NMOS transistor.

[0054] The channel size of the second NMOS transistor NM1 is larger than the channel size of the first NMOS transistor NM0. For example, the channel width of the second NMOS transistor NM1 is larger than the channel width of the first NMOS transistor NM0, the channel length of the second NMOS transistor NM1 is larger than the channel length of the first NMOS transistor NM0, and the width-to-length ratio of the channel of the second NMOS transistor NM1 is larger than the width-to-length ratio of the channel of the first NMOS transistor NM0. In this way, the driving capability of the second NMOS transistor NM1 is stronger and can be suitable for driving a larger load current.

[0055] In some embodiments, the first pull-down path 102 includes a fourth NMOS transistor NM2 and a first PMOS transistor PM0 .

[0056] A source of the fourth NMOS transistor NM2 is connected to the ground VSS, and a source of the first PMOS transistor PM0 is connected to a source of the first NMOS transistor NM0 .

[0057] The gate and drain of the fourth NMOS transistor NM2 are connected to the gate and drain of the first PMOS transistor PM0. Figure 2 In the embodiment, the gate of the fourth NMOS transistor NM2 is a node nbias.

[0058] A driving tube composed of a second NMOS tube NM1, the gate of the driving tube is connected to the driving voltage, the source of the driving tube is the output end of the output voltage VDD; the drain of the driving tube is connected to the power supply voltage VCC; a second pull-down path 103 is connected between the source of the driving tube and the ground VSS, and the second pull-down path 103 and the first pull-down path 102 are mirror images of each other; the output voltage VDD is used to provide an external load, and the source-drain current of the driving tube increases with the increase of the load current.

[0059] In some embodiments, the second pull-down path 103 includes a fifth NMOS tube NM3, the source of the fifth NMOS tube NM3 is grounded VSS, and the drain of the fifth NMOS tube NM3 is connected to the source of the second NMOS tube NM1.

[0060] The gate of the fifth NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM2.

[0061] Negative feedback paths include:

[0062] The sampling tube 101, the source-drain current of the sampling tube 101 is the sampling current, and the sampling current is the mirror current of the source-drain current of the driving tube.

[0063] In the embodiment of the present invention, the sampling tube 101 includes a third NMOS tube NM4.

[0064] The source of the third NMOS transistor NM4 is connected to the source of the second NMOS transistor NM1 .

[0065] The gate of the third NMOS transistor NM4 is connected to the gate of the second NMOS transistor NM1 .

[0066] A first mirror circuit 104, wherein the first mirror circuit 104 provides a second input current, wherein the second input current is a mirror current of the sampling current, and the second input current is input to the drain of the first NMOS tube NM0;

[0067] The source-drain current of the first NMOS tube NM0 is formed by the superposition of the first input current I1 and the second input current; when the load current increases, the second input current also increases, so that the source-drain current of the first NMOS tube NM0 also increases and the gate-source voltage of the first NMOS tube NM0 increases, thereby increasing the driving voltage output by the gate of the first NMOS tube NM0, thereby improving the driving ability of the driving tube and preventing the output voltage VDD from decreasing as the load current increases.

[0068] In the embodiment of the present invention, the first mirror circuit 104 includes a second PMOS transistor PM2 and a third PMOS transistor PM1.

[0069] The drain and gate of the second PMOS transistor PM2 and the gate of the third PMOS transistor PM1 are connected to the drain of the third NMOS transistor NM4 , that is, the node pb.

[0070] The source of the second PMOS transistor PM2 and the source of the third PMOS transistor PM1 are both connected to the power supply voltage VCC.

[0071] A source of the third PMOS transistor PM1 is connected to a drain of the first NMOS transistor NM0 .

[0072] The source-drain current of the second PMOS transistor PM2 is equal to the sampling current, and the source-drain current of the third PMOS transistor PM1 is the second input current.

[0073] In the embodiment of the present invention, the negative feedback path further includes a second mirror circuit 105; the second mirror circuit 105 provides a third extraction current, the third extraction current is a mirror current of the sampling current, and the third extraction current is connected to the source of the first NMOS tube NM0.

[0074] The second mirror circuit 105 includes a fourth PMOS transistor PM3, a sixth NMOS transistor NM5 and a seventh NMOS transistor NM6.

[0075] The gate of the fourth PMOS transistor PM3 is connected to the gate of the second PMOS transistor PM2.

[0076] The source of the fourth PMOS transistor PM3 is connected to the power supply voltage VCC.

[0077] The drain of the fourth PMOS transistor PM3, the drain and gate of the sixth NMOS transistor NM5, and the gate of the seventh NMOS transistor NM6, namely, the node nb, are connected together.

[0078] The source of the sixth NMOS transistor NM5 and the source of the seventh NMOS transistor NM6 are both connected to the ground VSS.

[0079] The drain of the seventh NMOS transistor NM6 is connected to the source of the first NMOS transistor NM0 , that is, the node vbias.

[0080] The source-drain current of the fourth PMOS transistor PM3 is a mirror current of the sampling current and is equal to the source-drain current of the sixth NMOS transistor NM5 .

[0081] The source-drain current of the seventh NMOS transistor NM6 is the third extraction current and is a mirror current of the source-drain current of the sixth NMOS transistor NM5 .

[0082] In some embodiments, a compensation capacitor Cc is connected between the gate of the second NMOS transistor NM1 and the ground VSS.

[0083] In some embodiments, the magnitude of the third extracted current is set to be less than or equal to the second input current, so that the current of the first pull-down path 102 is greater than or equal to the first input current I1.

[0084] Figure 2 In the example, the clamping voltage generated at the node ndr is Vgs_n+Vgs_p+Vgs_nz.

[0085] Wherein, Vgs_n represents the gate-source voltage of the diode-connected NMOS tube NM2, Vgs_p represents the gate-source voltage of the diode-connected PMOS tube PM0, and Vgs_n represents the gate-source voltage of the diode-connected intrinsic NMOS tube NM0.

[0086] The magnitudes of Vgs_n and Vgs_p are related to the magnitude of the current of the first pull-down path 102 . If the magnitude of the current of the first pull-down path 102 remains unchanged or increases, the magnitudes of Vgs_n and Vgs_p will also remain unchanged or increase.

[0087] Vgs_nz is related to the sum of the first input current I1 and the second input current. The larger the sum of the first input current I1 and the second input current is, the larger Vgs_nz is.

[0088] Therefore, in the embodiment of the present invention, by providing the second input current, Vgs_nz can be increased, and finally the clamping voltage generated at the node ndr, that is, the driving voltage, can be increased.

[0089] At the same time, after increasing the third extraction current, the current size of the first pull-down path 102 can be adjusted, so that the current size of the first pull-down path 102 remains unchanged, so that the sizes of Vgs_n and Vgs_p remain unchanged, and the Figure 2 The performance of the main circuit after removing the negative feedback circuit and Figure 1 The main circuit performance is consistent.

[0090] In some embodiments, the current of the first pull-down path 102 can be increased by adjusting the third extraction current, so that the driving voltage can be further increased. However, since the mirror current is proportional, the increase in the current of the first pull-down path 102 will also increase the current of the second pull-down path 103, so that Figure 2 The performance of the main circuit after removing the negative feedback circuit and Figure 1 There are certain changes in the performance of the main circuit.

[0091] In some embodiments, the current of the first pull-down path 102 can also be reduced by adjusting the third extraction current, as long as the overall increase of the driving voltage is ensured in the end.

[0092] In the embodiment of the present invention, the output voltage VDD is less than several volts.

[0093] The maximum value of the load current reaches several hundred microamperes.

[0094] The embodiment of the present invention can adopt the load current in real time by setting the sampling tube 101 to sample the source-drain current of the driving tube. The driving voltage of the driving tube can be increased by feedback through the obtained sampling current. After the driving voltage is increased, since the source-drain current of the driving tube is determined by the difference between the driving voltage connected to the gate and the output voltage VDD output by the source, that is, the gate-source voltage, when the driving voltage is increased, the gate-source voltage of the driving tube can be increased under the condition that the output voltage VDD does not decrease, so that the output voltage VDD does not decrease when the load current increases and the source-drain current of the driving tube increases. Therefore, the embodiment of the present invention can prevent the output voltage VDD from decreasing as the load current increases, thereby improving the driving capability of large load current.

[0095] like Figure 3 As shown, it is the curve of the output voltage of the embodiment of the present invention and the existing voltage source circuit changing with the load current, curve 201 is the curve of the output voltage of the existing voltage source circuit changing with the load current, and curve 202 is the curve of the output voltage of the voltage source circuit of the embodiment of the present invention changing with the load current.

[0096] The horizontal coordinates of curves 201 and 202 are the same, the vertical coordinate of curve 201 is in mV, and the vertical coordinate of curve 202 is in V. It can be seen that in curve 201, as the load current increases, the output voltage VDD gradually decreases. In curve 202, when the load current is small, the output voltage VDD drops to a minimum value, and then gradually increases as the load current increases.

[0097] From the data comparison, it can be seen that the output voltage of the voltage source circuit of the embodiment of the present invention is as low as 0.820V when the load varies in the range of 0.1uA to 500uA; the output voltage of the existing voltage source circuit is as low as 0.470V when the load varies in the range of 0.1uA to 500uA.

[0098] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A voltage source circuit, characterized in that ,include: A first NMOS transistor, wherein a first pull-down path is connected between a source of the first NMOS transistor and a ground, and a gate of the first NMOS transistor outputs a driving voltage; The first pull-down path has a plurality of diode-connected MOS transistors; the gate of the first NMOS transistor is connected to the drain, the drain of the first NMOS transistor is connected to a first current source, and the first current source provides a first input current of a fixed magnitude; A driving tube composed of a second NMOS tube, wherein the gate of the driving tube is connected to the driving voltage, the source of the driving tube is the output end of the output voltage; the drain of the driving tube is connected to the power supply voltage; a second pull-down path is connected between the source of the driving tube and the ground, and the second pull-down path and the first pull-down path are mirror images of each other; the output voltage is used to provide an external load, and the source-drain current of the driving tube increases with the increase of the load current; Negative feedback paths include: A sampling tube, wherein the source-drain current of the sampling tube is a sampling current, and the sampling current is a mirror current of the source-drain current of the driving tube; A first mirror circuit, wherein the first mirror circuit provides a second input current, the second input current is a mirror current of the sampling current, and the second input current is input to the drain of the first NMOS tube; The source-drain current of the first NMOS tube is formed by the superposition of the first input current and the second input current; when the load current increases, the second input current also increases, so that the source-drain current of the first NMOS tube also increases and the gate-source voltage of the first NMOS tube increases, thereby increasing the driving voltage output by the gate of the first NMOS tube, thereby improving the driving ability of the driving tube and preventing the output voltage from decreasing as the load current increases.

2. The voltage source circuit as claimed in claim 1, characterized in that: The negative feedback path also includes a second mirror circuit; the second mirror circuit provides a third extraction current, the third extraction current is a mirror current of the sampling current, and the third extraction current is connected to the source of the first NMOS tube.

3. The voltage source circuit as claimed in claim 2, characterized in that: The first pull-down path includes a fourth NMOS transistor and a first PMOS transistor; The source of the fourth NMOS tube is grounded, and the source of the first PMOS tube is connected to the source of the first NMOS tube; The gate and drain of the fourth NMOS tube are connected to the gate and drain of the first PMOS tube.

4. The voltage source circuit as claimed in claim 3, characterized in that: The second pull-down path includes a fifth NMOS tube, the source of the fifth NMOS tube is grounded, and the drain of the fifth NMOS tube is connected to the source of the second NMOS tube; The gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube.

5. The voltage source circuit as claimed in claim 2, characterized in that: The sampling tube includes a third NMOS tube; The source of the third NMOS tube is connected to the source of the second NMOS tube; The gate of the third NMOS tube is connected to the gate of the second NMOS tube.

6. The voltage source circuit as claimed in claim 5, characterized in that: The first mirror circuit includes a second PMOS tube and a third PMOS tube; The drain and gate of the second PMOS tube and the gate of the third PMOS tube are connected to the drain of the third NMOS tube; The source of the second PMOS tube and the source of the third PMOS tube are both connected to a power supply voltage; The source of the third PMOS tube is connected to the drain of the first NMOS tube; The source-drain current of the second PMOS tube is equal to the sampling current, and the source-drain current of the third PMOS tube is the second input current.

7. The voltage source circuit as claimed in claim 6, characterized in that: The second mirror circuit includes a fourth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The gate of the fourth PMOS tube is connected to the gate of the second PMOS tube; The source of the fourth PMOS tube is connected to the power supply voltage; The drain of the fourth PMOS tube, the drain and gate of the sixth NMOS tube, and the gate of the seventh NMOS tube are connected together; The source of the sixth NMOS tube and the source of the seventh NMOS tube are both grounded; The drain of the seventh NMOS tube is connected to the source of the first NMOS tube; The source-drain current of the fourth PMOS tube is a mirror current of the sampling current and is equal to the source-drain current of the sixth NMOS tube; The source-drain current of the seventh NMOS tube is the third extraction current and is a mirror current of the source-drain current of the sixth NMOS tube.

8. The voltage source circuit according to claim 2 or 7, characterized in that: The magnitude of the third extracted current is set to be less than or equal to the second input current, so that the current of the first pull-down path is greater than or equal to the first input current.

9. The voltage source circuit according to claim 2 or 7, characterized in that: A compensation capacitor is connected between the gate of the second NMOS tube and the ground.

10. The voltage source circuit as claimed in claim 1, characterized in that: The second NMOS tube is an intrinsic NMOS tube.

11. The voltage source circuit as claimed in claim 10, characterized in that: The first NMOS tube is an intrinsic NMOS tube.

12. The voltage source circuit according to claim 11, characterized in that: The channel size of the second NMOS transistor is larger than the channel size of the first NMOS transistor.

13. The voltage source circuit as claimed in claim 1, characterized in that: The output voltage is below several volts.

14. The voltage source circuit as claimed in claim 1, characterized in that: The maximum value of the load current reaches several hundred microamperes.

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