A method and apparatus for testing a circuit, an electronic device, and a storage medium

Abstract

The application relates to the computer technical field, and particularly relates to a circuit testing method and device, electronic equipment and storage medium, which are used for solving the problem of low testing efficiency of the existing method. The method comprises the following steps: in the process of tracking the encoder buffer based on the output of the processor, the retired instruction and the data packet generated by the retired PC, in response to the occurrence of data packet loss, the packet loss time is recorded; the data packet is analyzed, when the data packet is a starting data packet, the retired PC in the starting data packet and the corresponding packet loss time are stored into an actual PC file, and an expected PC file is generated based on the output of the processor and the output time; in this way, when the expected PC file and the actual PC file are compared, the packet loss time and the output time are used to reposition to the expected PC which is aligned with the actual PC after the packet loss in time, so that the retired PC which is aligned in time is analyzed, and the testing result of the tracking encoder is obtained, and the testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a method, apparatus, electronic device, and storage medium for testing circuits. Background Technology

[0002] With the rapid development of computer technology, before various types of software are put into use, it is necessary to test whether the central processing unit (CPU) can execute the corresponding program of the software normally. This requires reproducing all retired instruction addresses (Program Counter, PC) executed by the CPU, so as to test the software.

[0003] In related technologies, all retired PCs executed by the CPU can be reproduced through a tracking encoder. Therefore, the proper functioning of the tracking encoder circuitry directly affects the accuracy of software testing. Traditionally, the actual PC file and the expected PC file are compared to test for vulnerabilities in the tracking encoder circuitry. The expected PC file contains multiple lines of expected PCs, while the actual PC file contains multiple lines of actual PCs, no more than the total number of lines in the expected PC file. If the actual PC file and the expected PC file do not match, it indicates that the tracking encoder circuitry is malfunctioning.

[0004] However, if a First-In-First-Out (FIFO) overflow occurs during the execution of multi-loop instructions by the CPU, some retired program counters (PCs) will be discarded. Simultaneously, an error message and a sync message will be generated. The sync message indicates the starting address of the lost PCs. Because the CPU executes multiple loop instructions, there is a significant amount of PC duplication. This causes problems when comparing the actual PC file with the expected PC file, making it impossible to determine which loop the PC pointed to by the sync message belongs to. This results in frequent error outputs during the comparison process, reducing testing efficiency. Summary of the Invention

[0005] This application provides a circuit testing method, apparatus, electronic device, and storage medium to improve testing efficiency.

[0006] The specific technical solutions provided in this application are as follows:

[0007] In a first aspect, embodiments of this application provide a circuit testing method, comprising:

[0008] During the process of tracking the data packets generated by the encoder cache based on the retirement instructions and retirement instruction addresses output by the processor, in response to the occurrence of data packet loss, the time of packet loss is recorded. The time of packet loss corresponds to a starting data packet, which includes the starting address of the retirement instruction after the packet loss.

[0009] The data packet is parsed. If the data packet is the starting data packet, the retirement instruction address and the corresponding packet loss time in the starting data packet are stored in the actual instruction address file. Otherwise, the retirement instruction address in the data packet is stored in the actual instruction address file.

[0010] Generate the desired instruction address file based on the retirement instruction address and output time output by the processor;

[0011] By using the packet loss time and the output time, the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file are analyzed to obtain the test results of the tracking encoder.

[0012] In one possible implementation, the packet loss time is obtained as follows:

[0013] Detecting electrical signals within the tracking encoder, wherein the electrical signals include at least one of current signals and voltage signals;

[0014] Determine whether the electrical signal meets the circuit conditions for FIFO overflow;

[0015] If so, the detection time of the electrical signal is recorded, and the detection time is determined as the packet loss time.

[0016] In one possible implementation, recording the packet loss time includes:

[0017] The packet loss times are recorded in the packet loss time file in chronological order of their acquisition.

[0018] Before storing the retirement instruction address and corresponding packet loss time in the initial data packet to the actual instruction address file, the method further includes:

[0019] Determine the sorting information of the starting data packet in the starting data packet sequence;

[0020] Obtain the packet loss time corresponding to the sorting information from the packet loss time file.

[0021] In one possible implementation, the output time is obtained as follows:

[0022] Monitor the processor's kernel;

[0023] When the kernel outputs the address of the retirement instruction, the time of the output is recorded.

[0024] In one possible implementation, the step of analyzing the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file using the packet loss time and the output time to obtain the test results of the tracking encoder includes:

[0025] Starting from the first line of the actual instruction address file, the actual instruction addresses in the actual instruction address file and the expected instruction addresses in the expected instruction address file are compared sequentially.

[0026] If there is a packet loss moment at the actual instruction address to be compared, then the packet loss moment is compared with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. The reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address.

[0027] The expected instruction address corresponding to the output time that is the same as the packet loss time is used as the new comparison start address, and the comparison start address is compared with the actual instruction address, and the comparison is performed sequentially from the actual instruction address;

[0028] After comparing the last row, the circuit function of the tracking encoder is analyzed based on the comparison results to obtain the test results of the tracking encoder.

[0029] In one possible implementation, the step of analyzing the circuit function of the tracking encoder based on the comparison results to obtain the test results of the tracking encoder includes:

[0030] If the comparison results show inconsistencies, it is determined that the test result of the tracking encoder indicates that the circuit function is incorrect.

[0031] If the comparison results are consistent, then the test result of the tracking encoder is determined to be that the circuit function is correct.

[0032] Secondly, an embodiment of this application provides a circuit testing apparatus, comprising:

[0033] The time recording unit is used to record the time of packet loss in response to packet loss during the process of tracking the data packets generated by the encoder cache based on the retirement instructions and retirement instruction addresses output by the processor. The time of packet loss corresponds to a starting data packet, and the starting data packet includes the starting address of the retirement instruction after the packet loss.

[0034] The parsing unit is used to parse the data packet. When the data packet is the starting data packet, it stores the retirement instruction address and the corresponding packet loss time in the starting data packet into the actual instruction address file; otherwise, it stores the retirement instruction address in the data packet into the actual instruction address file.

[0035] The expected instruction address file generation unit is used to generate an expected instruction address file based on the retirement instruction address and output time output by the processor.

[0036] The analysis unit is used to analyze the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file using the packet loss time and the output time, and to obtain the test results of the tracking encoder.

[0037] In one possible implementation, the packet loss time is obtained as follows:

[0038] Detecting electrical signals within the tracking encoder, wherein the electrical signals include at least one of current signals and voltage signals;

[0039] Determine whether the electrical signal meets the circuit conditions for FIFO overflow;

[0040] If so, the detection time of the electrical signal is recorded, and the detection time is determined as the packet loss time.

[0041] In one possible implementation, the time recording unit is used to: record the packet loss times in the order they were obtained into a packet loss time file;

[0042] The parsing unit is further configured to: determine the sorting information of the starting data packet in the starting data packet sequence before storing the retirement instruction address and the corresponding packet loss time in the starting data packet to the actual instruction address file; and obtain the packet loss time corresponding to the sorting information from the packet loss time file.

[0043] In one possible implementation, the output time is obtained as follows:

[0044] Monitor the processor's kernel;

[0045] When the kernel outputs the address of the retirement instruction, the time of the output is recorded.

[0046] In one possible implementation, the analysis unit is specifically used for:

[0047] Starting from the first line of the actual instruction address file, the actual instruction addresses in the actual instruction address file and the expected instruction addresses in the expected instruction address file are compared sequentially.

[0048] If there is a packet loss moment at the actual instruction address to be compared, then the packet loss moment is compared with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. The reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address.

[0049] The expected instruction address corresponding to the output time that is the same as the packet loss time is used as the new comparison start address, and the comparison start address is compared with the actual instruction address, and the comparison is performed sequentially from the actual instruction address;

[0050] After comparing the last row, the circuit function of the tracking encoder is analyzed based on the comparison results to obtain the test results of the tracking encoder.

[0051] In one possible implementation, the analysis unit is specifically used for:

[0052] If the comparison results show inconsistencies, it is determined that the test result of the tracking encoder indicates that the circuit function is incorrect.

[0053] If the comparison results are consistent, then the test result of the tracking encoder is determined to be that the circuit function is correct.

[0054] Thirdly, an electronic device provided in this application includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of any of the above methods.

[0055] Fourthly, embodiments of this application provide a computer-readable storage medium including a computer program, which, when run on an electronic device, causes the electronic device to perform the steps of any of the methods described above.

[0056] Fifthly, embodiments of this application provide a computer program product, the computer program product including a computer program stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, causing the electronic device to perform the steps of any of the above methods.

[0057] The beneficial effects of this application are as follows:

[0058] This application provides a circuit testing method, apparatus, electronic device, and storage medium. The circuit testing method provided by this application allows for accurate relocation of the expected instruction address, which is time-aligned with the actual instruction address after packet loss, during the comparison of the expected instruction address file and the actual instruction address file in a CPU multi-loop instruction execution scenario. This improves testing efficiency, especially if a FIFO overflow occurs during the comparison. The method utilizes the packet loss time and the output time to smoothly perform the comparison check.

[0059] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of an application scenario in an embodiment of this application;

[0061] Figure 2 This is a schematic diagram of the circuit test architecture for a circuit test method according to an embodiment of this application;

[0062] Figure 3 This is a flowchart illustrating a circuit testing method according to an embodiment of this application;

[0063] Figure 4 This is a schematic diagram of a process for obtaining the packet loss time in an embodiment of this application;

[0064] Figure 5 This is a schematic diagram illustrating a process for obtaining packet loss times from a packet loss time file in an embodiment of this application;

[0065] Figure 6 This is a schematic diagram of an actual PC file in an embodiment of this application;

[0066] Figure 7 This is a schematic diagram of a process for determining the output time in an embodiment of this application;

[0067] Figure 8 This is a schematic diagram of a desired PC file in an embodiment of this application;

[0068] Figure 9 This is a schematic diagram of a process for comparing and analyzing actual PC files and expected PC files in an embodiment of this application;

[0069] Figure 10 This is a schematic diagram illustrating a relocation of a new comparison starting address in an embodiment of this application;

[0070] Figure 11 This is a schematic diagram of the logic architecture of a circuit testing device according to an embodiment of this application;

[0071] Figure 12 This is a schematic diagram of the composition structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only some embodiments of the technical solutions of this application, and not all embodiments. Based on the embodiments recorded in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this application.

[0073] The following explanations of some terms used in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0074] (1) In the embodiments of this application, the term "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0075] (2) The term “retirement instruction” in the embodiments of this application, also known as “retirement instruction”, is a CPU instruction, such as retired, which is used to indicate that the instruction has completed all operations and exited normally.

[0076] (3) In the embodiments of this application, the term “retirement instruction address” is the instruction address (PC) corresponding to the retirement instruction.

[0077] (4) In the embodiments of this application, the term “Trace Encoder” is used to reproduce all retired PCs executed by the CPU.

[0078] In this embodiment, the trace encoder generates a data packet from the retirement instructions and retirement PC output by the CPU based on the trace protocol, and caches the data packet. The trace decoder corresponding to the trace encoder retrieves the data packet from the cache and decodes it based on the trace protocol to obtain the corresponding actual PC file, so as to reproduce all instruction PCs executed by the CPU.

[0079] For example, the trace protocol mentioned above could be the Nexus 5001 Forum™ Standard protocol, and the data packets generated by the trace encoder compression are called Nexus Public Messages.

[0080] (5) In the embodiments of this application, the term “sync message” is generated by the tracking encoder when a data packet is lost (e.g., FIFO overflow) and is used to point to the starting address of the PC after some data packets are dropped.

[0081] In related technologies, when the tracking encoder reaches the maximum buffer size in the buffer (e.g., FIFO memory), a FIFO overflow occurs, generating an error message and a sync message. The error message informs the tracking decoder that a FIFO overflow has occurred and some data packets have been discarded. The sync message informs the tracking encoder that the PCs discarded after the sync message should start from the PC pointed to by the sync message.

[0082] The design concept of the embodiments of this application is briefly introduced below:

[0083] In related technologies, if the tracking encoder experiences data packet loss, such as FIFO overflow, during the execution of multi-loop instructions, the CPU will discard some retired PCs and generate error messages and sync messages. The error message indicates that the tracking encoder has experienced FIFO overflow or other data packet loss; the sync message indicates the starting address of the PC after the loss.

[0084] However, when comparing the actual PC file with the expected PC file, there are often situations where the actual PC file contains the actual PCs that have been compared, but the expected PC file still contains multiple expected PCs that have not been compared, resulting in an error output. Or, the comparison process cannot be carried out smoothly, resulting in frequent error outputs, which leads to low testing efficiency.

[0085] Through extensive analysis, the inventors discovered that the reason for the low efficiency of the above tests is that during the execution of multi-loop instructions by the CPU, the PC will be repeated a lot. In the process of comparing the actual PC file and the expected PC file, it is impossible to determine which loop the PC pointed to by the syncmessage is in, and it is also impossible to determine whether the data packets discarded by the tracking encoder also contain the same PC pointed to by the sync message. Therefore, frequent output errors are caused.

[0086] In view of this, embodiments of this application propose a circuit testing method, apparatus, electronic device, and storage medium. In this embodiment, during the process of a tracking encoder buffering data packets generated based on the retirement instructions and retirement instruction addresses output by the processor, in response to data packet loss, the packet loss time is recorded. The packet loss time corresponds to a starting data packet, which includes the starting address of the retirement instruction after the packet loss. Then, the data packet is parsed. If the data packet is a starting data packet, the retirement instruction address and the corresponding packet loss time within the starting data packet are stored in the actual instruction address file; otherwise, the retirement instruction address within the data packet is stored in the actual instruction address file. Furthermore, a desired instruction address file is generated based on the retirement instruction address and output time output by the processor. Thus, when comparing the desired instruction address file and the actual instruction address file, the time-aligned retirement instruction addresses in the actual instruction address file and the desired instruction address file are analyzed using the packet loss time and the output time, thereby obtaining the test result of the tracking encoder.

[0087] The testing method using the circuit provided in this application embodiment can, in the scenario of CPU executing multiple loop instructions, if the tracking encoder has experienced data packet loss during the comparison of the expected instruction address file and the actual instruction address file, the expected instruction address that is time-aligned with the actual instruction address after the packet loss can be accurately located using the packet loss time and the output time, thereby successfully performing the comparison check and improving the testing efficiency.

[0088] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0089] Before describing the circuit testing method provided in the embodiments of this application, a brief overview of the application scenarios of the embodiments of this application will be given first.

[0090] Figure 1 This illustration shows an application scenario provided by an embodiment of this application. (See attached diagram.) Figure 1 As shown, this application scenario includes an electronic device 100. The electronic device 100 contains a CPU circuit. After the core circuit in the CPU circuit executes the instructions, it outputs a retirement instruction and a retirement PC. Based on the retirement instruction and the retirement PC, a desired PC file and an actual PC file are generated, thereby realizing the circuit function detection of the tracking encoder.

[0091] For example, the electronic device can be a smart mobile terminal, tablet computer, laptop computer, desktop computer, etc. The electronic device can be equipped with a circuit testing device, which can be... Figure 1 The software virtual device shown may also be an external device; this application does not impose any specific limitations on it.

[0092] It should be noted that the above application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementation of this application is not limited in any way.

[0093] Figure 2 This diagram illustrates a circuit test architecture for a circuit testing method provided in an embodiment of this application. In this embodiment, see [reference needed]. Figure 2 As shown, the circuit test architecture described above is applicable to the aforementioned electronic device, including a processor (e.g., CPU) circuit and a trace decoder model. The CPU circuit consists of a core circuit and a trace encoder circuit. In this method, the trace encoder is the Design Under Test (DUT), and the trace decoder model is a pre-written decoder model used to parse the data packets output by the trace encoder based on the trace protocol used with the trace encoder.

[0094] It should be noted that, Figure 2 The test cases shown are merely examples and are not intended to be specific limitations in this application. These test cases can be at least one of the following: historical test cases of a tested kernel and newly written test cases. The test cases can be written in C or assembly language, etc. Historical test cases of a tested kernel refer to test cases used to test whether the kernel circuitry functions correctly. These test cases can be used to test whether the trace encoder's circuitry functions correctly, such as test cases for multi-loop instructions. Newly written test cases refer to test cases written to test whether the trace encoder's circuitry functions correctly, such as test cases for abnormal conditions.

[0095] In this embodiment of the application, when compiling test cases into instruction files, the test cases can be compiled into instruction files using the GNU Compiler Collection (GCC), for example, the generated instruction files are ELF files.

[0096] Compiling test cases into a disassembled file refers to disassembling the instruction file generated by compiling the test cases using a command-line tool. For example, an ELF file can be disassembled using a command-line tool (objdump) to generate a disassembled file.

[0097] After introducing the application scenarios and circuit test architecture diagrams of the embodiments of this application, please refer to... Figure 3 The flowchart shown is an implementation diagram of a circuit testing method provided in this application embodiment. The specific implementation process of this method is as follows:

[0098] Step 300: During the process of tracking the encoder cache data packets generated based on the processor output retirement instructions and retirement instruction addresses, record the time of packet loss in response to the occurrence of data packet loss.

[0099] In related technologies, tracing encoders are used to reproduce the retired PCs of a processor. For linear PC streams output by the processor's instruction file, the tracing encoder typically only needs to record the first and last retired PCs in the linear instruction stream to completely reproduce the processor's retired PC stream. For non-linear PC streams output by the processor, the tracing encoder typically needs to record the first retired PC, the retired PCs corresponding to each turning point, and the last retired PC in the non-linear instruction stream to reproduce the processor's retired PC stream. Therefore, when the number of retired instructions output by the processor is small and the tracing encoder has sufficient cache, the data packets generated by the tracing encoder based on the retired instructions and retired PCs output by the processor's core circuits can be cached sequentially, and then each data packet can be parsed by a tracing decoder model that matches the tracing encoder, thereby successfully reproducing the retired PC stream of the instruction file executed by the processor.

[0100] However, processors typically need to process a large number of instructions, resulting in a large number of retired program counters (PCs) being output by the processor's core circuitry. These retired PCs correspond to a large number of data packets that need to be buffered, which can easily cause the trace encoder's buffer to reach its maximum capacity. When the trace encoder's buffer reaches its maximum capacity, a FIFO overflow will occur in the trace encoder running in loop mode. At this point, the trace encoder will discard some data packets and, based on the trace protocol, generate error and sync messages. These error and sync messages are then compressed to generate the initial data packet, which is then buffered.

[0101] Since the FIFO overflow of the tracking encoder is caused by the circuit's own buffer reaching its maximum buffer size, therefore, in the embodiments of this application, refer to... Figure 4 As shown, during step 300, in the process of caching the data packet generated based on the processor output retirement instruction and retirement instruction address in the encoder, the moment of packet loss can be obtained in the following way:

[0102] Step 3001: Detect an electrical signal within the tracking encoder, wherein the electrical signal includes at least one of a current signal and a voltage signal.

[0103] Step 3002: Determine whether the electrical signal meets the circuit conditions for FIFO overflow.

[0104] Step 3003: If yes, record the detection time of the electrical signal and determine the detection time as the packet loss time.

[0105] Thus, during the process of tracking encoder buffering data packets, by executing steps 3001 to 3003, the electrical signal of the tracking encoder is detected through the backdoor. Based on the electrical signal, it can be identified whether the tracking encoder has or is about to experience a FIFO overflow. Then, after determining that the electrical signal in the tracking encoder meets the circuit conditions for FIFO overflow, the time at this moment is recorded, thereby determining the generation time corresponding to the initial data packet, i.e., the packet loss time. Then, the packet loss time is recorded in the packet loss time file in the order of the obtained time to complete the operation of recording the packet loss time in step 300.

[0106] Step 310: Parse the data packet. If the data packet is a starting data packet, store the retirement instruction address and the corresponding packet loss time in the starting data packet to the actual instruction address file. Otherwise, store the retirement instruction address in the data packet to the actual instruction address file.

[0107] In this embodiment of the application, when executing step 310, the tracing decryptor model is invoked to parse the data packet. If the parsed data packet is the aforementioned starting data packet, that is, the starting data packet obtained by compressing the generated error message and sync message after the tracing encoder loses a data packet, then the retirement PC obtained by parsing the starting data packet and the packet loss time corresponding to the starting address are stored in the actual PC file. If the parsed data packet is a data packet generated by the tracing encoder based on the retirement instruction and retirement PC output by the processor, then the parsed retirement PC is stored in the actual PC file.

[0108] For specific implementation details, please refer to... Figure 5 As shown, before storing the retirement instruction address and corresponding packet loss time in the initial data packet to the actual instruction address file in step 310, the packet loss time corresponding to the retirement instruction address in the initial data packet is obtained in the following way:

[0109] Step 500: Determine the sorting information of the starting data packet in the starting data packet sequence.

[0110] In this embodiment of the application, when performing step 500, the sorting information of the currently parsed starting data packet in the sequence of parsed starting data packets is determined, that is, the number of the parsed starting data packets that the currently parsed starting data packet is.

[0111] Step 510: Obtain the packet loss time corresponding to the sorting information from the packet loss time file.

[0112] In this embodiment of the application, since each packet loss time in the packet loss time file is sorted in the order of acquisition, when executing step 510, the packet loss time corresponding to the sorting information of the currently parsed starting data packet determined in step 500 is obtained from the packet loss time file. This packet loss time is the time when the starting data packet was generated, that is, the time when the tracking encoder experienced FIFO overflow.

[0113] In this embodiment of the application, a complete actual PC file can be obtained by performing step 310. Figure 6 This shows a portion of the actual PC from the complete actual PC file. See also... Figure 6 As shown, compared with the actual PC file obtained under the existing technology, the PC pointed to by the sync message is marked with the recorded packet loss time, such as 8000_0100,240.

[0114] Step 320: Generate the desired instruction address file based on the retirement instruction address and output time of the processor.

[0115] Under related technologies, a desired PC file can be generated based on the retired PC output by the processor. In the embodiments of this application, see [reference needed]. Figure 7 As shown, before generating the desired PC file, the output time corresponding to the retirement PC of each processor is obtained in the following way:

[0116] Step 600: Listen to the processor kernel.

[0117] Step 610: When the kernel outputs the retirement instruction address, record the output time.

[0118] In specific implementation, when step 610 is executed, when the kernel outputs the retired PC, the time at that moment is recorded as the output time corresponding to the retired PC.

[0119] Then, in this embodiment of the application, when performing step 320, during the process of the processor executing the instruction file, a retirement PC and output time of the processor output to the tracking encoder can be obtained. The retirement PC and output time are then stored in the expected instruction address file until the last retirement PC and output time are obtained, thereby obtaining a complete expected PC file.

[0120] Figure 8 This shows a portion of the expected PC from the complete expected PC file and a portion of the actual PC from the actual PC file. See also... Figure 8 As shown, compared with the expected PC file obtained under the prior art, the corresponding output time is marked after each expected PC, such as 8000_0100,240 in the second loop.

[0121] Step 330: Using the packet loss time and output time, analyze the retirement instruction addresses that are time-aligned in the actual instruction address file and the expected instruction address file to obtain the test results of the tracking encoder.

[0122] In this embodiment of the application, by executing steps 300 to 320, the processor execution instruction file, the actual PC file, and the expected PC file are obtained. Then, refer to... Figure 9 As shown, step 330 is implemented by performing the following steps:

[0123] Step 3301: Starting from the first line of the actual instruction address file, compare the actual instruction address in the actual instruction address file with the expected instruction address in the expected instruction address file.

[0124] Step 3302: If there is a packet loss moment at the actual instruction address to be compared, then compare the packet loss moment with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. Here, the reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address.

[0125] In this embodiment of the application, the above-mentioned actual instruction address has a packet loss time to indicate that the actual PC is the starting PC after the tracking encoder loses packets, that is, the PC pointed to by the sync message.

[0126] Therefore, when executing step 3302, based on the packet loss time corresponding to the actual PC, the output time of each line of expected PC after the reference PC in the expected PC file is compared to obtain the output time that is the same as the packet loss time. That is, the expected PC that is time-aligned with the actual PC is queried from the expected PC file. The reference PC is the expected PC that is compared with the actual PC in the previous line of the actual PC.

[0127] Step 3303: Take the expected instruction address corresponding to the same output time as the packet loss time as the new comparison start address, compare the comparison start address with the actual instruction address, and start the comparison from the actual instruction address and proceed sequentially.

[0128] In this embodiment of the application, when performing step 3303, the expected PC that is time-aligned with the actual PC obtained in step 3302 is used as the new comparison start address, and the comparison start address (i.e., the expected PC corresponding to the output time that is the same as the packet loss time) is compared with the actual PC, and each subsequent expected PC and each actual PC are compared in turn.

[0129] See Figure 10 As shown, assuming the actual PC file obtained is as follows: Figure 6As shown, the expected PC file obtained is as follows Figure 8 As shown.

[0130] So, see Figure 10 As shown in this embodiment, the actual PC file and the expected PC file are compared. When the comparison reaches the actual PC: 8000_0100, 240, it is determined that the actual PC marks the packet loss time, i.e., 240. Therefore, it can be determined that packet loss occurred before "8000_0100, 240" in the actual PC file. "8000_0100, 240" is the starting PC redefined by the tracking encoder after the packet loss. Then, based on the packet loss time, the output time of each line of expected PC after "8000_0120, 220" in the expected PC file is compared to obtain the expected PC corresponding to the same output time as the packet loss time 240.

[0131] If, by comparing the packet loss time and the output time, the "8000_0100,240" in the second loop is found to have the same time as the actual PC marked with the packet loss time, then "8000_0100,240" is taken as the new comparison starting address, and the comparison is performed sequentially from this comparison starting address.

[0132] In some feasible embodiments, if the actual PC at the time of packet loss is compared again, the above method is still used to determine a new comparison start address until the last line is compared, thereby obtaining the test results of the tracking encoder.

[0133] In this way, after comparing the actual PC corresponding to the starting data packet generated based on the error message and the sync message, the starting address of the subsequent comparison can be located based on the packet loss time and the output time. This allows for the smooth and quick determination of the new starting position of the subsequent comparison, so as to continue comparing the subsequent PCs and quickly obtain the comparison results, which greatly improves the testing efficiency.

[0134] Step 3304: After comparing the last row, analyze the circuit function of the tracking encoder based on the comparison results to obtain the test results of the tracking encoder.

[0135] In this embodiment of the application, when performing step 3304, after comparing the last row, a comparison result is obtained. Then, based on the comparison result, the circuit function of the tracking encoder is analyzed to obtain the test result of the tracking encoder.

[0136] In some possible embodiments, if there is an inconsistency in the comparison results, it is determined that the test result of the tracking encoder is that the circuit function is incorrect.

[0137] In some other possible embodiments, if the comparison results are consistent, the test result of the tracking encoder is determined to be that the circuit function is correct.

[0138] Based on the same inventive concept, see [reference] Figure 11 As shown in the illustration, this application also provides a circuit testing apparatus, comprising:

[0139] The time recording unit 1110 is used to record the time of packet loss in response to packet loss during the process of tracking the data packets generated by the encoder cache based on the retirement instructions and retirement instruction addresses output by the processor. The time of packet loss corresponds to a starting data packet, and the starting data packet includes the starting address of the retirement instruction after the packet loss.

[0140] The parsing unit 1120 is used to parse the data packet. When the data packet is the starting data packet, it stores the retirement instruction address and the corresponding packet loss time in the starting data packet to the actual instruction address file; otherwise, it stores the retirement instruction address in the data packet to the actual instruction address file.

[0141] The expected instruction address file generation unit 1130 is used to generate an expected instruction address file based on the retirement instruction address and output time output by the processor.

[0142] Analysis unit 1140 is used to analyze the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file using the packet loss time and the output time, and obtain the test results of the tracking encoder.

[0143] In one possible implementation, the packet loss time is obtained as follows:

[0144] Detecting electrical signals within the tracking encoder, wherein the electrical signals include at least one of current signals and voltage signals;

[0145] Determine whether the electrical signal meets the circuit conditions for FIFO overflow;

[0146] If so, the detection time of the electrical signal is recorded, and the detection time is determined as the packet loss time.

[0147] In one possible implementation, the time recording unit 1110 is used to: record the packet loss time into a packet loss time file in the order in which the time was obtained;

[0148] The parsing unit 1120 is further configured to: determine the sorting information of the starting data packet in the starting data packet sequence before storing the retirement instruction address and the corresponding packet loss time in the starting data packet to the actual instruction address file; and obtain the packet loss time corresponding to the sorting information from the packet loss time file.

[0149] In one possible implementation, the output time is obtained as follows:

[0150] Monitor the processor's kernel;

[0151] When the kernel outputs the address of the retirement instruction, the time of the output is recorded.

[0152] In one possible implementation, the analysis unit 1140 is specifically used for:

[0153] Starting from the first line of the actual instruction address file, the actual instruction addresses in the actual instruction address file and the expected instruction addresses in the expected instruction address file are compared sequentially.

[0154] If there is a packet loss moment at the actual instruction address to be compared, then the packet loss moment is compared with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. The reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address.

[0155] The expected instruction address corresponding to the output time that is the same as the packet loss time is used as the new comparison start address, and the comparison start address is compared with the actual instruction address, and the comparison is performed sequentially from the actual instruction address;

[0156] After comparing the last row, the circuit function of the tracking encoder is analyzed based on the comparison results to obtain the test results of the tracking encoder.

[0157] In one possible implementation, the analysis unit 1140 is specifically used for:

[0158] If the comparison results show inconsistencies, it is determined that the test result of the tracking encoder indicates that the circuit function is incorrect.

[0159] If the comparison results are consistent, then the test result of the tracking encoder is determined to be that the circuit function is correct.

[0160] For ease of description, the above sections are divided into modules (or units) according to their functions and described separately. Of course, in implementing this application, the functions of each module (or unit) can be implemented in one or more software or hardware components.

[0161] After introducing the test method and apparatus for the circuits of exemplary embodiments of this application, the electronic device according to another exemplary embodiment of this application will be introduced next.

[0162] Those skilled in the art will understand that various aspects of this application can be implemented as a system, method, or program product. Therefore, various aspects of this application can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, collectively referred to herein as a "circuit," "module," or "system."

[0163] Based on the same inventive concept, this application also provides an electronic device, the structure of which can be as follows: Figure 12 As shown, it includes a memory 1201 and one or more processors 1202.

[0164] The memory 1201 is used to store computer programs executed by the processor 1202. The memory 1201 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required for running circuit testing functions, etc.; the data storage area may store packet loss times and output times, etc.

[0165] Memory 1201 may be volatile memory, such as random-access memory (RAM); memory 1201 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 1201 may be any other medium capable of carrying or storing a desired computer program having the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 1201 may be a combination of the above-described memories.

[0166] Processor 1202 may include one or more CPUs or digital processing units, etc. Processor 1202 is used to implement the above method when calling a computer program stored in memory 1201.

[0167] This application embodiment does not limit the specific connection medium between the memory 1201 and the processor 1202 described above. This application embodiment... Figure 12 The memory 1201 and the processor 1202 are connected via a bus 1203, and the bus 1203 is in Figure 12The diagram uses thick lines to describe the connections between other components; these are for illustrative purposes only and should not be considered limiting. Bus 1203 can be divided into address bus, data bus, control bus, etc. For ease of description, Figure 12 It is described using only a thick line, but does not indicate that there is only one bus or one type of bus.

[0168] The memory 1201 contains a computer storage medium storing computer-executable instructions for implementing the methods of the embodiments of this application. The processor 1202 is used to execute the methods of the various embodiments described above, such as... Figure 3 As shown.

[0169] In some possible implementations, various aspects of the circuit testing method provided in this application can also be implemented in the form of a program product, which includes a computer program. When the program product is run on an electronic device, the computer program is used to cause the electronic device to perform the steps of the methods described above according to the various exemplary embodiments of this application. For example, the electronic device can perform actions such as... Figure 3 The steps are shown in the figure.

[0170] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0171] The program product of the embodiments of this application may employ a portable compact disc read-only memory (CD-ROM) and include a computer program, and may run on a computing device. However, the program product of this application is not limited thereto. In this document, the readable storage medium may be any tangible medium that contains or stores a program that may be used by or in conjunction with a command execution system, apparatus, or device.

[0172] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a readable computer program. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting a program for use by or in conjunction with a command execution system, apparatus, or device.

[0173] Computer programs contained on readable media may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0174] Computer programs for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The computer program can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0175] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0176] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0177] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing a computer-usable computer program.

[0178] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0179] These computer program commands may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the commands stored in the computer-readable storage medium produce an article of manufacture including command means that implement the functions specified in one or more processes in a flowchart and / or one or more blocks in a block diagram.

[0180] These computer program commands may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the commands executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0181] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0182] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for testing a circuit, characterized in that, include: During the process of tracking the data packets generated by the encoder cache based on the retirement instructions and retirement instruction addresses output by the processor, in response to the occurrence of data packet loss, the time of packet loss is recorded. The time of packet loss corresponds to a starting data packet, which includes the starting address of the retirement instruction after the packet loss. The data packet is parsed. If the data packet is the starting data packet, the retirement instruction address and the corresponding packet loss time in the starting data packet are stored in the actual instruction address file. Otherwise, the retirement instruction address in the data packet is stored in the actual instruction address file. Generate the desired instruction address file based on the retirement instruction address and output time output by the processor; Using the packet loss time and the output time, analyze the retirement instruction addresses that are time-aligned in the actual instruction address file and the expected instruction address file to obtain the test results of the tracking encoder; The step of analyzing the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file using the packet loss time and the output time to obtain the test results of the tracking encoder includes: Starting from the first line of the actual instruction address file, the actual instruction addresses in the actual instruction address file and the expected instruction addresses in the expected instruction address file are compared sequentially. If there is a packet loss moment at the actual instruction address to be compared, then the packet loss moment is compared with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. The reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address. The expected instruction address corresponding to the output time that is the same as the packet loss time is used as the new comparison start address, and the comparison start address is compared with the actual instruction address, and the comparison is performed sequentially from the actual instruction address; After comparing the last row, the circuit function of the tracking encoder is analyzed based on the comparison results to obtain the test results of the tracking encoder.

2. The method as described in claim 1, characterized in that, The packet loss time is obtained as follows: Detecting electrical signals within the tracking encoder, wherein the electrical signals include at least one of current signals and voltage signals; Determine whether the electrical signal meets the circuit conditions for FIFO overflow; If so, the detection time of the electrical signal is recorded, and the detection time is determined as the packet loss time.

3. The method as described in claim 2, characterized in that, The recorded packet loss time includes: The packet loss times are recorded in the packet loss time file in chronological order of their acquisition. Before storing the retirement instruction address and corresponding packet loss time in the initial data packet to the actual instruction address file, the method further includes: Determine the sorting information of the starting data packet in the starting data packet sequence; Obtain the packet loss time corresponding to the sorting information from the packet loss time file.

4. The method as described in claim 1, characterized in that, The output time is obtained in the following way: Monitor the processor's kernel; When the kernel outputs the address of the retirement instruction, the time of the output is recorded.

5. The method according to any one of claims 1-4, characterized in that, The analysis of the circuit function of the tracking encoder based on the comparison results to obtain the test results of the tracking encoder includes: If the comparison results show inconsistencies, it is determined that the test result of the tracking encoder indicates that the circuit function is incorrect. If the comparison results are consistent, then the test result of the tracking encoder is determined to be that the circuit function is correct.

6. A circuit testing device, characterized in that, include: The time recording unit is used to record the time of packet loss in response to packet loss during the process of tracking the data packets generated by the encoder cache based on the retirement instructions and retirement instruction addresses output by the processor. The time of packet loss corresponds to a starting data packet, and the starting data packet includes the starting address of the retirement instruction after the packet loss. The parsing unit is used to parse the data packet. When the data packet is the starting data packet, it stores the retirement instruction address and the corresponding packet loss time in the starting data packet into the actual instruction address file; otherwise, it stores the retirement instruction address in the data packet into the actual instruction address file. The expected instruction address file generation unit is used to generate an expected instruction address file based on the retirement instruction address and output time output by the processor. The analysis unit is used to analyze the time-aligned retirement instruction addresses in the actual instruction address file and the expected instruction address file using the packet loss time and the output time, to obtain the test results of the tracking encoder; wherein, the analysis unit is specifically used for: Starting from the first line of the actual instruction address file, the actual instruction addresses in the actual instruction address file and the expected instruction addresses in the expected instruction address file are compared sequentially. If there is a packet loss moment at the actual instruction address to be compared, then the packet loss moment is compared with the output moment of each line of expected instruction address after the reference instruction address until the output moment that is the same as the packet loss moment is obtained. The reference instruction address is the expected instruction address that is compared with the line of actual instruction address before the actual instruction address. The expected instruction address corresponding to the output time that is the same as the packet loss time is used as the new comparison start address, and the comparison start address is compared with the actual instruction address, and the comparison is performed sequentially from the actual instruction address; After comparing the last row, the circuit function of the tracking encoder is analyzed based on the comparison results to obtain the test results of the tracking encoder.

7. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the steps of any one of the methods described in claims 1 to 5.

8. A computer-readable storage medium, characterized in that, It includes a computer program that, when run on an electronic device, causes the electronic device to perform the steps of any of the methods described in claims 1 to 5.

9. A computer program product, characterized in that, The method includes a computer program stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, causing the electronic device to perform the steps of any one of claims 1 to 5.

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