A high-efficiency, fast-transient-response dual-phase Buck circuit power management chip

Abstract

The present invention discloses a high-efficiency, fast-transient-response dual-phase Buck circuit power management chip. The chip comprises a reference circuit module, a protection module, a zero-crossing detection module, a mode selection module, a clock generation module, a soft-start module, an error amplifier, a load switching detection circuit, a current sampling module, a downslope generator, a hysteresis comparator, a control logic and drive module, a phase switching module, a current sharing module, and four on-chip power switches. The power management chip can rapidly respond to load changes, adaptively adjusting the number of active phases and the system operating mode. Compared to traditional voltage-controlled Buck circuit power management chips, the present invention offers faster response speed and lower overshoot voltage during sudden load changes, improving chip efficiency across the full load range, addressing the issue of concentrated heat generation, and enhancing system safety and reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-efficiency, fast transient response dual-phase Buck circuit power management chip. Background Art

[0002] A power management chip (PMIC) is responsible for converting, distributing, detecting, and other energy management functions within electronic equipment systems. It typically consists of peripheral circuits and control circuits. The peripheral circuits typically include a switch consisting of at least two semiconductor components, an energy storage element (such as an inductor or capacitor), and an output filter. The control circuit controls the opening and closing of the semiconductor switches to uniformly and stably transmit the converted input voltage to the output terminal for subsequent loads.

[0003] Figure 1 The figure shows a traditional voltage-controlled Buck circuit. The error amplifier amplifies the feedback voltage V FB With reference voltage V REF The difference between the two generates an analog error signal V EA , V EA The compensation module adjusts the PWM comparator input V C And with the ramp voltage V ramp By comparison, we can get the power switch tube S p1 、S n1 Under high load current and rapid load changes, the traditional Buck circuit will experience a rapid decrease in system efficiency due to the rapid increase in conduction losses of the power switch tube. The transient response speed will also be limited by the voltage loop bandwidth. At the same time, the traditional Buck circuit has only one switching branch, making reliability difficult to guarantee.

[0004] To improve efficiency, the paper [Mi Z, Low Q, iek LA High Efficiency Synchronous Buck Converter with Adaptive Dead-Time Control [C] / / International Symposium on Integrated Circuits. IEEE, 2017] proposed an adaptive dead-time control technique that eliminates power losses caused by body diode conduction and inductor reverse current, thereby improving efficiency. However, the power consumption of the introduced dead-time controller and dynamic delay generator circuits is not negligible at light loads, resulting in a rapid drop in light-load efficiency and failure to achieve high efficiency at full load. To improve response speed, the paper [Bari S, Qiang L, Lee FC. Fast Adaptive on Time Control for Transient Performance Improvement [C] / / Applied Power Electronics Conference & Exposition. IEEE, 2015] proposed detecting output load steps to change the on-time and thereby reduce output voltage undershoot and overshoot. However, this method is only applicable to PFM-controlled buck converter circuits and consumes a lot of power, thus having certain limitations. Summary of the Invention

[0005] In view of the above, the present invention provides a high-efficiency, fast-transient-response dual-phase Buck circuit power management chip, which can achieve high efficiency over the full load range while improving system reliability and transient response speed.

[0006] A high-efficiency, fast-transient-response dual-phase Buck circuit power management chip, comprising:

[0007] Four power switches M in a dual-phase Buck circuit p1 、M p2 、M n1 and M n2 , integrated on-chip;

[0008] Protection module, used to detect the load current and output voltage V of the dual-phase Buck circuit out , and generate a protection signal by comparison according to the detection results;

[0009] Zero-crossing detection module, used to detect the power switch tube M p1 The drain voltage is measured and compared with the power ground to generate the inductor current zero-crossing signal;

[0010] Mode selection module, used to detect the power switch tube M in a switching cycle p1 The off time generates a mode selection signal, including two modes, namely normal operation mode and low power consumption mode; when the off time is greater than the preset delay, the mode selection signal corresponding to the low power consumption mode is output;

[0011] The reference circuit module generates and provides a reference voltage V for the chip when the external enable signal is high according to the mode selection signal. REF ;

[0012] The soft start module generates a soft start voltage V when the chip is powered on. ST ;

[0013] The error amplifier, based on the soft start voltage V ST After the chip soft start is completed, the reference voltage V REF With the feedback voltage V FB The difference between the two generates the output voltage V EA ; The feedback voltage V FB is the output voltage V out Obtained after resistor voltage division;

[0014] The load switching detection circuit detects the feedback voltage V FB The load condition is judged by the size of , thereby outputting the overshoot response signal OSR and the undershoot response signal USR;

[0015] The clock generation module generates two extremely low duty cycle clock signals CLK1 and CLK2 with a phase difference of 180° according to the overshoot response signal OSR and the undershoot response signal USR when the external reset signal is at a low level;

[0016] The current sampling module is used to collect the two-phase inductor current ripple and convert it into a voltage signal V ramp1 and V ramp2 ;

[0017] The current balancing module is used to amplify the difference between the two-phase inductor currents and generate a pair of differential current balancing voltages V with an amplitude positively correlated with the current difference. CB1 and V CB2 ;

[0018] Two down-slope generators, based on the output voltage V EA and V out Generate two down-ramp signals V with the same frequency and phase difference as CLK1 and CLK2 respectively slope1 and V slope2 ;

[0019] The two hysteresis comparators B1 and B2 have two pairs of positive and negative input terminals, of which one pair of positive and negative input terminals of B1 is connected to Vslope1 and V ramp1 , the other pair of positive and negative input terminals are connected to V CB2 and V CB1 , the output terminal generates a comparison signal V comp1 ; A pair of positive and negative input terminals of B2 are connected to V slope2 and V ramp2 , the other pair of positive and negative input terminals are connected to V CB1 and V CB2 , the output terminal generates a comparison signal V comp2 ;

[0020] A phase switching module is used to compare the load current with a given reference value and generate a phase switching signal;

[0021] The control logic module is based on the inductor current zero-crossing signal, phase switching signal, protection signal and comparison signal V comp1 and V comp2 , generate M through control logic p1 、M p2 、M n1 、M n2 The gate drive signal is used to control the on and off of these power switches through the drive circuit.

[0022] Furthermore, when the load current is greater than a preset current threshold or the output voltage exceeds a preset normal range, the protection signal generated by the protection module is a high level, and in other cases it is a low level.

[0023] Furthermore, when the load current is greater than the reference value, the phase switching signal generated by the phase switching module is at a low level, and is at a high level in other cases.

[0024] Furthermore, the mode selection module includes a delay module Delay1, an inverter INV1, a D flip-flop D1, two OR gates OR1 and OR2, an N-bit up-down counter CT1 and an RS flip-flop RS1, wherein: the input end of Delay1 is connected to the input end of INV1 and is connected to the power switch tube M p1 The gate drive signal of Delay1 is connected to the input of D1, the output of INV1 is connected to the clock terminal of D1, the positive output of D1 is connected to the first input of OR1, the negative output of D1 is connected to the first input of OR2, the second input of OR1 and the second input of OR2 are connected to M p1 The gate drive signal of OR1 is connected to the subtraction terminal of CT1, the output terminal of OR2 is connected to the addend terminal of CT1, the borrow terminal of CT1 is connected to the R input terminal of RS1, the carry terminal of CT1 is connected to the S input terminal of RS1, and the output terminal of RS1 generates a mode selection signal.

[0025] Furthermore, the N-bit up-down counter CT1 is triggered by a rising edge, and the count value is increased by 1 each time the addend receives a rising edge, and the count value is reduced by 1 each time the subtractend receives a rising edge, and the upper and lower limits of the count value are 2 N and 0, when the count value accumulates to 2 N The carry terminal outputs a high level, otherwise it is a low level; when the count value is decremented to 0, the borrow terminal outputs a high level, otherwise it is a low level.

[0026] Furthermore, the clock generation module includes an oscillator, a D flip-flop DF1, an inverter I1, a delay module DL1, an XOR gate XOR1, six AND gates AND1 to AND6, two two-to-one selectors MUX1 and MUX2, and two three-bit counters CA1 and CA2, wherein the oscillator self-generates an oscillation signal V with a switching frequency twice as high as the switching frequency. OSC DF1’s input is connected to the inverting output, and DF1’s clock is connected to the oscillation signal V OSC The positive-phase output of DF1 is connected to the input of I1, the first input of XOR1, the first input of AND1, and the input of DL1. The output of DL1 is connected to the second input of XOR1, the output of XOR1 is connected to the second input of AND1 and the first input of AND2, the output of I1 is connected to the second input of AND2, the output of AND1 is connected to the input of CA1 and the first input of AND3, the output of CA1 is connected to the second input of AND3, the output of AND2 is connected to the input of CA2 and the first input of AND4, the output of CA2 is connected to the second input of AND4, and the first input of MUX1 and MUX2 are connected to the oscillation signal V OSC The output end of AND3 is connected to the second input end of MUX1, the output end of AND4 is connected to the second input end of MUX2, the selection ends of MUX1 and MUX2 are connected to the undershoot response signal USR, the first input ends of AND5 and AND6 are connected to the overshoot response signal OSR, the output end of MUX1 is connected to the second input end of AND5, the output end of AND5 generates the clock signal CLK1, the output end of MUX2 is connected to the second input end of AND6, and the output end of AND6 generates the clock signal CLK2.

[0027] Furthermore, the three-bit counters CA1 and CA2 are both rising-edge triggered. The count value of CA1 and CA2 increases by 1 each time the input terminal receives a rising edge. When the count value of CA1 and CA2 accumulates to 8, the output terminal generates a high level, otherwise it generates a low level.

[0028] Furthermore, the down-slope generator includes a bias current source, 11 PMOS tubes P1 to P11 , 9 NMOS tubes N1~N9, a resistor Res1 and a capacitor Cap1, where the source of P1 is connected to the source of P2, the source of P3, the source of P4, the source of P5 and the source of P 11 The source of P1 is connected to the power supply voltage VDD, the gate of P1 is connected to the drain of P1, the gate of P2, the gate of P3 and the input of the bias current source, the output of the bias current source is connected to the source of N1, the source of N2, the source of N3, the source of N7, the source of N8, the source of N9 and one end of Res1 and connected to the power supply ground VSS, the drain of P2 is connected to the source of P8 and the source of P9, and the gate of P8 is connected to the output voltage V out , the drain of P8 is connected to the drain of N1, the gate of N1 and the gate of N2, the drain of P9 is connected to the drain of N2 and the gate of N3, the gate of P9 is connected to the source of N4 and the other end of Res1, the drain of P3 is connected to the drain of N3 and the gate of N4, the gate of P4 is connected to the gate of P5, the drain of P4 and the source of P6, the gate of P6 is connected to the gate of P7, the drain of P6 and the drain of N4, the drain of P5 is connected to the source of P7, the drain of P7 is connected to the drain of N5, the gate of N5 and the gate of N6, the source of N5 is connected to the drain of N7, the gate of N7 and the gate of N8, the drain of N8 is connected to the source of N6, the drain of N6 is connected to one end of Cap1 and P 10 The drain of the slope1 or V slope2 , the other end of Cap1 is connected to P 10 The source is connected to the output voltage V EA , P 10 The gate and P 11 The drain of N9 is connected to the drain of P 11 The gate of is connected to the gate of N9 and is connected to the clock signal CLK1 or CLK2.

[0029] Furthermore, when the comparison signal V comp1 When the protection signal and the inductor current zero-crossing signal are both at low levels, the control logic module generates M p1 The gate drive signal is low level, and high level in other cases; when the comparison signal V comp2 When the level is high and the protection signal, the phase switching signal and the inductor current zero-crossing signal are all low, the control logic module generates M p2 The gate drive signal is low level, and high level in other cases; when the comparison signal V comp1 When the protection signal and the inductor current zero-crossing signal are both low, the control logic module generates M n1The gate drive signal is high level, and low level in other cases; when the comparison signal V comp2 When the protection signal, the phase switching signal and the inductor current zero-crossing signal are all low, the control logic module generates M n2 The gate drive signal is high in some cases and low in other cases.

[0030] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0031] 1. The power management chip of the present invention can adaptively adjust the number of phases opened and the system operating mode according to the load conditions, achieving high efficiency within the full load range.

[0032] 2. The power management chip of the present invention balances the load current when operating in two phases, thereby alleviating the problem of concentrated heat.

[0033] 3. The power management chip of the present invention can timely sense load changes and enable the two switch branches to respond simultaneously, with faster response speed and lower overshoot voltage.

[0034] 4. The power management chip of the present invention has a soft start function when powered on, and has overvoltage, undervoltage and overcurrent protection functions during normal operation, thereby improving the stability of system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a structural diagram of a traditional voltage-controlled Buck circuit.

[0036] Figure 2 This is a schematic diagram of the structure of the power management chip of the present invention.

[0037] Figure 3 This is a schematic diagram of the circuit structure of the clock generation module.

[0038] Figure 4 (a) is a schematic diagram of the key signal waveform when the load switches from heavy load to light load.

[0039] Figure 4 (b) is a schematic diagram of the key signal waveform when the load switches from light load to heavy load.

[0040] Figure 5 Schematic diagram of the circuit structure of the down-ramp generator.

[0041] Figure 6 This is a circuit diagram of the mode selection module.

[0042] Figure 7 Schematic diagram of simulation results of the power management chip efficiency of the present invention. DETAILED DESCRIPTION

[0043] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] like Figure 2 As shown, the dual-phase Buck circuit power management chip of the present invention is suitable for high current applications, and it has a power input pin (V in )、output voltage pin (V out ), ground pin (GND), two feedback ripple pins (V ramp1 and V ramp2 ) and two switch pins (V SW1 and V SW2 The power management chip includes a reference circuit module, a protection module, a zero-crossing detection module, a mode selection module, a clock generation module, an error amplifier, a load switching detection circuit, a current sampling module, a down-slope generator, a hysteresis comparator, a control logic and drive module, a phase switching module, a current sharing module and four on-chip switch tubes M p1 、M p2 and M n1 、M n2 .

[0045] As a typical application of this chip, the power input pin (V in ) is connected to each module in the chip to generate the power supply potential for the normal operation of each module in the chip; the external ground potential is connected to each module in the chip through the ground pin (GND) to generate the reference ground potential for the normal operation of each module in the chip.

[0046] Two switch SW pins (V SW1 and V SW2 ), respectively connected to the power switch tube M p1 and M n1 , power switch tube M p2 and M n2 The power switch tube level is sampled and the power switch tube level is input into the zero-crossing detection module. The output of the zero-crossing detection module is connected to the control logic module to realize the power switch tube M n1 and M n2 Zero current shutdown reduces switching losses.

[0047] Two feedback ripple pins (V ramp1 and V ramp2 ), respectively connected to the feedback resistor R F1 and feedback capacitor C F1 , feedback resistor R F2 and feedback capacitor C F2 Between them, two feedback ripples (V ramp1 and V ramp2 ) are connected to the negative terminals of the two main comparators. ramp1 and Vramp2 The DC component is V out , V ramp1 The AC component is V ramp2 The AC component is If you set and Then V ramp1 and V ramp2 The AC components of are respectively proportional to the AC components of the inductor L1 current and the inductor L2 current.

[0048] The protection module detects the load current and output voltage V out , and generates a protection signal by comparison based on the detection results; when the load current is greater than the preset current threshold or the output voltage exceeds the preset normal range, the protection signal output by the protection module is triggered at a high level, and it is at a low level at other times.

[0049] The phase switching module compares the load current with a reference value and generates a phase switching signal. When the load current is higher than the preset reference value, the phase switching signal is high and low at other times.

[0050] The zero-crossing detection module detects the power switch tube M p1 (or M p2 ) and compares it with the power ground to generate the inductor current zero-crossing signal.

[0051] The mode selection module detects the power switch tube M in a switching cycle. p1 The off time is greater than the preset delay, and the low power mode is entered.

[0052] The reference circuit module generates and provides a reference voltage V for the chip when the external enable signal is high according to the mode selection signal LP. REF .

[0053] The soft start module generates a soft start voltage V when the chip system is powered on. ST supplied to the error amplifier.

[0054] The current sampling module is used to collect the voltage signal V with the inductor current ripple information ramp1 and V ramp2 .

[0055] The error amplifier is based on the soft start voltage V ST After the chip system is powered on, the reference voltage V REF With the feedback voltage V FB (Output voltage V outThe difference between the two voltages is obtained by resistor division, and the output voltage V EA .

[0056] The load switching detection circuit is based on the feedback voltage V FB The load condition is judged by the size of the output signal, and the overshoot response signal OSR and undershoot response signal USR are output.

[0057] The clock generation module generates two extremely low duty cycle clock signals CLK1 and CLK2 with a phase difference of 180° according to the overshoot response signal OSR and the undershoot response signal USR when the external reset signal is low, and inputs them into the two down-slope generators respectively. Figure 3 As shown, the clock generation module in this embodiment includes an oscillator OSC, a D flip-flop DF1, an inverter I1, a delay module DL1, an XOR gate XOR1, six AND gates AND1 to AND6, two two-to-one selectors MUX1 to MUX2, and two three-bit counters CA1 to CA2; wherein the oscillator output V OSC The D-type flip-flop DF1 is used for frequency division. The divided signal CLK is delayed by the delay module DL1 and then XORed with the original signal CLK to produce a signal with a very low duty cycle. This signal is then ANDed with CLK and its inverted signal CLK_N. Two three-bit counters CA1 and CA2 prevent instability upon power-up. Two data selectors MUX1 and MUX2 and AND gates AND5 and AND6 determine the system clock signals CLK1 and CLK2 based on the detection results of the load detection circuit.

[0058] Figure 4 (a) is the key signal waveform when the load switches from heavy load to light load in this embodiment. At this time, the output voltage overshoots, and the load switching detection circuit outputs the overshoot enable signal OSR, which becomes low, preventing the rising edges of the clock signals CLK1 and CLK2 from arriving until the output voltage returns to below the high threshold. Figure 4 (b) is the key signal waveform when the load switches from light load to heavy load in this embodiment. At this time, the output voltage undershoots, and the load switching detection circuit outputs the undershoot enable signal USR, which becomes a low level. The clock frequency is accelerated so that the two phases process the load change simultaneously until the output voltage recovers to above the low threshold.

[0059] Output voltage pin (V out ) is also connected to the down-slope generator in the chip, and the down-slope generator inputs the stable voltage V output by the error amplifier EA The clock signals CLK1 and CLK2 generated by the clock generation module, when the rising edge of the clock signal arrives, the down-slope generator generates a set of ramp signals V slope1 and Vslope2 Input to a positive terminal of the main comparator and compare with the corresponding feedback ripple signal. Figure 5 As shown, in this embodiment, the down-slope generator includes a bias current source, 11 PMOS tubes P1 to P 11 , 9 NMOS tubes N1~N9, a resistor Res1 and a capacitor Cap1; among them, PMOS tubes P1~P3, PMOS tubes P8~P9 and NMOS tubes N1~N3 form a two-stage operational amplifier structure, and PMOS tubes P4~P7 and NMOS tubes N5~N8 form a cascode current mirror; whenever the rising edge of CLK1 arrives, the PMOS tube P 10 Turn on, initialize V slope1 Since the duty cycle of CLK1 is very small, the initialization operation is completed within a few ns, and then V slope1 will be subject to a slope of The discharge current is affected and linearly decreases until the next clock rising edge arrives; similarly, whenever the CLK2 rising edge arrives, the initialization V slope2 , then V slope2 will be subject to a slope of The discharge current decreases linearly until the next clock rising edge arrives.

[0060] The hysteresis comparator has two pairs of positive and negative input terminals, one of which receives the downward ramp signal V slope1 (or V slope2 ) and feedback ripple V ramp1 (or V ramp2 ), the other current balancing voltage V CB1 and V CB2 , generating a comparison signal and inputting it into the control logic circuit; at the same time, the output signals of the protection module and the zero-crossing detection module are also inputted into the control logic circuit, and the driving signal is generated by the control logic and the driving circuit and then inputted into the power switch tube M p1 (or M p2 ) and power switch tube M n1 (or M n2 ) gate.

[0061] When the load switches, the phase switching module detects the load change, generates a phase switching signal and inputs it into the control logic circuit of the second phase to control the opening or closing of the second phase to maximize efficiency. At the same time, the mode selection module detects the power switch tube M in each cycle. p1 The off time determines the working mode of the system. Figure 6 As shown, the mode selection module in this embodiment includes a delay module Delay1, an inverter INV1, a D flip-flop D1, two OR gates OR1-OR2, an N-bit up-down counter CT1 and an RS flip-flop RS1; wherein DRV_HGA is a power switch tube Mp1 If the power switch tube M p1 If the off time of the delay module Delay1 is greater than the delay of the delay module Delay1, the Q terminal of the D flip-flop D1 is high level when each Clk rising edge arrives. At this time, the output of the OR gate OR1 is always high level, and the subtraction function of the N-bit up-down counter CT1 is invalid. The OR gate OR2 outputs a pulse signal that is exactly the same as DRV_HGA, so the N-bit up-down counter CT1 increases by 1 cycle by cycle. If the Q terminal is kept high for 2 N cycles, indicating that the load current has become very small, and the carry signal CA of the N-bit up-down counter CT1 will become high. After passing through the RS trigger, the signal LP is set high. The signal LP is input to the reference circuit, which adjusts the bias current of each module and shuts down unnecessary modules to put the system into low power mode. When the load jumps out of the extremely light load range, the Q end of the D flip-flop D1 is low at each Clk rising edge. At this time, the output of the OR gate OR2 is always high, and the addition function of the N-bit up-down counter CT1 is invalid. The OR gate OR1 outputs a pulse signal exactly the same as DRV_HGA, so the N-bit up-down counter CT1 decreases by 1 cycle by cycle. If the Q end is low for 2 N cycles, indicating that the load current has become relatively large, the borrow signal BO of the N-bit up / down counter CT1 will become high, and after passing through the RS trigger, the signal LP will be set low. The signal LP is input to the reference circuit, which adjusts the bias current of each module and turns on the necessary modules to put the system into normal working mode.

[0062] Figure 7 The simulation results of the chip system efficiency of this embodiment show that the system reaches a peak efficiency of 90.1% at a load of 450mA. The phase switching module and the mode selection module ensure that the system efficiency is basically higher than 80% within the full load range, greatly improving the full load efficiency of the chip.

[0063] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It will be apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring inventive effort. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A high-efficiency, fast transient response dual-phase Buck circuit power management chip, characterized in that: include: Four power switches M in a dual-phase Buck circuit p1 、M p2 、M n1 and M n2 , integrated on-chip; Protection module, used to detect the load current and output voltage V of the dual-phase Buck circuit out , and generate a protection signal by comparison according to the detection results; Zero-crossing detection module, used to detect the power switch tube M p1 The drain voltage is measured and compared with the power ground to generate the inductor current zero-crossing signal; Mode selection module, used to detect the power switch tube M in a switching cycle p1 The off time generates a mode selection signal, including two modes, namely normal operation mode and low power consumption mode; when the off time is greater than the preset delay, the mode selection signal corresponding to the low power consumption mode is output; The reference circuit module generates and provides a reference voltage V for the chip when the external enable signal is high according to the mode selection signal. REF ; The soft start module generates a soft start voltage V when the chip is powered on. ST ; The error amplifier, based on the soft start voltage V ST After the chip soft start is completed, the reference voltage V REF With the feedback voltage V FB The difference between the two generates the output voltage V EA ; The feedback voltage V FB is the output voltage V out Obtained after resistor voltage division; The load switching detection circuit detects the feedback voltage V FB The load condition is judged by the size of , thereby outputting the overshoot response signal OSR and the undershoot response signal USR; The clock generation module generates two extremely low duty cycle clock signals CLK1 and CLK2 with a phase difference of 180° according to the overshoot response signal OSR and the undershoot response signal USR when the external reset signal is at a low level; The current sampling module is used to collect the two-phase inductor current ripple and convert it into a voltage signal V ramp1 and V ramp2 ; The current balancing module is used to amplify the difference between the two-phase inductor currents and generate a pair of differential current balancing voltages V with an amplitude positively correlated with the current difference. CB1 and V CB2 ; Two down-slope generators, based on the output voltage V EA and V out Generate two down-ramp signals V with the same frequency and phase difference as CLK1 and CLK2 respectively slope1 and V slope2 ; The two hysteresis comparators B1 and B2 have two pairs of positive and negative input terminals, of which one pair of positive and negative input terminals of B1 is connected to V slope1 and V ramp1 , the other pair of positive and negative input terminals are connected to V CB2 and V CB1 , the output terminal generates a comparison signal V comp1 ; A pair of positive and negative input terminals of B2 are connected to V slope2 and V ramp2 , the other pair of positive and negative input terminals are connected to V CB1 and V CB2 , the output terminal generates a comparison signal V comp2 ; A phase switching module is used to compare the load current with a given reference value and generate a phase switching signal; The control logic module is based on the inductor current zero-crossing signal, phase switching signal, protection signal and comparison signal V comp1 and V comp2 , generate M through control logic p1 、M p2 、M n1 、M n2 The gate drive signal is used to control the on and off of these power switches through the drive circuit.

2. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: When the load current is greater than a preset current threshold or the output voltage exceeds a preset normal range, the protection signal generated by the protection module is a high level, and in other cases it is a low level.

3. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: When the load current is greater than the reference value, the phase switching signal generated by the phase switching module is at a low level, and is at a high level in other cases.

4. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: The mode selection module includes a delay module Delay1, an inverter INV1, a D flip-flop D1, two OR gates OR1 and OR2, an N-bit up-down counter CT1 and an RS flip-flop RS1, wherein: the input end of Delay1 is connected to the input end of INV1 and connected to the power switch tube M p1 The gate drive signal of Delay1 is connected to the input of D1, the output of INV1 is connected to the clock terminal of D1, the positive output of D1 is connected to the first input of OR1, the negative output of D1 is connected to the first input of OR2, the second input of OR1 and the second input of OR2 are connected to M p1 The gate drive signal of OR1 is connected to the subtraction terminal of CT1, the output terminal of OR2 is connected to the addend terminal of CT1, the borrow terminal of CT1 is connected to the R input terminal of RS1, the carry terminal of CT1 is connected to the S input terminal of RS1, and the output terminal of RS1 generates a mode selection signal.

5. The dual-phase Buck circuit power management chip according to claim 4, characterized in that: The N-bit up-down counter CT1 is triggered by the rising edge. The addend receives a rising edge and the subtractor receives a rising edge, and the count value is reduced by 1. The upper and lower limits of the count value are 2 N and 0, when the count value accumulates to 2 N The carry terminal outputs a high level, otherwise it is a low level; when the count value is decremented to 0, the borrow terminal outputs a high level, otherwise it is a low level.

6. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: The clock generation module includes an oscillator, a D flip-flop DF1, an inverter I1, a delay module DL1, an XOR gate XOR1, six AND gates AND1 to AND6, two two-to-one selectors MUX1 and MUX2, and two three-bit counters CA1 and CA2. The oscillator generates an oscillation signal V with a switching frequency twice as high as the switching frequency. OSC DF1’s input is connected to the inverting output, and DF1’s clock is connected to the oscillation signal V OSC The positive-phase output of DF1 is connected to the input of I1, the first input of XOR1, the first input of AND1, and the input of DL1. The output of DL1 is connected to the second input of XOR1, the output of XOR1 is connected to the second input of AND1 and the first input of AND2, the output of I1 is connected to the second input of AND2, the output of AND1 is connected to the input of CA1 and the first input of AND3, the output of CA1 is connected to the second input of AND3, the output of AND2 is connected to the input of CA2 and the first input of AND4, the output of CA2 is connected to the second input of AND4, and the first input of MUX1 and MUX2 are connected to the oscillation signal V OSC The output end of AND3 is connected to the second input end of MUX1, the output end of AND4 is connected to the second input end of MUX2, the selection ends of MUX1 and MUX2 are connected to the undershoot response signal USR, the first input ends of AND5 and AND6 are connected to the overshoot response signal OSR, the output end of MUX1 is connected to the second input end of AND5, the output end of AND5 generates the clock signal CLK1, the output end of MUX2 is connected to the second input end of AND6, and the output end of AND6 generates the clock signal CLK2.

7. The dual-phase Buck circuit power management chip according to claim 6, characterized in that: The three-bit counters CA1 and CA2 are both rising edge triggered. The count value of CA1 and CA2 increases by 1 each time the input terminal receives a rising edge. When the count value of CA1 and CA2 accumulates to 8, the output terminal generates a high level, otherwise it generates a low level.

8. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: The down-slope generator includes a bias current source, 11 PMOS tubes P1 to P 11 , 9 NMOS tubes N1~N9, a resistor Res1 and a capacitor Cap1, where the source of P1 is connected to the source of P2, the source of P3, the source of P4, the source of P5 and the source of P 11 The source of P1 is connected to the power supply voltage VDD, the gate of P1 is connected to the drain of P1, the gate of P2, the gate of P3 and the input of the bias current source, the output of the bias current source is connected to the source of N1, the source of N2, the source of N3, the source of N7, the source of N8, the source of N9 and one end of Res1 and connected to the power supply ground VSS, the drain of P2 is connected to the source of P8 and the source of P9, and the gate of P8 is connected to the output voltage V out , the drain of P8 is connected to the drain of N1, the gate of N1 and the gate of N2, the drain of P9 is connected to the drain of N2 and the gate of N3, the gate of P9 is connected to the source of N4 and the other end of Res1, the drain of P3 is connected to the drain of N3 and the gate of N4, the gate of P4 is connected to the gate of P5, the drain of P4 and the source of P6, the gate of P6 is connected to the gate of P7, the drain of P6 and the drain of N4, the drain of P5 is connected to the source of P7, the drain of P7 is connected to the drain of N5, the gate of N5 and the gate of N6, the source of N5 is connected to the drain of N7, the gate of N7 and the gate of N8, the drain of N8 is connected to the source of N6, the drain of N6 is connected to one end of Cap1 and P 10 The drain of the slope1 or V slope2 , the other end of Cap1 is connected to P 10 The source is connected to the output voltage V EA , P 10 The gate and P 11 The drain of N9 is connected to the drain of P 11 The gate of is connected to the gate of N9 and is connected to the clock signal CLK1 or CLK2.

9. The dual-phase Buck circuit power management chip according to claim 1, characterized in that: When the comparison signal V comp1 When the protection signal and the inductor current zero-crossing signal are both low, the control logic module generates M p1 The gate drive signal is low level, and high level in other cases; when the comparison signal V comp2 When the level is high and the protection signal, the phase switching signal and the inductor current zero-crossing signal are all low, the control logic module generates M p2 The gate drive signal is low level, and high level in other cases; when the comparison signal V comp1 When the protection signal and the inductor current zero-crossing signal are both low, the control logic module generates M n1 The gate drive signal is high level, and low level in other cases; when the comparison signal V comp2 When the protection signal, the phase switching signal and the inductor current zero-crossing signal are all low, the control logic module generates M n2 The gate drive signal is high in some cases and low in other cases.

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