Multi-layer capacitor

Abstract

A multilayer capacitor is provided. The multilayer capacitor includes a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a dielectric layer, a first internal electrode, and a second internal electrode. The first external electrode and the second external electrode are respectively disposed at both ends of the capacitor body and connected to the exposed portions of the first internal electrode and the second internal electrode. A / B satisfies 0.0016 ≤ A / B < 1, where A is the thickness of the dielectric layer and B is the average length of the edges of the capacitor body in the length direction, and A is 1 μm or less.

Description

[0001] This application is a divisional application of the invention patent application with the application date of April 7, 2020, the application number of 202010264538.9, and the title of "Multilayer Capacitor and Board with Multilayer Capacitor Mounted Thereon". Technical Field

[0002] The present disclosure relates to a multilayer capacitor and a board with the multilayer capacitor mounted thereon. Background Art

[0003] A multilayer ceramic capacitor (MLCC) is a passive component that controls an electrical signal in a circuit.

[0004] The main functions of a multilayer capacitor are to accumulate charges in electrodes, block a direct current (DC) signal, and act as a filter that allows an alternating current (AC) signal to pass through.

[0005] In other words, the multilayer capacitor bypasses and eliminates AC noise in a power line to stabilize the operation of an integrated circuit (IC).

[0006] Various methods have been tried to increase the capacitance of such an MLCC.

[0007] For example, methods of increasing the dielectric constant of a dielectric material, reducing the thickness of the dielectric material, or increasing the area of overlap of internal electrodes have been proposed.

[0008] However, when the area of overlap of internal electrodes increases, the edges in the length direction or width direction of the product may decrease. If the amount of edge reduction is too large, a problem may occur in that the electric field characteristics may be weakened. Summary of the Invention

[0009] The present invention content is provided to introduce selected concepts in a simplified form, which will be further described in the following detailed description. The present invention content is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0010] One aspect of the present disclosure is to provide a multilayer capacitor and a board with the multilayer capacitor mounted thereon, wherein the edge of the capacitor body is adapted to prevent deterioration of electric field characteristics while increasing the area of overlap of internal electrodes.

[0011] According to one aspect of the present disclosure, a multilayer capacitor includes: a capacitor body including a dielectric layer, a first internal electrode, and a second internal electrode; a first external electrode and a second external electrode disposed at two ends of the capacitor body in a length direction and connected to an exposed first end of the first internal electrode and an exposed first end of the second internal electrode. When the thickness of the dielectric layer is defined as A and the average length of an edge of the capacitor body in the length direction is defined as B, A is 1 μm or less, and A / B satisfies 0.0016 ≤ A / B < 1. The edges are dielectric portions of the capacitor body in the length direction from respective second ends of the first internal electrode and the second internal electrode opposite to the first ends to adjacent side surfaces of the capacitor body.

[0012] The thickness of each of the first internal electrode and the second internal electrode may be 0.4 μm or less.

[0013] The capacitor body may include a first surface and a second surface opposite to each other, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface. The first internal electrode and the second internal electrode are respectively exposed through the third surface and the fourth surface of the capacitor body in the length direction, and the dielectric layer is interposed between the first internal electrode and the second internal electrode.

[0014] The first external electrode and the second external electrode may include: a first connection portion and a second connection portion respectively disposed on the third surface and the fourth surface of the capacitor body and connected to the exposed first end of the first internal electrode and the exposed first end of the second internal electrode, and a first strip portion and a second strip portion respectively extending from the first connection portion and the second connection portion in the length direction to a portion of the first surface of the capacitor body.

[0015] Each of the first strip portion and the second strip portion further extends to a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface.

[0016] A plating layer may be provided to cover each of the first external electrode and the second external electrode. The plating layer may include a nickel plating layer and a tin plating layer.

[0017] The thickness of the dielectric layer may be 1 μm and A / B may satisfy 0.002 ≤ A / B ≤ 0.2.

[0018] The thickness of the dielectric layer may be 0.4 μm and A / B may satisfy 0.0016 ≤ A / B ≤ 0.5.

[0019] The average length of the edge of the capacitor body in the length direction may be from 0.8 μm to 500 μm.

[0020] According to one aspect of the present disclosure, a board on which a multilayer capacitor is mounted includes: a substrate, on one surface of the substrate, a first electrode pad and a second electrode pad are provided; and the multilayer capacitor as described above, the multilayer capacitor is mounted in such a manner that the first external electrode and the second external electrode are respectively provided on the first electrode pad and the second electrode pad to be connected to the first electrode pad and the second electrode pad.

[0021] According to another aspect of the present disclosure, a multilayer capacitor includes a capacitor body, the capacitor body includes first internal electrodes and second internal electrodes stacked alternately, and a dielectric layer is laminated between the first internal electrodes and the second internal electrodes. Each first internal electrode and each second internal electrode respectively have a first end exposed through a first side surface and a second side surface of the capacitor body in a length direction, and a second end opposite to the respective first end. The capacitor body further includes: a first side edge portion defined as a dielectric portion disposed between each second end of the first internal electrode and the second side surface of the capacitor body; and a second side edge portion defined as another dielectric portion disposed between each second end of the second internal electrode and the first side surface of the capacitor body. When A is the interval between adjacent layers of the first internal electrode and the second internal electrode and B is the average length of the first side edge portion or the second side edge portion in the length direction, A is 1 μm or less, and A / B satisfies 0.0016 ≤ A / B < 1.

[0022] The multilayer capacitor further includes: a first external electrode and a second external electrode, respectively provided on the first side surface and the second side surface of the capacitor body, and respectively connected to the exposed first ends of the first internal electrode and the second internal electrode.

[0023] The capacitor body includes: an upper edge portion including one or more dielectric layers and provided above the uppermost layer of the first internal electrodes and the second internal electrodes in the stacking direction of the first internal electrodes and the second internal electrodes; a lower edge portion including one or more dielectric layers and provided below the lowermost layer of the first internal electrodes and the second internal electrodes in the stacking direction. Description of the Drawings

[0024] Through the following specific embodiments in conjunction with the drawings, the above and other aspects, features and advantages of the present disclosure will be more clearly understood. In the drawings:

[0025] Figure 1is a perspective view schematically showing a multi-layer capacitor according to an exemplary embodiment of the present disclosure;

[0026] Figure 2A and Figure 2B are respectively plan views showing a first internal electrode and a second internal electrode of the multi-layer capacitor applied in Figure 1 ;

[0027] Figure 3 is a cross-sectional view taken along line I-I' of Figure 1 ;

[0028] Figure 4 is a cross-sectional view showing that a plating layer is further formed on the external electrode of Figure 3 ;

[0029] Figure 5 is a cross-sectional view of the capacitor body showing the position where the electric field is measured in the electric field measurement test; and

[0030] Figure 6 is a cross-sectional view schematically showing the state where the multi-layer capacitor of Figure 4 is mounted on a substrate. DETAILED DESCRIPTION

[0031] The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatuses, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will be apparent to those of ordinary skill in the art. The order of operations described herein is merely an example and is not limited to the order set forth herein, but rather may be changed in a manner that will be apparent to those of ordinary skill in the art, except for operations that need to occur in a specific order. Additionally, descriptions of functions and constructions well known to those of ordinary skill in the art may be omitted for the sake of clarity and brevity.

[0032] The features described herein may be implemented in different forms and are not to be construed as limited to the examples described herein. Rather, the examples described herein are provided so that this disclosure will be thorough and complete and will convey the full scope of this disclosure to those of ordinary skill in the art.

[0033] Here, it is worth noting that the use of the term "may" with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such a feature is included or implemented, and not all examples or embodiments are limited thereto.

[0034] Throughout the specification, when an element, such as a layer, region, or substrate, is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element can be directly "on" the other element, directly "connected to" the other element, or directly "coupled to" the other element, or there can be one or more other elements between the two elements. In contrast, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there can be no other elements between the two elements.

[0035] As used herein, the term "and / or" includes any one or any combination of any two or more of the associated listed items.

[0036] Although terms such as "first", "second", and "third" may be used herein to describe various components, elements, regions, layers, or sections, these components, elements, regions, layers, or sections are not limited by these terms. Rather, these terms are only used to distinguish one component, element, region, layer, or section from another. Thus, a first component, element, region, layer, or section referred to in the examples described herein may also be referred to as a second component, element, region, layer, or section without departing from the teachings of the examples.

[0037] For ease of description, spatial relative terms such as "above", "upper", "below", and "lower" may be used herein to describe the relationship of one element to another as shown in the figures. These spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "above" or "upper" relative to another element will be "below" or "lower" relative to that other element. Thus, the term "above" encompasses both the orientation of "above" and "below" depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein are to be interpreted accordingly.

[0038] The terms used herein are for the purpose of describing various examples only and are not intended to limit the disclosure. Unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. The terms "comprising", "including", and "having" list the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0039] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Accordingly, the examples described herein are not limited to the specific shapes shown in the drawings but include changes in shape that occur during manufacturing.

[0040] The features of the examples described herein can be combined in various ways that will be apparent after understanding the disclosure of this application. Further, although the examples described herein have various configurations, other configurations that will be apparent after understanding the disclosure of this application are possible.

[0041] For clarity, illustration, and convenience, the drawings may not be drawn to scale, and the relative dimensions, proportions, and depictions of elements in the figures may be exaggerated.

[0042] Subsequently, the examples will be described in further detail with reference to the drawings.

[0043] Hereinafter, when defining the direction of the capacitor body 110 for clearly describing the embodiments, X, Y, and Z shown in the drawings respectively refer to the length direction, width direction, and thickness direction of the capacitor body 110. Further, in the embodiments, the Z direction may be used in the same concept as the stacking direction of the stacked dielectric layers.

[0044] Figure 1 To schematically show a perspective view of a multilayer capacitor according to an exemplary embodiment of the present disclosure, Figure 2A and Figure 2B are respectively a plan view showing a first internal electrode and a second internal electrode of the multilayer capacitor applied to Figure 1 and Figure 3 is a cross-sectional view taken along line I-I' of Figure 1 Hereinafter, with reference to

[0045] Referring to Figures 1 to 3 , a multilayer capacitor 100 according to an exemplary embodiment of the present disclosure includes a capacitor body 110, a first external electrode 131, and a second external electrode 141. The capacitor body 110 includes a dielectric layer 111, a plurality of first internal electrodes 121, and a plurality of second internal electrodes 122. The first external electrode 131 and the second external electrode 141 are respectively disposed at both ends of the capacitor body 110 in the length direction (e.g., the X direction) and are connected to the exposed portions of the first internal electrodes 121 and the exposed portions of the second internal electrodes 122.

[0046] In this case, when the thickness of the dielectric layer 111 or the interval between adjacent layers of the first internal electrode and the second internal electrode is defined as A and the length of the edge of the capacitor body 110 in the X direction is defined as B, A is 1 μm or less, and the ratio (A / B) of the thickness of the dielectric layer to the length of the edge of the capacitor body 110 in the X direction may satisfy 0.0016 ≤ A / B < 1.

[0047] A capacitor body 110 is obtained by stacking a plurality of dielectric layers 111 in the Z direction and then sintering them so that the adjacent dielectric layers 111 can be integrated with each other, making it difficult to confirm the boundary between them without using a scanning electron microscope (SEM).

[0048] In this case, the capacitor body 110 may be substantially hexahedral, but the embodiments are not limited thereto.

[0049] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to those shown in the drawings of this embodiment.

[0050] In this embodiment, for ease of description, two surfaces of the capacitor body 110 that are opposite to each other in the Z direction are defined as the first surface 1 and the second surface 2, two surfaces of the capacitor body 110 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in the X direction are defined as the third surface 3 and the fourth surface 4, and two surfaces of the capacitor body 110 that are connected to the first surface 1 and the second surface 2 and are connected to the third surface 3 and the fourth surface 4 and are opposite to each other in the Y direction are defined as the fifth surface 5 and the sixth surface 6.

[0051] In this embodiment, the mounting surface of the multilayer capacitor 100 may be the first surface 1 of the capacitor body 110.

[0052] The dielectric layer 111 may include a ceramic material having a high dielectric constant, such as barium titanate-based (BaTiO3) or strontium titanate (SrTiO3)-based ceramic powder, etc., but the ceramic material is not limited thereto. For example, any ceramic material can be used as long as sufficient capacitance can be obtained therefrom.

[0053] In addition, ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be further added to the dielectric layer 111 together with the ceramic powder.

[0054] The ceramic additives may be, for example, transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), aluminum (Al), etc.

[0055] The capacitor body 110 may include an effective region, an upper cover 112, and a lower cover 113. The effective region is the part that contributes to the formation of the capacitance of the capacitor. The upper cover 112 and the lower cover 113 are respectively provided as the upper edge and the lower edge on the upper and lower parts of the effective region in the Z direction. Therefore, the upper cover and the lower cover may also be respectively referred to as the upper edge part and the lower edge part.

[0056] Except for not including the internal electrodes, the upper cover 112 and the lower cover 113 may have the same material and structure as those of the dielectric layer 111.

[0057] The upper cover 112 and the lower cover 113 can be formed by stacking a single dielectric layer or two or more dielectric layers on the upper surface and the lower surface in the Z direction in the effective area, respectively, and can be basically used to prevent damage to the inner electrodes 121 and 122 caused by physical stress or chemical stress.

[0058] The first inner electrode 121 and the second inner electrode 122 are electrodes for receiving different polarities, and are alternately arranged in the Z direction. The dielectric layer 111 is interposed between the first inner electrode 121 and the second inner electrode 122, and one end of the first inner electrode 121 and one end of the second inner electrode 122 can be exposed through the third surface 3 and the fourth surface 4, respectively.

[0059] In this case, the first inner electrode 121 and the second inner electrode 122 can be electrically insulated from each other through the dielectric layer 111 provided therebetween.

[0060] The end portions of the first inner electrode 121 and the second inner electrode 122 alternately exposed through the third surface 3 and the fourth surface 4 of the capacitor body 110 can be respectively connected to the first outer electrode 131 and the second outer electrode 141 provided on the third surface 3 and the fourth surface 4 of the capacitor body 110 to be electrically connected to the first outer electrode 131 and the second outer electrode 141.

[0061] According to the above structure, when a predetermined voltage is applied to the first outer electrode 131 and the second outer electrode 141, charges accumulate between the first inner electrode 121 and the second inner electrode 12.

[0062] In this case, the capacitance of the multilayer capacitor 100 is proportional to the overlapping area of the first inner electrode 121 and the second inner electrode 122 overlapping each other in the Z direction in the effective area.

[0063] The materials used to form the first inner electrode 121 and the second inner electrode 122 are not particularly limited. For example, noble metal materials such as platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloy, etc. and conductive pastes formed of at least one of nickel (Ni) and copper (Cu) can be used.

[0064] In this case, as the printing method of the conductive paste, a screen printing method, a gravure printing method, etc. can be used, but the embodiments are not limited thereto.

[0065] In this embodiment, the thickness of each of the first inner electrode 121 and the second inner electrode 122 can be 0.4 μm or less.

[0066] If the thickness of each of the first inner electrode 121 and the second inner electrode 122 exceeds 0.4 μm, it may be difficult to ensure an appropriately designed capacitance.

[0067] Since multilayer capacitors tend to be miniaturized and have high capacitance, for the miniaturization and high capacitance of multilayer capacitors, the thickness of the inner electrode may specifically be 0.4 μm or less.

[0068] The first external electrode 131 and the second external electrode 141 may be provided with voltages of different polarities, may be disposed at both ends of the capacitor body 110 in the X direction, and are respectively connected to the exposed portions of the first inner electrode 121 and the second inner electrode 122 to be electrically connected to the first inner electrode 121 and the second inner electrode 122.

[0069] The first external electrode 131 may include a first connection portion 131a and a first band portion 131b.

[0070] The first connection portion 131a is a portion disposed on the third surface 3 of the capacitor body 110 to connect to the exposed portion of the first inner electrode 121, and the first band portion 131b is a portion extending from the first connection portion 131a to a part of the first surface 1 of the capacitor body 110.

[0071] In this case, the first band portion 131b may further extend to a part of the fifth surface 5, a part of the sixth surface 6, and a part of the second surface 2 of the capacitor body 110 to improve the fixing strength.

[0072] The second external electrode 141 may include a second connection portion 141a and a second band portion 141b.

[0073] The second connection portion 141a is a portion disposed on the fourth surface 4 of the capacitor body 110 and connected to the exposed portion of the second inner electrode 122, and the second band portion 141b is a portion extending from the second connection portion 141a to a part of the first surface 1 of the capacitor body 110.

[0074] In this case, the second band portion 141b may further extend to a part of the fifth surface 5, a part of the sixth surface 6, and a part of the second surface 2 of the capacitor body 110 to improve the fixing strength.

[0075] As Figure 4 shown, a first plating layer and a second plating layer may be further formed to cover the first external electrode 131 and the second external electrode 141, respectively.

[0076] In this case, the first plating layer and the second plating layer may include a first nickel plating layer 132 and a second nickel plating layer 142 respectively disposed on the surfaces of the first external electrode 131 and the second external electrode 141, and a first tin plating layer 133 and a second tin plating layer 143 respectively covering the first nickel plating layer 132 and the second nickel plating layer 142.

[0077] In this embodiment, when the thickness of the dielectric layer is defined as A and the average length of the edges of the capacitor body 110 in the length direction is defined as B, A / B satisfies 0.0016 ≤ A / B < 1. The dimension A can also be defined as the interval between adjacent layers of the first inner electrode 121 and the second inner electrode 122.

[0078] As a result of checking the electric field behavior based on the X-direction edge length within the numerical range of A / B, it can be seen that the electric field characteristics do not deteriorate.

[0079] Therefore, the overlapping area between the first inner electrode and the second inner electrode can be ensured to be the maximum value within the numerical range of A / B, thereby providing a multilayer capacitor with high capacitance without the occurrence of electric field distortion phenomenon.

[0080] When suppressing or preventing the electric field distortion of the multilayer capacitor and the electric field value of the multilayer capacitor is thus reduced, defects such as breakdown voltage (BDV) of the multilayer capacitor can be prevented.

[0081] The thickness A of the dielectric layer can specifically be 1 μm or less.

[0082] For example, the multilayer capacitor of this embodiment can be a small-size high-capacitance product with the thickness A of the dielectric layer being 1 μm or less.

[0083] Since the multilayer capacitor has a tendency to be miniaturized and have high capacitance, for the miniaturization and high capacitance of the multilayer capacitor, the thickness of the dielectric layer can specifically be 1 μm or less.

[0084] Table 1 below shows the measurement results of the maximum electric field according to the change of the A / B value of the multilayer capacitor using Ansys Maxwell 2D simulation.

[0085] Refer to Figure 5 , the position where the electric field is measured is measured at the observation line OL provided by drawing a vertical line between the parts having a distance g of 0.5 μm from the end of the inner electrode (such as the connection line between the upper point Z2 and the lower point Z1 as shown in Figure 5 ).

[0086] In this case, g is for the simulation by sampling only a part of the multilayer capacitor.

[0087] In this case, the thickness A of the dielectric layer is 1 μm or 0.4 μm, and while changing the average length of the edges B of the capacitor body of the multilayer capacitor in the X direction (for example, from 0.8 μm to 500 μm), the electric field distribution of the multilayer capacitor is respectively confirmed, as shown in Table 1 or Table 2.

[0088] Table 1

[0089]

[0090] Table 1 shows the case where the thickness of the dielectric layer is 1 μm. Referring to Table 1, in the cases of #1 to #5 where the A / B value is between 0.002 and 0.2, the maximum electric field is about 13.18 V / μm to 13.20 V / μm, and there is no significant difference. Therefore, when the thickness of the dielectric layer is 1 μm and 0.002 ≤ A / B ≤ 0.2, a multilayer capacitor with stable electric field characteristics can be provided by suppressing the occurrence of electric field distortion and preventing the capacitance reduction of the multilayer capacitor.

[0091] In addition, in the case of #6 where the A / B value is 1.0, electric field distortion is caused, and the maximum electric field is 14.25 V / μm, which is increased by about 7.35% compared with the cases of #1 to #5.

[0092] In the case of #7 where the A / B value is 1.25, the electric field distortion is greater than that of #6, and the maximum electric field is 15.48 V / μm, which is increased by about 14.72% compared with the cases of #1 to #5.

[0093] Table 2

[0094]

[0095] Table 2 shows the case where the thickness of the dielectric layer is 0.4 μm. Referring to Table 2, in the cases of #8 to #12 where the A / B value is between 0.0016 and 0.5, the maximum electric field is in the range of about 32.95 V / μm to 33.00 V / μm, from which it can be confirmed that the maximum electric field is maintained without significant difference. Therefore, when the thickness of the dielectric layer is 0.4 μm and 0.0016 ≤ A / B ≤ 0.5, a multilayer capacitor with stable electric field characteristics can be provided by suppressing the occurrence of electric field distortion and preventing the capacitance reduction of the multilayer capacitor.

[0096] In addition, in the case of #13 where the A / B value is 1.0, electric field distortion is caused and the maximum electric field is 35.62 V / μm, which is increased by about 7.35% compared with the cases of #8 to #12.

[0097] In the case of #14 where the A / B value is 1.25, the electric field distortion is greater than that of #13, and the maximum electric field is about 38.76 V / μm, which is increased by about 14.86% compared with the cases of #8 to #12.

[0098] Therefore, the multilayer capacitor of this embodiment has the characteristics of a small-size, high-capacitance product including a thin dielectric layer, and when the A / B value is less than 1.0, a multilayer capacitor with stable electric field characteristics can be provided by suppressing the occurrence of electric field distortion and preventing the capacitance reduction of the multilayer capacitor.

[0099] When the A / B value is less than 0.0016, since the capacitance decreases while the overlapping area of the adjacent inner electrodes above and below decreases, the A / B value can specifically be 0.0016 or greater.

[0100] Referring to Figure 6 , according to an exemplary embodiment of the present disclosure, a board on which a multilayer electronic component is mounted may include a substrate 210 having a first electrode pad 221 and a second electrode pad 222 mounted on one surface thereof, and a multilayer capacitor 100 mounted on the upper surface of the substrate 210. The multilayer capacitor 100 is mounted in such a manner that a first tin plating layer 133 of the first outer electrode 131 and a second tin plating layer 143 of the second outer electrode 141 are respectively disposed on the first electrode pad 221 and the second electrode pad 222 to be connected to the first electrode pad 221 and the second electrode pad 222.

[0101] Although the multilayer capacitor 100 is shown and described as being mounted on the substrate 210 by solder 231 and solder 232, a conductive paste may be used instead of solder as needed.

[0102] As described above, according to an exemplary embodiment of the present disclosure, by restricting the thickness of the dielectric layer with respect to the length of the edge of the capacitor body, the overlapping area of the inner electrodes is increased, thereby increasing the capacitance of the multilayer capacitor while preventing the electric field distortion of the multilayer capacitor. By reducing the electric field value, defects such as breakdown voltage (BDV) of the multilayer capacitor can be prevented.

[0103] Although the present disclosure includes specific examples, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be in a descriptive sense only and not for purposes of limitation. The description of each feature or aspect in an example is considered to be applicable to similar features or aspects in other examples. Appropriate results can be obtained if the above techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner, and / or if the components in the described system, architecture, device, or circuit are replaced or added by other components or their equivalents. Therefore, the scope of the present disclosure is defined not by the specific embodiments but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents will be construed as being included in the present disclosure.

Claims

1. A multilayer capacitor, comprising: A capacitor body, comprising a dielectric layer, a first internal electrode, and a second internal electrode; And A first external electrode and a second external electrode, disposed at two ends of the capacitor body, and respectively connected to a first end of the first internal electrode exposed in a length direction and a first end of the second internal electrode exposed in the length direction, Wherein, A / B satisfies 0.04 ≤ A / B < 1.25, where A is the thickness of the dielectric layer, and B is the average length of an edge of the capacitor body in the length direction, the edge being the dielectric part of the capacitor body from a respective second end of the first internal electrode and the second internal electrode opposite to the exposed first end to a side surface of the capacitor body adjacent to the respective second end in the length direction, and Wherein, each of the first internal electrode and the second internal electrode has a thickness of 0.4 μm or less.

2. The multilayer capacitor according to claim 1, wherein, A / B satisfies 0.04 ≤ A / B ≤ 1.

0.

3. The multilayer capacitor according to claim 2, wherein, A / B satisfies 0.04 ≤ A / B ≤ 0.

5.

4. The multilayer capacitor according to claim 3, wherein, A / B satisfies 0.04 ≤ A / B ≤ 0.

2.

5. The multilayer capacitor according to claim 1, wherein, A / B satisfies 0.2 ≤ A / B < 1.

0.

6. The multilayer capacitor according to claim 1, wherein, Each of the dielectric layers has a thickness of 1.0 μm or less.

7. The multilayer capacitor according to claim 6, wherein, The average length of the edge of the capacitor body in the length direction is 0.4 μm to 10 μm.

8. The multilayer capacitor according to claim 7, wherein, The average length of the edge of the capacitor body in the length direction is 0.8 μm to 10 μm.

9. The multilayer capacitor according to claim 8, wherein, The average length of the edge of the capacitor body in the length direction is 0.8 μm to 5 μm.

10. The multilayer capacitor according to claim 1, wherein, A / B satisfies 0.1 ≤ A / B < 1.

25.

11. The multilayer capacitor according to claim 10, wherein, A / B satisfies 0.1 ≤ A / B ≤ 0.

2.

12. The multilayer capacitor according to claim 10, wherein, The average length of the edge of the capacitor body in the length direction is 5 μm to 10 μm.

13. The multilayer capacitor according to claim 1, wherein, A plating layer is provided to cover each of the first external electrode and the second external electrode, and Wherein, each plating layer includes a nickel plating layer and a tin plating layer.

Images