A surge current test circuit for electronic components

Abstract

The application provides a surge current test circuit of electronic components, comprising: a main voltage reduction unit, a to-be-tested component being connected to a power supply end through a first current-limiting resistor and an isolation transformer; an AC sampling unit, used for sampling a high-voltage AC voltage; a sine wave shaping unit, used for performing sine wave shaping processing on a sampling signal and outputting a zero-crossing square wave signal; a key dithering unit, connected to a key unit and comprising a first timing module and a second timing module; a delay unit, connected to the sine wave shaping unit and the key dithering unit respectively; a short pulse generating unit, connected to the delay unit; a driving test unit, connected to the short pulse generating unit, the driving test unit comprising a driver and a controlled switch, and the controlled switch being connected to the to-be-tested component. Advantageous effects: the pure hardware logic triggering function is realized through a logic gate circuit, and the complicated test equipment needs not to be purchased, and the device characteristic verification can be performed only by using a basic infrastructure such as an oscilloscope and an AC power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of surge test, in particular to a surge current test circuit of electronic components. BACKGROUND

[0002] With the progress of semiconductor material and device process technology, the manufacturing process and device structure design of silicon (Si) based power electronic devices have been matured and gradually approached the theoretical limit determined by material properties. The third generation of semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN) is a rapidly developing semiconductor material after the first and second generations of semiconductor materials. In particular, SiC semiconductor material has the advantages of large band gap, high breakdown field, high thermal conductivity, high electron saturation velocity, etc., and is very suitable for preparing a new generation of high-voltage, high-temperature, high-current, high operating frequency and radiation-resistant power electronic devices, which has an attractive application prospect in electric locomotive, electric vehicle and other fields.

[0003] However, due to the limitations of SiC MOSFET gate oxide process, its reliability is a problem. If the wide application of SiC MOSFET is to be realized, the problem of reliability must be solved. At present, in the power switch converter, surge current is common, which often causes impact on the device. It is very important to investigate the surge capacity of the device during the development and production of the device. The surge is a forward surge of the device, and the duration is long. The price of such professional surge equipment is expensive, and the testing cost is high. The circuit for testing the surge performance of the device is not practical. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a surge current test circuit of electronic components.

[0005] The technical problem solved by the present application can be realized by the following technical scheme:

[0006] A surge current test circuit of electronic components, comprising:

[0007] A main voltage reduction unit under test, comprising an isolation transformer, the primary side of the isolation transformer is connected with a power supply end, the secondary side of the isolation transformer is connected with a device under test through a first current limiting resistor, and the primary side and the secondary side of the isolation transformer are respectively connected with a bypass load in parallel;

[0008] An alternating current sampling unit connected between the power supply end and the ground end, for sampling the high-voltage alternating current after the power supply end is powered on, to obtain a sampling signal;

[0009] A sine wave shaping unit connected with the alternating current sampling unit, for performing sine wave shaping processing on the sampling signal, and outputting a zero-crossing square wave signal;

[0010] a key unit, configured to output a key signal under an external control;

[0011] a key de-bouncing unit, comprising a first timing module connected to the key unit, and a second timing module connected to the first timing module, configured to perform delay de-bouncing processing on the key signal to obtain an enable signal;

[0012] a delay unit connected to the sine wave shaping unit and the key de-bouncing unit respectively, configured to enable the delay unit under the action of the enable signal, perform delay processing on the zero-crossing square wave signal, and start cycle counting;

[0013] a short pulse generating unit connected to the delay unit, configured to obtain a short pulse trigger signal according to the delay-processed zero-crossing square wave signal;

[0014] a drive test unit connected to the short pulse generating unit, the drive test unit comprising a driver and a controlled switch, the controlled switch being connected to the to-be-tested component, the driver being configured to output a drive signal according to the short pulse trigger signal to drive the controlled switch to turn on, and the to-be-tested component being subjected to a periodic current to complete a surge test of the to-be-tested component.

[0015] Preferably, the AC sampling unit comprises a first capacitor and a second capacitor connected in series between the power supply end and the ground end, and the sampling signal is output from the connection between the first capacitor and the second capacitor.

[0016] Preferably, the sine wave shaping unit comprises:

[0017] a Schmitt trigger, a trigger port and a reset lock port of the Schmitt trigger being connected to the sampling signal;

[0018] a first transistor, a gate of the first transistor being connected to an output port of the Schmitt trigger, a drain of the first transistor being connected to a power supply end through a first resistor, the zero-crossing square wave signal being output from the drain of the first transistor, and a source of the first transistor being connected to the ground end.

[0019] Preferably, the first timing module comprises:

[0020] a second transistor, a gate of the second transistor being connected to the key signal, a drain of the second transistor being connected to the power supply end through a second resistor, and a source of the second transistor being connected to the ground end.

[0021] a first monostable trigger, a trigger port of the first monostable trigger being connected to the power supply end through a third resistor and to the second transistor drain through a third capacitor, and an output port of the first monostable trigger being connected to the second timing module.

[0022] Preferably, the second timing module comprises:

[0023] an RS trigger, a reset lock port of the RS trigger being connected to an output of the first timing module;

[0024] a third transistor, a gate of the third transistor being connected to an output port of the RS trigger, a drain of the third transistor being connected to a trigger port of the RS trigger and to a power supply end through a fourth resistor, the enable signal or the disable enable signal being output from the drain of the third transistor, and a source of the third transistor being connected to the ground end;

[0025] a fourth transistor, a gate of the fourth transistor being connected to the short pulse trigger signal, a drain of the fourth transistor being connected to the power supply end through a fifth resistor, and a source of the fourth transistor being connected to the ground end.

[0026] Preferably, the delay unit comprises:

[0027] a first D trigger, a clock control port of the first D trigger being connected to the zero-crossing square wave signal;

[0028] a fifth transistor, a gate of the fifth transistor being connected to the enable signal or the disable enable signal, a drain of the fifth transistor being connected to a set port of the first D trigger and to a power supply end through a sixth resistor, and a source of the fifth transistor being connected to the ground end;

[0029] a second D trigger, a clock control port of the second D trigger being connected to an output port of the first D trigger, and an output port of the second D trigger outputting the delayed zero-crossing square wave signal.

[0030] Preferably, the short pulse generation unit comprises:

[0031] a sixth transistor, a gate of the sixth transistor being connected to the delayed zero-crossing square wave signal, a drain of the sixth transistor being connected to a power supply end through a seventh resistor, and a source of the sixth transistor being connected to the ground end;

[0032] a second monostable trigger, a trigger port of the second monostable trigger being connected to the power supply end through an eighth resistor and to the sixth transistor drain through a fourth capacitor, and an output port of the second monostable trigger outputting the short pulse trigger signal.

[0033] Preferably, the device failure detection unit further comprises:

[0034] a failure indicator lamp, an anode of the failure indicator lamp is connected to a voltage source through a second current-limiting resistor, a cathode of the failure indicator lamp is connected to the device under test and the ground through a third current-limiting resistor.

[0035] Preferably, the current tolerance of the controlled switch is greater than 5 times the current tolerance of the device under test.

[0036] Preferably, the second timing module is connected to the short pulse generation unit and is further used for resetting and latching the short pulse trigger signal and outputting a disconnect enable signal to the delay unit so as to disable the delay unit.

[0037] The technical scheme of the present application has the following advantages or beneficial effects:

[0038] The present application provides a self-adaptive simple and convenient surge test circuit, which realizes pure hardware logic trigger function through a logic gate circuit, does not need to purchase complex test equipment, and only uses an oscilloscope, an alternating current power supply and other infrastructures to verify the device characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 For the preferred embodiment of the present application, the circuit schematic diagram of the surge current test circuit of the electronic component is shown in the figure.

[0040] Figure 2 For the preferred embodiment of the present application, the flowchart of the surge current test method of the electronic component is shown in the figure.

[0041] Figure 3 For the preferred embodiment of the present application, the waveform diagram of the surge current test of the electronic component is shown in the figure. DETAILED DESCRIPTION

[0042] The technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0043] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0044] The present application will be further described below with reference to the drawings and specific embodiments, but is not limited by the present application.

[0045] In the preferred embodiment of the present application, based on the above-mentioned problems existing in the prior art, a surge current test circuit for electronic components is provided, which comprises a main voltage reduction unit, an AC sampling unit 1, a sine wave shaping unit 2, a key unit, a key debounce unit 4, a delay unit 3, a short pulse generation unit 5, a driving test unit, and a component to be tested. As shown in the figure, wherein: Figure 1

[0046] The main voltage reduction unit comprises an isolation transformer, a first current limiting resistor RL, a component to be tested 6, a first bypass load RL1, and a second bypass load RL2. The primary side L1 of the isolation transformer is connected to a power supply end AC, the secondary side L2 of the isolation transformer is connected to the component to be tested 6 through the first current limiting resistor RL, and the primary side and the secondary side of the isolation transformer are respectively connected in parallel with a bypass load, wherein the primary side L1 of the isolation transformer is connected in parallel with the first bypass load RL1, and the secondary side L2 of the isolation transformer is connected in parallel with the second bypass load RL2.

[0047] The component to be tested 6 can be a SiC SBD device or a SiC MOSFET device, and can also be other electronic components, such as a low-voltage Trench MOS device, a shielded gate SGT MOS device, a super-junction SJ MOSFET device, a TVS diode device, a silicon fast recovery diode FRD device, an IGBT internally integrated diode FRD device, a gallium nitride transistor GaN HETM device, a fast-melting fuse, a recoverable fuse, and various composite fuses, etc., which can all be subjected to surge testing by using the circuit of the present application, and different components to be tested 6 can be freely switched.

[0048] The AC sampling unit 1 is connected between the power supply end AC and the ground end, and is used to sample the high-voltage AC after the power supply end AC is powered on to obtain a sampling signal.

[0049] The sine wave shaping unit 2 is connected to the AC sampling unit 1, and is used to perform sine wave shaping processing on the sampling signal and output a zero-crossing square wave signal.

[0050] The key unit is used to output a key signal according to an external control.

[0051] The key debounce unit 4 comprises a first timing module connected to the key unit, and a second timing module connected to the first timing module, which is used to perform delay debounce processing on the key signal to obtain an enable signal.

[0052] The delay unit 3 is connected to the sine wave shaping unit 2 and the key debounce unit 4, respectively, and is used to enable the delay unit under the action of the enable signal, perform delay processing on the zero-crossing square wave signal, and start period counting. ​

[0053] The short pulse generating unit 5 is connected to the delay unit 3 and is used to obtain a short pulse trigger signal according to the delayed zero-crossing square wave signal.

[0054] The drive test unit is connected to the short pulse generating unit 5 and includes a driver SW and a controlled switch M0. The controlled switch M0 is connected to the device under test 6. The driver SW outputs a driving signal according to the short pulse trigger signal to drive the controlled switch M0 to be turned on, so that the device under test 6 can bear the periodic current to complete the surge test of the device under test 6.

[0055] Specifically, after power-on, the AC sampling unit 1 performs voltage division sampling on the high-voltage AC power to obtain a sampling signal. The sampling signal is output after being processed by the sine wave shaping unit 2 to output a zero-crossing square wave signal. At this time, the delay unit 3 only receives the zero-crossing square wave signal without delay processing before receiving the enable signal. The waiting key unit outputs a key signal after triggering. The key signal is output after delay and anti-jitter processing by the key anti-jitter unit 4 to output the enable signal to the delay unit 3. The delay unit 3 performs counting after receiving the enable signal, and performs delay processing on the zero-crossing square wave signal output by the sine wave shaping unit 2. Then, the short pulse generating unit 5 processes the delayed zero-crossing square wave signal and outputs a short pulse trigger signal to the driver SW. The driver SW drives the controlled switch M0 to be turned on. The device under test 6 is turned on to perform surge test on the device under test 6. The controlled switch M0 can be turned off automatically after the sine period ends to realize single-period surge test on the device under test 6.

[0056] At the same time, the short pulse trigger signal is output after being processed by the second timing module to output a disconnection enable signal. The delay unit 3 only receives the zero-crossing square wave signal without delay processing and performs counting reset for the next time.

[0057] As a preferred embodiment, the AC sampling unit 1 includes a first capacitor C1 and a second capacitor C2 connected in series between the power supply end AC and the ground end. The sampling signal is output from the connection between the first capacitor C1 and the second capacitor C2.

[0058] As a preferred embodiment, the sine wave shaping unit 2 includes:

[0059] A Schmitt trigger U3. The trigger port TRIG and the reset lock port THRS of the Schmitt trigger U3 are connected to the sampling signal.

[0060] A first transistor M1. The gate of the first transistor M1 is connected to the output port of the Schmitt trigger U3. The drain of the first transistor M1 is connected to the power supply end VDD through a first resistor R1, and the zero-crossing square wave signal is output from the drain of the first transistor M1. The source of the first transistor M1 is connected to the ground end.

[0061] Specifically, the Schmidt trigger U3 is composed of NE555, and the NE555 includes eight ports, i.e. a ground port GND, a trigger port TRIG, an output port OUT, a reset port RST, a control port CV, a reset lock port THRS, a discharge port DIS and a power supply port VCC.

[0062] The ground port GND is connected to a ground end, the trigger port TRIG and the reset lock port THRS are connected to the connection of the first capacitor C1 and the second capacitor C2, for receiving a sampling signal, the output port OUT is connected to the gate of the first transistor M1, the reset port RST and the power supply port VCC are connected to a power supply end VDD, the control port CV is connected to the ground end through a capacitor C31, and the discharge port DIS is suspended.

[0063] The resistance R31 and the resistance R32 are connected in series between the power supply end VDD and the ground end, and the connection of the resistance R31 and the resistance R32 is connected to the reset lock port THRS of the NE555.

[0064] As a preferred implementation, the first timing module includes:

[0065] The gate of the second transistor M2 is connected to a key signal, the drain of the second transistor M2 is connected to the power supply end VDD through a second resistance R2, and the source of the second transistor M2 is connected to the ground end.

[0066] The trigger port TRIG of the first monostable trigger U1 is connected to the power supply end VDD through a third resistance R3 and connected to the drain of the second transistor M2 through a third capacitor C3, and the output port OUT of the first monostable trigger U1 is connected to the second timing module.

[0067] Specifically, the first monostable trigger U1 is composed of NE555, wherein the ground port GND of the NE555 is connected to the ground end, the trigger port TRIG is connected to the drain of the second transistor M2 through the third capacitor C3, the output port OUT is connected to the second timing module, the reset port RST and the power supply port VCC are connected to the power supply end VDD, the control port CV is connected to the ground end through the capacitor C11, and the resistance R11 and the capacitor C12 are connected in series between the power supply end VDD and the ground end, and the connection of the resistance R11 and the capacitor C12 is connected to the discharge port DIS and the reset lock port THRS of the NE555.

[0068] As a preferred implementation, the second timing module includes:

[0069] The reset lock port THRS of the RS trigger U2 is connected to the output of the first timing module.

[0070] a third transistor M3, a gate of the third transistor M3 is connected with an output port OUT of the RS flip-flop U2, a drain of the third transistor M3 is connected with a power supply end VDD through a fourth resistor R4, an enable signal or a disable signal is outputted from the drain of the third transistor M3, and a source of the third transistor M3 is connected with a ground end;

[0071] a fourth transistor M4, a gate of the fourth transistor M4 is connected with the short pulse trigger signal, a drain of the fourth transistor M4 is connected with a trigger port TRIG of the RS flip-flop U2 and the power supply end VDD through a fifth resistor R5, and a source of the fourth transistor M4 is connected with the ground end.

[0072] Specifically, the RS flip-flop U2 is composed of NE555, wherein a ground port GND of the NE555 is connected with the ground end, the trigger port TRIG is connected with the drain of the fourth transistor M4, the output port OUT is connected with the gate of the third transistor M3, the reset port RST and the power supply port VCC are connected with the power supply end VDD, the control port CV is connected with the ground end through the capacitor C21, the reset lock port THRS is connected with the output port OUT of the first monostable trigger U1, and the discharge port DIS is suspended.

[0073] Further, in order to avoid logic errors caused by continuously pressing the switch S1 during operation, the specifications of the resistor R11 and the capacitor C12 can be adjusted to control the duration of the set pulse, so that the first monostable trigger U1 and the RS flip-flop U2 synchronously form the key debouncing and signal maintaining functions.

[0074] As a preferred implementation, the second timing module is connected with the short pulse generating unit, and is further configured to reset and latch the short pulse trigger signal, and output a disable signal to the delay unit to disable the delay unit.

[0075] As a preferred implementation, the delay unit comprises:

[0076] a first D flip-flop U4, a clock control port CLK of the first D flip-flop U4 is connected with the zero-crossing square wave signal;

[0077] a fifth transistor M5, a gate of the fifth transistor M5 is connected with the enable signal or the disable signal, a drain of the fifth transistor M5 is connected with a set port PRE of the first D flip-flop U4 and the power supply end VDD through a sixth resistor R6, and a source of the fifth transistor M5 is connected with the ground end;

[0078] a second D flip-flop U5, a clock control port CLK of the second D flip-flop U5 is connected with an output port of the first D flip-flop U4, and an output port of the second D flip-flop U5 outputs the delayed zero-crossing square wave signal.

[0079] Specifically, the delay unit is composed of two D flip-flops, which are used to flip and delay the zero-crossing square wave signal output by the sine wave shaping unit 2 twice.

[0080] The priority of the set port PRE of the first D flip-flop U4 is higher than that of the clock control port CLK. When the first D flip-flop U4 does not receive the enable signal provided by the fifth transistor M5 or receives the disconnected enable signal, it only receives the zero-crossing square wave signal output by the Schmitt trigger U3 but does not perform delay processing. When the enable signal provided by the fifth transistor M5 is received, the first D flip-flop U4 is enabled after being inverted by the fifth transistor M5, and the counting starts.

[0081] As a preferred embodiment, the short pulse generating unit comprises:

[0082] The gate of the sixth transistor M6 is connected to the delayed zero-crossing square wave signal, the drain of the sixth transistor M6 is connected to the power supply end through a seventh resistor R7, and the source of the sixth transistor M6 is connected to the ground end.

[0083] The trigger port TRIG of the second monostable trigger U6 is connected to the power supply end through an eighth resistor R8 and connected to the drain of the sixth transistor through a fourth capacitor C4, and the short pulse trigger signal is output from the output port of the second monostable trigger U6.

[0084] Specifically, the second monostable trigger U6 is also composed of NE555, wherein the ground port GND of NE555 is connected to the ground end, the trigger port TRIG is connected to the drain of the sixth transistor through the fourth capacitor C4, the output port OUT is connected to the gate of the fourth transistor M4 and the driver SW respectively, the reset port RST and the power supply port VCC are connected to the power supply end VDD, the control port CV is connected to the ground end through the capacitor C61, and the resistor R61 and the capacitor C62 are connected in series between the power supply end VDD and the ground end, and the connection point of the resistor R61 and the capacitor C62 is connected to the discharge port DIS and the reset lock port THRS of NE555.

[0085] Further, the resistor R61 and the capacitor C62 can be adjusted. By adjusting the specifications of the resistor R61 and the capacitor C62, the length of the short pulse trigger signal can be controlled. Generally, the length of the short pulse trigger signal does not exceed one twentieth of the entire frequency period.

[0086] Further, the controlled switch M0 can be a transistor switch such as a MOSFET, and by adjusting the specifications of the resistor R61 and the capacitor C62, different angles of sine period off and multiple sine period surge tests can be realized. By replacing the specifications of the circuit components, the single trigger time can be adjusted, and the circuit parameters can be switched adaptively, and the surge load current limit value can be adjusted.

[0087] As a preferred embodiment, the device failure detection unit comprises:

[0088] A failure indicator lamp D1, the anode of the failure indicator lamp D1 is connected to a voltage source V2 through a second current-limiting resistor R71, the cathode of the failure indicator lamp D1 is connected to the to-be-tested device 6 and the ground through a third current-limiting resistor R72.

[0089] Specifically, whether the to-be-tested device 6 is damaged or not is indicated by the failure indicator lamp D1. If the to-be-tested device 6 is damaged, the voltage source V2 has a closed current loop, and the failure indicator lamp D1 is always on.

[0090] As a preferred embodiment, in order to avoid failure, the current tolerance of the controlled switch is always greater than 5 times the current tolerance of the to-be-tested device.

[0091] Further, the to-be-tested device 6 is not limited to unidirectional conduction devices, but can also be bidirectional conduction devices. At this time, a resistor needs to be connected in series at the upper end of the load to protect the controlled switch M0.

[0092] Further, a current probe or a shunt can be provided, which is connected to the to-be-tested device 6 and used to sample the peak current for surge test observation.

[0093] Further, the controlled switch M0 and the first current-limiting resistor RL can adopt different specifications, and 1A-500A current adjustment can be realized in a single sine period.

[0094] Further, in actual circuit construction, the driver SW can be realized by using a conventional gate driver or a totem pole circuit connected externally after the signal is inverted.

[0095] Further, by jumpering the shorting wire to the input of the Schmidt trigger U3 and the second monostable trigger U6, the repeated triggering of the sine period can be realized, and the multi-period surge test can be realized.

[0096] Further, the circuit of the present application is powered by an auxiliary power supply, or can also be powered by a linear voltage reduction after rectification of the mains.

[0097] In the above preferred embodiment, the surge current test circuit using the above electronic components is used for surge test, and the steps are as follows:

[0098] After power on, the first capacitor C1 and the second capacitor C2 sample the high-voltage alternating current, and then send the sampling signal to the Schmidt trigger U3 for sine wave shaping, and then send the signal to the delay unit through the first transistor M1, at this time, if the first D trigger U4 does not receive the pull-down enable signal provided by the fifth transistor M5, only the zero-crossing square wave signal output by the Schmidt trigger U3 is received.

[0099] At this time, the manual press key switch S1 is pressed, and the output key signal is sent to the first monostable trigger U1 through the pulse response of the third capacitor C3 for fixed delay, and then sent to the RS trigger U2, and then the enable signal is output through the RS trigger U2, and then the first D trigger U4 is enabled through the fifth transistor M5, the delay unit starts to work and starts to count, at the same time, the first D trigger U4 and the second D trigger U5 flip the received zero-crossing square wave signal twice, and then send it to the second monostable trigger U6 through the pulse response of the fourth capacitor C4, and then send it to the driver SW through the resistance R61 and the capacitor C62 to adjust the length of the short pulse trigger signal, and then drive the controlled switch M0 to open through the driver SW, and then perform surge test on the to-be-tested component 6, and the controlled switch M0 can be automatically turned off after the sine period ends, so that the single-period surge test of the to-be-tested component 6 is realized.

[0100] At the same time, the second monostable trigger U6 also sends the short pulse trigger signal to the RS trigger U2 for resetting and latching, and the RS trigger U2 outputs the disconnection enable signal according to the short pulse trigger signal, and then the disconnection enable signal is sent to the setting port PRE of the first D trigger U4 through the fifth transistor M5, so that the first D trigger U4 is not enabled, at this time, only the zero-crossing square wave signal is received, but no delay processing is performed, and the period count is no longer output, so that the closed-loop control of the surge test is realized, so as to facilitate the manual trigger of the key switch S1 next time.

[0101] The sine surge current of the embodiment of the application is adjustable, and the surge current bearing period and size of the to-be-tested component 6 can be directly changed according to the mains wave or the conventional laboratory alternating current source. The pure hardware logic trigger function is realized through the logic gate circuit, and a self-adaptive simple and convenient surge test circuit is provided for verifying the device characteristics only by using the oscilloscope, the alternating current source and other basic infrastructures without purchasing complex test equipment. Meanwhile, the circuit of the application can also be applied to the research on the surge current of the parasitic diode of the power device and the reliability of the device.

[0102] The above description is only the preferred embodiment of the application, and does not limit the implementation and protection scope of the application. It should be realized by those skilled in the art that any equivalent replacement and obvious changes made according to the content of the specification and the drawings should be included in the protection scope of the application.

Claims

1. A surge current testing circuit for electronic components, characterized in that, include: A main step-down test unit includes an isolation transformer. The primary side of the isolation transformer is connected to a power supply terminal, and the secondary side of the isolation transformer is connected to a device under test through a first current-limiting resistor. A bypass load is connected in parallel to the primary and secondary sides of the isolation transformer. An AC sampling unit is connected between the power supply terminal and the grounding terminal, and is used to perform voltage division sampling on the high-voltage AC power after the power supply terminal is powered on to obtain a sampling signal; A sine wave shaping unit is connected to the AC sampling unit and is used to perform sine wave shaping processing on the sampled signal and output a zero-crossing square wave signal. A button unit is used to output a button signal according to an external control. A button debouncing unit includes a first timing module connected to the button unit; and a second timing module connected to the first timing module, used to perform delay debouncing processing on the button signal to obtain an enable signal. A delay unit is connected to the sine wave shaping unit and the key debouncing unit respectively. It is used to enable the delay unit under the action of the enable signal. The delay unit performs delay processing on the zero-crossing square wave signal and starts period counting. A short pulse generation unit, connected to the delay unit, is used to process the delayed zero-crossing square wave signal to obtain a short pulse trigger signal. A drive test unit is connected to the short pulse generation unit. The drive test unit includes a driver and a controlled switch. The controlled switch is connected to the device under test. The driver outputs a drive signal according to the short pulse trigger signal to drive the controlled switch to turn on. The device under test is subjected to periodic current to complete the surge test of the device under test.

2. The surge current testing circuit for electronic components according to claim 1, characterized in that, The AC sampling unit includes a first capacitor and a second capacitor, which are connected in series between the power supply terminal and the ground terminal, and output the sampling signal from the connection point of the first capacitor and the second capacitor.

3. The surge current testing circuit for electronic components according to claim 1, characterized in that, The sine wave shaping unit includes: A Schmitt trigger, wherein the trigger port and reset lock port of the Schmitt trigger are connected to the sampling signal; A first transistor, the gate of the first transistor is connected to the output port of the Schmitt trigger, the drain of the first transistor is connected to the power supply terminal through a first resistor, and the zero-crossing square wave signal is output from the drain of the first transistor, and the source of the first transistor is connected to the ground terminal.

4. The surge current testing circuit for electronic components according to claim 1, characterized in that, The first timing module includes: A second transistor, the gate of which is connected to the button signal, the drain of which is connected to the power supply terminal through a second resistor, and the source of which is connected to the ground terminal; A first monostable multivibrator is provided, wherein the trigger port of the first monostable multivibrator is connected to the power supply terminal through a third resistor and to the drain of the second transistor through a third capacitor, and the output port of the first monostable multivibrator is connected to the second timing module.

5. The surge current testing circuit for electronic components according to claim 1, characterized in that, The second timing module includes: An RS trigger, wherein the reset lockout port of the RS trigger is connected to the output of the first timing module; A third transistor, the gate of which is connected to the output port of the RS flip-flop, the drain of which is connected to the power supply terminal through a fourth resistor, the enable signal or the de-enable signal is output from the drain of the third transistor, and the source of which is connected to the ground terminal. A fourth transistor, the gate of which is connected to the short pulse trigger signal, the drain of which is connected to the trigger port of the RS flip-flop and to the power supply terminal through a fifth resistor, and the source of which is connected to the ground terminal.

6. The surge current testing circuit for electronic components according to claim 5, characterized in that, The delay unit includes: A first D flip-flop, wherein the clock control port of the first D flip-flop is connected to the zero-crossing square wave signal; A fifth transistor, the gate of which is connected to the enable signal or the off enable signal, the drain of which is connected to the set port of the first D flip-flop and to the power supply terminal through a sixth resistor, and the source of which is connected to the ground terminal. A second D flip-flop is provided, the clock control port of the second D flip-flop is connected to the output port of the first D flip-flop, and the output port of the second D flip-flop outputs the delayed zero-crossing square wave signal.

7. The surge current testing circuit for electronic components according to claim 1, characterized in that, The short pulse generation unit includes: A sixth transistor, the gate of which is connected to the delayed zero-crossing square wave signal, the drain of which is connected to the power supply terminal through a seventh resistor, and the source of which is connected to the ground terminal. A second monostable multivibrator is provided, wherein the trigger port of the second monostable multivibrator is connected to the power supply terminal through an eighth resistor and to the drain of the sixth transistor through a fourth capacitor, and the short pulse trigger signal is output from the output port of the second monostable multivibrator.

8. The surge current testing circuit for electronic components according to claim 1, characterized in that, It also includes a device failure detection unit, which comprises: A failure indicator light is provided, wherein the anode of the failure indicator light is connected to a voltage source through a second current-limiting resistor, and the cathode of the failure indicator light is connected to the component under test and to the ground terminal through a third current-limiting resistor.

9. The surge current testing circuit for electronic components according to claim 1, characterized in that, The current withstand capability of the controlled switch is greater than 5 times the current withstand capability of the device under test.

10. The surge current testing circuit for electronic components according to claim 1, characterized in that, The second timing module is connected to the short pulse generation unit and is also used to reset and latch the short pulse trigger signal, and output a disconnect enable signal to the delay unit so that the delay unit is disabled.

Images