A mainboard and a debugging method

Abstract

Embodiments of the present application provide a mainboard and a debugging method, and relate to the technical field of computing devices, which can effectively reduce the debugging cost and improve the efficiency of fault debugging. The mainboard comprises a BMC and an identification circuit, the BMC is coupled with the identification circuit; the identification circuit is configured to identify the type of a central processing unit (CPU) to be debugged, and send indication information to the BMC; the indication information is used to indicate the type of the CPU to be debugged; the BMC is configured to receive the indication information from the identification circuit, and based on the type of the CPU to be debugged, simulate output of a debugging signal matching the type of the CPU; wherein the debugging signal comprises a first debugging signal sent by the BMC and a second response signal sent by the CPU to be debugged; the second response signal is a response signal output by the CPU to be debugged in response to the first debugging signal; the first debugging signal and the second response signal satisfy the signal characteristics of a debugging tool corresponding to the CPU to be debugged. The embodiments of the present application can be used in the process of CPU fault debugging.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computing device, and particularly, to a mainboard and a debugging method. BACKGROUND

[0002] When a computing device fails, the cause of the failure needs to be found and the computing device needs to be maintained in time to restore the normal operation of the computing device. Currently, a commonly used method is to manually use a debugging tool to detect and eliminate the failure of the computing device.

[0003] For example, for a computing device with an AMD type CPU, a hardware detection tool (HDT) is used for debugging. For a computing device with an INTEL type CPU, an extended debug port (XDP) tool is used for debugging. However, the HDT tool and the XDP tool both have the characteristic of high tool cost, resulting in high computing device operation and maintenance cost, which is not suitable for large-scale use. Moreover, a staff needs to be on site to adjust the debugging parameters of the debugging tool, which is low in debugging efficiency. SUMMARY

[0004] Embodiments of the present application provide a mainboard and a debugging method, which can effectively reduce the debugging cost and improve the efficiency of failure debugging.

[0005] In a first aspect, embodiments of the present application provide a mainboard, which comprises a baseboard management controller (BMC) and an identification circuit, the BMC is coupled with the identification circuit; the identification circuit is configured to identify the type of a central processing unit (CPU) to be debugged, and send indication information to the BMC; the indication information is used to indicate the type of the CPU to be debugged; the BMC is configured to receive the indication information from the identification circuit, and based on the type of the CPU to be debugged, simulate output of a debugging signal matching the type of the CPU to be debugged; wherein the debugging signal comprises a first debugging signal sent by the BMC and a second response signal sent by the CPU to be debugged; the second response signal is a response signal output by the CPU to be debugged in response to the first debugging signal; the first debugging signal and the second response signal satisfy the signal characteristics of a debugging tool corresponding to the CPU to be debugged.

[0006] In a possible implementation manner, the BMC comprises a plurality of simulated debugging tools, and each simulated debugging tool corresponds to a type of CPU.

[0007] In another possible implementation manner, the BMC further includes a control device, a debugging driver, and a joint test action group (JTAG) pin used for outputting a debugging signal; the control device is configured to receive indication information from the identification circuit; the control device is further configured to send a control instruction to the debugging driver based on a type of the CPU to be debugged indicated by the indication information; the control instruction is used to instruct to call a target simulation debugging tool corresponding to the type of the CPU to be debugged; the target simulation debugging tool is one of a plurality of simulation debugging tools; and the debugging driver is configured to call the target simulation debugging tool based on the control instruction, acquire a debugging signal generated by the target simulation debugging tool, and output the debugging signal through the JTAG pin.

[0008] In another possible implementation manner, the control device is specifically configured to: when the CPU to be debugged is of the first type, send a control instruction for calling the simulation HDT tool to the debugging driver; and when the CPU to be debugged is of the second type, send a control instruction for calling the simulation extended XDP tool to the debugging driver.

[0009] In another possible implementation manner, the identification circuit includes a complex programmable logic device (CPLD); one end of the CPLD is coupled with the CPU to be debugged, and the other end of the CPLD is coupled with the BMC; the CPLD is configured to receive the type reported by the CPU to be debugged; and the CPLD is further configured to send the type of the CPU to be debugged to the BMC through a local bus.

[0010] In another possible implementation manner, the mainboard further includes a switch chip; one end of the switch chip is coupled with the BMC, and the other end of the switch chip is coupled with the CPU to be debugged; voltages at the two ends of the switch chip are different; and the switch chip is configured to convert a level of the first debugging signal into a level that can be recognized by the CPU to be debugged, or convert a level of the second response signal into a level that can be recognized by the BMC.

[0011] In another possible implementation manner, the switch chip includes a remote debugging channel; and the BMC is further configured to send a control signal to the switch chip, where the control signal is used to instruct the switch chip to transmit a debugging signal between the BMC and the CPU to be debugged through the remote debugging channel.

[0012] In another possible implementation manner, the BMC establishes a network communication connection with a user-side device; and the BMC is further configured to enable the remote debugging function in response to an operation instruction issued by the user through the user-side device.

[0013] In yet another possible implementation manner, the mainboard further comprises: a slot carrying at least one debugging interface, the slot being coupled with the switch chip, and the slot supporting plugging of a debugging tool; the debugging tool is configured with the debugging interface, and when the debugging tool is plugged into the slot, the debugging tool is configured to debug the CPU to be debugged through the debugging interface.

[0014] The mainboard provided in the embodiments of the present application has clear and simple link constitution and is convenient to implement. Moreover, the hardware BMC simulation test tool can reduce the cost of purchasing HDT / XDP tools. In addition, the BMC can automatically simulate the corresponding debugging tool based on the type of the CPU, and therefore, the mainboard provided in the embodiments of the present application has stronger universality and can be applied to common INTEL type computing devices or AMD type computing devices. Furthermore, the BMC supports network communication, and therefore, remote debugging can be implemented, and the staff can locate the CPU fault reason without going to the site of the computer room, thereby improving the research and development efficiency. In summary, the mainboard provided in the embodiments of the present application can meet the debugging requirements in the scene of large-scale computing device cluster and is more suitable for the future trend of high computing power and big data.

[0015] In a second aspect, the embodiments of the present application provide a debugging method, which is applied to a mainboard, the mainboard comprising: a BMC and a recognition circuit; the method comprising: receiving indication information sent by the recognition circuit, the indication information being used to indicate the type of the CPU to be debugged; simulating the characteristics of the debugging tool corresponding to the type of the CPU to be debugged based on the type of the CPU to be debugged indicated by the indication information, and outputting a debugging signal.

[0016] In a possible implementation manner, the simulating the characteristics of the debugging tool corresponding to the type of the CPU to be debugged and outputting the debugging signal comprises: when the CPU to be debugged is of a first type, simulating the characteristics of an HDT tool and outputting the debugging signal; and when the CPU to be debugged is of a second type, simulating the characteristics of an XDP tool and outputting the debugging signal.

[0017] In a third aspect, the embodiments of the present application provide a computing device, comprising: a processor and a memory; the memory stores instructions executable by the processor; and the processor is configured to execute the instructions, so that the computing device implements the method in the second aspect.

[0018] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, comprising: computer software instructions; when the computer software instructions run in a computing device, the computer implements the method in the second aspect.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a computing device, causes the computing device to perform the steps of the method described in the first aspect to implement the method described in the second aspect.

[0020] The advantages of the second aspect to the fifth aspect can refer to the corresponding description of the first aspect, and will not be described again. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of a mainboard according to an embodiment of the present application is provided.

[0022] Figure 2 A schematic diagram of a BMC according to an embodiment of the present application is provided.

[0023] Figure 3 A schematic diagram of another mainboard according to an embodiment of the present application is provided.

[0024] Figure 4 A schematic diagram of another mainboard according to an embodiment of the present application is provided.

[0025] Figure 5 A schematic diagram of a HDT tool debugging according to an embodiment of the present application is provided.

[0026] Figure 6 A schematic diagram of another mainboard according to an embodiment of the present application is provided.

[0027] Figure 7 A schematic diagram of a remote debugging according to an embodiment of the present application is provided.

[0028] Figure 8 A schematic diagram of a debugging method according to an embodiment of the present application is provided.

[0029] Figure 9 A schematic diagram of a computing device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the embodiments of the present application.

[0031] It should be noted that in the embodiments of the present application, the words such as "exemplarily" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "exemplarily" or "for example" are intended to present the relevant concept in a specific manner.

[0032] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the embodiments of the present application, the words such as "first", "second" are used to distinguish the same items or similar items with basically the same function and role, and those skilled in the art can understand that the words such as "first", "second" are not limited in quantity and execution order.

[0033] With the establishment of a new type of computing power network system, the number of computing devices (or servers) in the data center is increasing. In order to ensure the normal operation of the computing device, it is necessary to pay attention to the possible problems that may occur in the running process of the computing device and solve them in time. Among them, CPU is the core component of computing device, mainly used for interpreting computer instructions and processing data in computer software. All operations in the computing device are responsible for instructions, and the core component of instruction decoding and execution. Therefore, CPU failure will affect the operation of the entire computing device, and it is particularly important to debug the CPU to find the fault reason in time.

[0034] At present, the CPU debugging method of computing device generally uses debugging tools, which can collect debugging parameters and locate fault reasons when CPU fails. Moreover, the debugging tools used for different types of CPUs are inconsistent. For example, for INTEL type CPU, the mainboard or printed circuit board card deployed on it carries a slot with XDP interface, which is used to interface with XDP tool to perform chip-level or system-level debugging and fault positioning of INTEL type CPU. Similarly, for AMD type CPU, the mainboard deployed on it carries a slot with HDT interface, which is used to interface with HDT tool to perform chip-level or system-level debugging and fault positioning of AMD type CPU.

[0035] The current CPU debugging scheme first needs to purchase debugging tools, and the cost of XDP / HDT tool is relatively high, which does not support large-scale collection. Moreover, when the computing device in the computer room fails, the relevant staff needs to use the debugging tool to locate the fault on site. Therefore, the current CPU debugging scheme has low debugging efficiency, and due to cost constraints, it cannot be applied to the scenario of data center with more computing devices.

[0036] In this background art, the embodiment of the present application provides a mainboard which can be applied to a computing device, replaces the function of XDP / HDT tool through the existing module (such as BMC) of the computing device, and reduces the cost of fault debugging. In addition, the mainboard can also be connected with a user-side device through network communication, so that when the CPU fails, the staff enables the mainboard to work through the user-side device to realize remote debugging, without the need for the staff to use a debugging tool to locate the fault on site in the computer room, thereby improving the debugging efficiency and timeliness of fault handling.

[0037] The scheme provided by the embodiment of the present application will be described below in conjunction with the accompanying drawings of the specification.

[0038] Figure 1 A schematic diagram of a mainboard provided by the embodiment of the present application is shown in the figure. The mainboard can be deployed in a computing device.

[0039] As shown in the figure, the mainboard includes a BMC and a recognition circuit. The BMC is coupled with the recognition circuit. In addition, Figure 1 The mainboard further includes a CPU to be debugged. The BMC can be coupled with the CPU to be debugged to debug the CPU to be debugged. Figure 1 It can be understood that the mainboard and the mainboard carrying the CPU to be debugged can be the same mainboard (i.e., the CPU to be debugged is integrated on the mainboard), or the mainboard and the mainboard carrying the CPU to be debugged are different mainboards, which are not limited. In addition,

[0040] The figure is only an exemplary figure, and the debugging of one CPU to be debugged is taken as an example for illustration. Figure 2

[0041] The BMC is a special microcontroller arranged on the mainboard of the computing device, communicates with various types of hardware inside the computing device through various interfaces, and provides query and control functions to the local host or remote computing device through network, serial, local bus standard (peripheral component interconnect, PCI), etc. In the embodiment of the present application, for the convenience of description, the debugging mode based on BMC is referred to as a remote debugging mode, which is uniformly described herein.

[0042] In the embodiment of the present application, the recognition circuit is configured to recognize the type of the central processing unit (CPU) to be debugged, and send indication information to the BMC; the indication information is used to indicate the type of the CPU to be debugged.

[0043] ​The BMC is configured to receive the indication information from the identification circuit, simulate and output a debugging signal matching the type of the CPU based on the type of the CPU to be debugged; wherein the debugging signal comprises a first debugging signal sent by the BMC and a second response signal sent by the CPU to be debugged; the second response signal is a response signal output by the CPU to be debugged in response to the first debugging signal; and the first debugging signal and the second response signal satisfy the signal characteristics of the debugging tool corresponding to the CPU to be debugged.

[0044] Specifically, the BMC includes a plurality of simulation debugging tools, each of which corresponds to a type of CPU. The BMC can determine a target simulation debugging tool corresponding to the type of the CPU to be debugged from the plurality of simulation debugging tools based on the type of the CPU to be debugged, so as to debug the CPU to be debugged. The simulation debugging tool is a code-implemented software driver that can simulate the functions of different debugging tools. The specific code implementation can refer to related technical documents, and will not be described in detail here.

[0045] The specific implementation of the BMC simulating and outputting the debugging signal will be described in combination with the accompanying drawings. Figure 2 An assembly schematic diagram of a BMC is provided for the embodiments of the present application. As shown in Figure 2 The BMC includes a controller, a debugging driver, and a JTAG pin. The JTAG pin can be located in the hardware layer and is used to output a debugging signal, i.e., output a first debugging signal to the CPU to be debugged, and receive a second response signal output by the CPU to be debugged in response to the first debugging signal.

[0046] The controller can be located in the operating system layer and is configured to receive the indication information from the identification circuit. In addition, the controller is further configured to send a control instruction to the debugging driver based on the type of the CPU to be debugged indicated by the indication information; the control instruction is used to instruct to call a target simulation debugging tool corresponding to the type of the CPU to be debugged.

[0047] The above debugging driver can be located in the driver layer and is configured to call the target simulation debugging tool based on the control instruction, obtain a debugging signal generated by the target simulation debugging tool, and output the debugging signal through the JTAG pin. It should be noted that the above plurality of simulation debugging tools can be included in the debugging driver.

[0048] As an example, when the CPU to be debugged is of a first type, i.e., an AMD type, the controller is specifically configured to send a control instruction for calling a simulation HDT tool to the debugging driver. When the CPU to be debugged is of a second type, i.e., an INTEL type, the controller is specifically configured to send a control instruction for calling a simulation extended XDP tool to the debugging driver.

[0049] It can be understood that, based onFigure 2 As shown in the mainboard, the BMC on the mainboard in the computing device can be configured to have the ability of debugging tools, the CPU debugging is realized based on the hardware deployed in the mainboard, the cost is saved, and after power-on, the BMC can automatically simulate different debugging tools to facilitate debugging different types of CPUs, and the versatility is relatively strong.

[0050] Figure 3 Another composition schematic diagram of a mainboard provided by the embodiment of the application is provided. As shown in the mainboard, Figure 3 As shown in the mainboard, Figure 1 On the basis of the mainboard shown in the mainboard, the identification circuit includes a CPLD. One end of the CPLD is coupled with the CPU to be debugged, and the other end is coupled with the BMC. The CPLD is configured to receive the type reported by the CPU to be debugged, and send the type of the CPU to be debugged to the BMC through a local bus.

[0051] In some embodiments, the CPUs carried in the computing device are generally of the same type, for example, all are of a first type (AMD type) or all are of a second type (INTEL type). For the convenience of description, the computing device carrying the INTEL type CPU is referred to as the INTEL type computing device, and the computing device carrying the AMD type CPU is referred to as the AMD type computing device. In this scenario, if the mainboard provided by the embodiment of the application is applied to the INTEL type computing device, after the computing device is powered on, the CPU to be debugged can report its type to the CPLD through a general-purpose input / output (GPIO) pin. For example, the AMD type corresponds to the level value "10" on the GPIO pin, and the INTEL type corresponds to the level value "01" on the GPIO pin. The CPLD can determine the type of the CPU to be debugged according to the level value combination on the corresponding GPIO pin. Further, after the CPLD obtains the type of the CPU to be debugged, the CPLD can send the type of the CPU to be debugged to the BMC through a local bus between the CPLD and the BMC.

[0052] Further, if the CPU to be debugged is of the AMD type, the controller in the BMC can instruct the debugging driver to call the simulation HDT tool, obtain the debugging signal generated by the simulation HDT tool, and output the debugging signal through the JTAG pin. That is, the BMC can simulate the characteristics of the HDT tool to generate a debugging signal that meets the signal characteristics of the HDT tool. Similarly, if the CPU to be debugged is of the INTEL type, the BMC can simulate the characteristics of the XDP tool to generate a debugging signal that meets the signal characteristics of the XDP tool.

[0053] It should be understood that, based on Figure 3As shown in the mainboard, the embodiment of the present application can automatically obtain the type of the CPU to be debugged through the CPLD and send it to the BMC, so that the BMC can automatically simulate different types of debugging tools. Among them, the CPLD is a commonly used component in computing devices, so the link provided by the embodiment of the present application to constitute the mainboard is simple, does not increase additional cost, and can be widely used in data centers and other scenarios to improve research and development efficiency and reduce cost.

[0054] It should be noted that, since the level output / receivable by the BMC side is inconsistent with the level output / receivable by the CPU side, in order to make the signal meet the level requirements of the opposite end / receiving end, the debugging signal needs to be converted in level during the debugging of the BMC to the CPU to be debugged, so that the debugging signal meets the level requirements of the BMC side and the CPU side to be debugged. The specific scheme is as shown in Figure 4 .

[0055] Figure 4 Another schematic diagram of the composition of the mainboard provided by the embodiment of the present application is shown in Figure 3 , based on the mainboard shown in the above embodiment, a switch chip is added. Among them, one end of the switch chip is coupled with the BMC, and the other end of the switch chip is coupled with the CPU to be debugged; the voltages at both ends of the switch chip are different.

[0056] The switch chip is configured to convert the level of the first debugging signal to a level recognizable by the CPU to be debugged; or convert the level of the second response signal to a level recognizable by the BMC.

[0057] In some embodiments, the switch chip is an intermediate device connected between the CPU to be debugged and the BMC, which realizes the signal interaction between the BMC and the CPU while also converting the level of the debugging signal. Specifically, the BMC outputs the first debugging signal to the switch chip, and the switch chip converts the level of the first debugging signal to a level recognizable by the CPU to be debugged, and outputs the first debugging signal after level conversion to the CPU to be debugged. Further, the CPU to be debugged can output the second response signal in response to the first debugging signal, and the switch chip converts the level of the second response signal to a level recognizable by the BMC, and outputs the second response signal after level conversion to the BMC. It should be noted that the second response signal carries the debugging parameters (such as the register list of the CPU) of the CPU to be debugged, and the BMC can analyze the debugging parameters to perform debugging work. As an example, the switch chip can be a chip of SGM65230HXTS16G / TR model.

[0058] For example, assume that the BMC side can receive a level of 3.3V and the CPU side can receive a level of 1.05V. In the first debug signal output by the BMC, the high level is 3.3V, and the switch chip needs to convert the high level in the first debug signal to 1.05V that can be recognized by the CPU, so as to obtain the first debug signal after level conversion and send it to the CPU to be debugged. Similarly, the high level of the second response signal output by the CPU to be debugged is 1.05V, and the switch chip needs to convert the high level in the second response signal from 1.05V to 3.3V, so as to obtain the second response signal after level conversion and send it to the BMC.

[0059] Optionally, in order to avoid manual on-site debugging and save labor costs, Figure 4 The application further includes a user side device, which can be a computer or a smart phone or the like, and the BMC can establish a network communication connection with the user side device, so as to realize remote control of the BMC on the CPU to be debugged by the user through network communication. For example, the network communication can be in the form of Ethernet, cellular network, wireless fidelity (WIFI) or the like.

[0060] When remote debugging is needed, the user (or staff) can issue an operation instruction through the user side device, and the BMC can enable the remote debugging function in response to the operation instruction. Further, in the process of remotely debugging the CPU to be debugged, the BMC can receive the second response signal output by the CPU to be debugged, extract relevant information such as debug parameters in the second response signal, and send it to the user side device through network communication so that the staff can analyze and determine the fault reason based on the debug parameters. For example, the debug parameters can be a register list of the CPU to be debugged, and the staff can compare the value of each item in the register list one by one to determine the fault reason. Correspondingly, the staff can also issue an instruction (such as an instruction to enable the motherboard to be remotely debugged) to the BMC through the user side device, so as to realize remote CPU debugging of the staff through network communication without going to the on-site machine room.

[0061] It can be understood that the motherboard provided by the embodiments of the application can realize the function of remote CPU debugging, greatly saving the labor resource cost. In the scene of a data center or the like, the remote debugging function can be used to realize batch correction, further improving the maintenance efficiency of the computing device.

[0062] Optionally, to ensure compatibility with existing debugging methods, the motherboard provided in this application embodiment also retains the function of manually debugging the CPU using debugging tools. In some embodiments, the motherboard further includes: a slot carrying at least one debugging interface, the slot being coupled to a switching chip, and the slot supporting the insertion of debugging tools; the debugging tool is configured with a debugging interface, and when the debugging tool is inserted into the slot, the debugging tool is configured to debug the CPU to be debugged through the debugging interface.

[0063] Taking HDT tool debugging as an example, Figure 5 This is a schematic diagram of an HDT tool debugging architecture provided in an embodiment of this application. The diagram includes the HDT tool, an HDT interface slot, a switching chip, and multiple AMD-type CPUs (such as...). Figure 1 (AMD CPU1 and AMD CPU2). One end of the switching chip connects to the HDT interface slot, and the other end connects to the AMD CPU. The HDT interface slot supports the insertion of HDT tools. In one possible implementation, the HDT tool can generate a first debug signal, which is then level-shifted by the switching chip and forwarded to the CPU. The first debug signal loops through each CPU (e.g., first through CPU1, then through CPU2) to obtain a second response signal. The switching chip can forward the second response signal to the HDT tool, which analyzes the second response signal to meet the needs of CPU debugging and fault location.

[0064] As mentioned earlier, the slot can be connected to either the XDP or HDT debugging tools to retain the functionality of on-site debugging. The following explanation uses a motherboard with two slots: one with an XDP interface and one with an HDT interface.

[0065] Combination Figure 6 To explain, Figure 6 This is a schematic diagram illustrating the composition of another motherboard provided in an embodiment of this application. For example... Figure 6 As shown, the motherboard is in Figure 4The mainboard shown further comprises a slot for mounting a debugging tool, which can support the plugging of an XDP debugging tool and an HDT debugging tool. Specifically, the slot can be an XDP interface slot (or seat) and an HDT interface slot. The XDP interface and the HDT interface are electrically connected to one end of the switch chip. The XDP interface slot is used to support the plugging of the XDP tool. If the computing device using the mainboard is a computing device carrying an INTEL type CPU, a worker can use the XDP tool on site, plug it into the XDP interface slot on the mainboard, and debug the INTEL type CPU through the debugging interface of the XDP tool. Similarly, the HDT interface slot is used to support the plugging of the HDT tool. If the computing device using the mainboard is a computing device carrying an AMD type CPU, a worker can use the HDT tool on site, plug it into the HDT interface slot on the mainboard, and debug the AMD type CPU through the debugging interface of the HDT tool.

[0066] Based on Figure 6 The mainboard shown allows users to independently select a manual debugging mode or a remote debugging mode according to their own needs, further improving the versatility of the mainboard provided by the embodiments of the application.

[0067] Figure 6 In the mainboard shown, the switch chip can further comprise a plurality of debugging channels (manual debugging channels and remote debugging channels, not shown in the figure) for transmitting debugging signals of different debugging modes (manual on-site debugging or BMC remote debugging).

[0068] Among them, for different debugging modes, the switch chip has different requirements for the level conversion of the debugging signal, and the debugging channels used to transmit the debugging signal are also different. For example, for the BMC-based remote debugging mode, the switch chip uses a remote debugging channel (which can be referred to as JTAG channel 1) to transmit the debugging signal. For the manual XDP tool debugging mode, the level-converted debugging signal is transmitted through an XDP debugging channel (for example, referred to as JTAG channel 2). For the manual HDT tool debugging mode, the level-converted debugging signal is transmitted through an HDT debugging channel (for example, referred to as JTAG channel 3). Therefore, different debugging modes require the switch chip to enable different debugging channels to meet different level conversion requirements.

[0069] It should be noted that which debug channel the switch chip uses by default can be set by default based on the use scenario. As mentioned earlier, the current computing device types are basically INTEL types or AMD types. For INTEL type computing devices, the worker can configure the switch chip to use the XDP debug channel by default in advance. For AMD type computing devices, the worker can configure the switch chip to use the HDT debug channel by default in advance. When on-site debugging of the CPU is needed, the worker can directly debug by connecting the debugging tool.

[0070] In the above scenario, since the debug channel of the switch chip is the artificial debug channel that supports on-site debugging of the debugging tool by default, when remote debugging is needed, the mainboard provided by the embodiment of the application also supports the function of switching the switch chip to the remote debug channel. The specific description is as follows:

[0071] In some embodiments, the BMC is configured to send a control signal to the switch chip, the control signal being used to instruct the switch chip to transmit the debug signal between the BMC and the CPU to be debugged through the remote debug channel (or enable the remote debug channel); the switch chip is specifically configured to control the transmission of the debug signal through the remote debug channel based on the control signal.

[0072] Wherein, when starting remote debugging, the BMC can automatically send a control signal to the switch chip to instruct the switch chip to switch the remote debug channel. Or, in response to the instruction of enabling remote debugging issued by the user-side device, the BMC sends a control signal to the switch chip. The embodiment of the application does not limit the specific implementation mode. During remote debugging, the switch chip can control the debug signal between the BMC and the CPU to be debugged to pass through the remote debug channel. Moreover, the switch chip also performs level conversion on the debug signal passing through itself according to the voltage requirement of the BMC side and the CPU side during remote debugging.

[0073] It should be noted that the mainboard provided by the embodiment of the application can be applied to a computing device with multiple CPUs. For example, a 4-way computing device or a more-way computing device can couple multiple CPUs in the form of a loopback circuit to debug multiple CPUs in batches, further enhancing the universality of the mainboard provided by the embodiment of the application.

[0074] Figure 7 A flowchart of a remote debugging process provided by the embodiment of the application is shown in FIG. 4. The specific implementation of the process is as follows: Figure 7The working process of the mainboard provided by the embodiment of the application is described. In the case of failure of the CPU of the computing device or the case of needing to debug the CPU, the CPLD in the mainboard can obtain the type of the failed CPU and report it to the BMC. After the BMC receives the type sent by the CPLD, the characteristics of the corresponding debugging tool are simulated based on the type of the failed CPU, and a debugging signal is output for debugging.

[0075] The technical solutions provided by the above embodiments at least have the following beneficial effects. The mainboard provided by the embodiment of the application has a clear and simple link structure and is easy to implement. Moreover, the hardware BMC can simulate the test tool, thereby reducing the cost of purchasing the HDT / XDP debugging tool.

[0076] In addition, the BMC can automatically simulate the corresponding debugging tool based on the type of the CPU. Therefore, the mainboard provided by the embodiment of the application has stronger universality and can be applied to common INTEL-type computing devices or AMD-type computing devices.

[0077] Furthermore, the BMC supports network communication, so that remote debugging can be implemented, and the staff can locate the cause of the CPU failure without going to the computer room, thereby improving the research and development efficiency. In summary, the mainboard provided by the embodiment of the application can meet the debugging requirements in the scenario of a large-scale computing device cluster and is more suitable for the future trend of high computing power and big data.

[0078] It can be seen that the above embodiments mainly provide an introduction to the embodiment of the application from the aspect of the hardware structure. Therefore, the debugging method provided by the embodiment of the application will be described in detail in combination with specific embodiments below, and the method can be applied to the above mainboard.

[0079] An exemplary flowchart of a debugging method provided by the embodiment of the application is shown in FIG. 8. Figure 8 As shown in FIG. 8, the debugging method provided by the embodiment of the application specifically includes the following steps: Figure 8

[0080] S801, receiving the indication information sent by the identification circuit.

[0081] The indication information is used to indicate the type of the CPU to be debugged.

[0082] In some embodiments, after the computing device is powered on, the CPU to be debugged can actively report its type to the identification circuit. Further, the identification circuit can send the indication information indicating the type to the BMC, and the BMC can receive the indication information sent by the identification circuit, so as to facilitate debugging.

[0083] S802, based on the type of the CPU to be debugged indicated by the indication information, simulating the characteristics of the debugging tool corresponding to the type of the CPU to be debugged, and outputting a debugging signal.​

[0084] In some embodiments, after the BMC obtains the type of the CPU to be debugged, the BMC can simulate the characteristics of the corresponding debugging tool based on the type, and output a debugging signal.

[0085] Specifically, the BMC can output a first debugging signal to the CPU to be debuged through a switch chip. After receiving the first debugging signal output by the switch chip, the CPU to be debugged can output a second response signal to the BMC through the switch chip in response to the first debugging signal. Further, the BMC can also analyze and obtain information such as a register list based on the second response signal, and report to a user-side device through network communication, so that the user determines the working condition, fault reason and other information of the CPU to be debugged by analyzing the register list, thereby achieving the purpose of remote debugging. In addition, in this process, the switch chip also converts the level of the first debugging signal and the second response signal. For specific description, please refer to the foregoing embodiments, which will not be repeated here.

[0086] Optionally, if the remote debugging channel in the switch chip is in a non-working state, the BMC can also send a control signal to the switch chip to switch to the remote debugging channel (or enable the remote debugging channel), so that the BMC sends a debugging signal to the CPU to be debugged through the remote debugging channel in the switch chip for remote debugging.

[0087] For example, when the CPU to be debugged is of a first type (AMD type), the BMC simulates the characteristics of the HDT tool and outputs a debugging signal. When the CPU to be debugged is of a second type (INTEL type), the BMC simulates the characteristics of the XDP tool and outputs a debugging signal. For specific simulation methods, please refer to the corresponding description in the hardware part described above, which will not be repeated here.

[0088] The beneficial effects brought by the debugging method can be referred to the description of the hardware part described above, which will not be repeated here.

[0089] It can be seen that the above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the method. In order to realize the above functions, the embodiments of the present application provide corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that the modules and algorithm steps of the examples described in combination with the embodiments disclosed in the present text can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0090] In the case of implementing the functions of the above-mentioned integrated modules in the form of hardware, the embodiment of the present application provides a schematic diagram of a composition of a computing device in which the above-mentioned mainboard can be mounted. As shown in Figure 9 The computing device 900 includes a processor 902, a communication interface 903, and a bus 904. Optionally, the computing device can further include a memory 901.

[0091] The processor 902 can be various exemplary logical blocks, modules and circuits described in combination with the disclosure of the embodiment of the present application. The processor 902 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure of the embodiment of the present application. The processor 902 can also be a combination of computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessor, etc.

[0092] The communication interface 903 is used to connect with other devices through a communication network. The communication network can be an Ethernet, a wireless access network, a wireless local area network (WLAN), etc.

[0093] The memory 901 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0094] As a possible implementation manner, the memory 901 can exist independently of the processor 902 or the BMC 905, and the memory 901 can be connected with the processor 902 or the BMC 905 through the bus 904, for storing instructions or program codes. When the processor 902 or the BMC 905 invokes and executes the instructions or program codes stored in the memory 901, the debugging method provided by the embodiment of the present application can be implemented.

[0095] In another possible implementation, the memory 901 can also be integrated with the processor 902.

[0096] The bus 904 can be an extended industry standard architecture (EISA) bus, etc. The bus 904 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 9 In the figure, only one thick line is used to represent the bus, but this does not mean that there is only one bus or only one type of bus.

[0097] Through the description of the above embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the computing device is divided into different functional modules to complete all or part of the functions described above.

[0098] The embodiment of the present application further provides a computer readable storage medium. All or part of the processes in the above method embodiments can be instructed by computer instructions to complete related hardware, and the program can be stored in the above computer readable storage medium. When the program is executed, the program can include the processes of the above method embodiments. The computer readable storage medium can be the memory of any of the preceding embodiments. The above computer readable storage medium can also be an external storage device of the computing device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the above computer readable storage medium can include both the internal storage unit of the computing device and the external storage device. The above computer readable storage medium is used to store the above computer program and other programs and data required by the computing device. The above computer readable storage medium can also be used to temporarily store data that has been output or will be output.

[0099] The embodiment of the present application further provides a computer program product, which contains a computer program, when the computer program product runs on a computer, makes the computer execute any one of the debugging methods provided in the above embodiments.

[0100] Although the present application embodiments have been described in connection with various embodiments, it will be understood that the application embodiments are capable of further modifications. Other variations and modifications of the present application embodiments will become apparent to those skilled in the art from this disclosure, whose objective is to enable any variations and modifications that come within the scope of the application embodiments. It is intended that the application embodiments cover any and all variations of the preferred embodiments. For the avoidance of doubt, the term "comprising" as used herein is synonymous with the term "including", and is used in the inclusive, rather than the exclusive or exhaustive, sense. That is, the term "comprising" as used herein is used to mean one or more of the listed elements or steps are present within the composition, product, method, process or apparatus, but not excluding others. The use of "one or more of" followed by a listing of elements or steps is specifically intended to convey that one or more of the listed elements or steps are present in the composition, product, method, process or apparatus. The use of the term "about" followed by a number or the use of the term "approximately" followed by a number is intended to mean that the number in question is likely to be close to the stated number within acceptable limits due to statistical variations. Where necessary, the number in question can be preceded by the term "at least" or "no more than" to indicate that the number in question can be greater than or less than the stated number. The use of the term "one" or "a" preceding the term "comprising" is not to be construed as excluding the presence of more than one, or more than a single, item. The use of the indefinite article "a" or "an" preceding the term "comprising" is not to be construed as excluding the presence of more than one, or more than a single, item. Individual processors or other units can implement several of the functions recited in the claims. Measures recited in mutually different dependent claims do not preclude their combination.

[0101] Although the present application embodiments have been described in connection with specific features thereof, it is to be understood that various modifications and alternatives can be apparent to those skilled in the art. Accordingly, the present description and drawings are to be regarded as illustrative in nature and are not to be considered as limiting to the scope of the application embodiments. It is to be understood that the application embodiments are capable of variation and modification and are, therefore, to be considered as being within the scope of the application embodiments as set out in the claims. It is to be understood that the application embodiments are capable of variation and modification and are, therefore, to be considered as being within the scope of the application embodiments as set out in the claims.

[0102] The above merely illustrates the specific application embodiments, but the protection scope of the application embodiments is not limited thereto, and any changes or replacements within the technical scope disclosed by the application embodiments should be covered within the protection scope of the application embodiments. Therefore, the protection scope of the application embodiments should be subject to the protection scope of the claims.

Claims

1. A main board, characterized by, The mainboard comprises a single board management controller (BMC) and an identification circuit, wherein the BMC is coupled with the identification circuit; The identification circuit is configured to identify a type of a central processing unit (CPU) to be debugged and send indication information to the BMC, wherein the indication information is used to indicate the type of the CPU to be debugged; The BMC is configured to receive the indication information from the identification circuit, simulate and output a debugging signal matching the type of the CPU to be debugged based on the type of the CPU to be debugged; The debugging signal comprises a first debugging signal sent by the BMC and a second response signal sent by the CPU to be debugged, wherein the second response signal is a response signal output by the CPU to be debugged in response to the first debugging signal, and the first debugging signal and the second response signal satisfy signal characteristics of a debugging tool corresponding to the CPU to be debugged.

2. The main plate of claim 1, wherein, The BMC comprises a plurality of simulation debugging tools, and each simulation debugging tool corresponds to a type of CPU.

3. The main plate of claim 2, wherein, The BMC further comprises a control device, a debugging driver and a joint test action group (JTAG) pin used to output a debugging signal; The control device is configured to receive indication information from the identification circuit; The control device is further configured to send a control instruction to the debugging driver based on the type of the CPU to be debugged indicated by the indication information, wherein the control instruction is used to instruct to call a target simulation debugging tool corresponding to the type of the CPU to be debugged, and the target simulation debugging tool is one of the plurality of simulation debugging tools; The debugging driver is configured to call the target simulation debugging tool based on the control instruction, acquire a debugging signal generated by the target simulation debugging tool, and output the debugging signal through the JTAG pin.

4. The main plate of claim 3, wherein, The control device is specifically configured to: when the CPU to be debugged is of a first type, send a control instruction for calling a hardware detection tool (HDT) to the debugging driver when the CPU to be debugged is of a second type, send a control instruction for calling an extended debug port (XDP) tool to the debugging driver.

5. The main plate according to any one of claims 1 to 4, characterized in that, The identification circuit comprises a complex programmable logic controller (CPLD); One end of the CPLD is coupled with the CPU to be debugged, and the other end of the CPLD is coupled with the BMC, wherein the CPLD is configured to receive the type reported by the CPU to be debugged and send the type of the CPU to be debugged to the BMC through a local bus.

6. The main plate according to any one of claims 1 to 4, characterized in that The mainboard further comprises a switch chip, wherein one end of the switch chip is coupled with the BMC, and the other end of the switch chip is coupled with the CPU to be debugged, and the voltages at the two ends of the switch chip are different; The switch chip is configured to convert a level of the first debugging signal into a level recognizable by the CPU to be debugged or convert a level of the second response signal into a level recognizable by the BMC.

7. The main plate of claim 6, wherein, The switch chip comprises a remote debugging channel. The BMC is further configured to send a control signal to the switch chip, the control signal being used to instruct the switch chip to transmit the debug signal between the BMC and the CPU to be debugged through the remote debugging channel.

8. The main plate of claim 1, wherein, The BMC establishes a network communication connection with a user-side device. The BMC is further configured to enable the remote debugging function in response to an operation instruction issued by a user through the user-side device.

9. The main plate of claim 6, wherein, The mainboard further comprises a slot carrying at least one debugging interface, the slot being coupled with the switch chip, and the slot supporting plugging of a debugging tool. The debugging tool is configured with a debugging interface, and when the debugging tool is plugged into the slot, the debugging tool is configured to debug the CPU to be debugged through the debugging interface.

10. A debugging method characterized by, The method is applied to a mainboard, and the mainboard comprises a BMC and an identification circuit. Receiving indication information sent by the identification circuit, the indication information being used to indicate a type of a CPU to be debugged; Based on the type of the CPU to be debugged indicated by the indication information, simulating a characteristic of a debugging tool corresponding to the type of the CPU to be debugged, and outputting a debug signal.

11. The method of claim 10, wherein, The simulating of the characteristic of the debugging tool corresponding to the type of the CPU to be debugged and the outputting of the debug signal comprise When the CPU to be debugged is of a first type, simulating a characteristic of an HDT tool, and outputting a debug signal; When the CPU to be debugged is of a second type, simulating a characteristic of an XDP tool, and outputting a debug signal.

12. A computing device, comprising: The computing device comprises a processor and a memory. The memory stores instructions executable by the processor. The processor is configured to execute the instructions, so that the computing device implements the method of claim 10 or 11.

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