A semiconductor test structure, a failure location method, and an electronic device

Abstract

The present invention provides a semiconductor test structure, a failure location method, and an electronic device. Specifically, in the test structure provided by the present invention, before forming a conventional metal layer for electrically connecting the first conductive plug and the second conductive plug and leading them out to the test pad, a new layer is formed to separately and blockwise electrically connect multiple polysilicon lines in the gate region and the first conductive plugs in the active region in the form of the active region array sub-units and lead them out to the upper metal layers (the first metal layer and the third metal layer). Thus, after finding the short-circuited polysilicon line through the third metal layer, only a limited number of first sub-metal lines of the polysilicon line in the corresponding active region need to be tested, and then it is possible to more accurately determine which two first conductive plugs corresponding to the active region array sub-units in the active region have a short-circuit problem.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly relates to a semiconductor test structure, a failure location method, and an electronic device. Background Art

[0002] In semiconductor technology, its manufacturing process can be divided into the front-end device process and the back-end metal interconnection process. Among them, the role of the back-end metal interconnection layer is to lead out the front-end devices for testing or operation. During semiconductor manufacturing, to evaluate the design structure and monitor the process stability on the production line, complex product structures are separately extracted or recombined into repetitive, large-area, and easily testable structures with this structure as a unit. By performing electrical tests on these test structures, a large number of corresponding electrical parameters are obtained, and these electrical parameters are analyzed to discover and solve problems in advance. Such a structure is called a test structure. Test structures are almost present in all levels of the manufacturing process, have various structures, and have characteristics such as being easy to test and easy to perform failure analysis.

[0003] Generally, when performing failure analysis on a test structure, its conventional failure analysis process includes: electrical confirmation, failure location determination, physical property analysis, and then finding the root cause of the failure. Among them, failure location determination is a very crucial step. Currently, the commonly used means for failure location determination in the semiconductor industry can be roughly divided into: Thermal Emission Microscope (Thermal), Electron Microscopy with Photon Emission (EMMI), Optically Beam Induced Resistance Change Microscope (OBIRCH), Electron Beam Induced Resistance Change Microscope (EBIRCH), etc.

[0004] However, as semiconductor process technology becomes more and more advanced, the test structures for testing are not only large in area and high in density but also more complex. The leakage caused by failure in many test structures becomes very small, and the defects causing failure also become very small. In the conventional failure analysis process, it usually uses on-line machines to perform on-line tests on common test structures, and this test process requires the use of test pads. If the common test structures are ground first, then manual tests need to be performed after grinding. Obviously, the former on-line test method cannot accurately locate the failure position on the test structure, and the latter manual test method after grinding increases the difficulty of location and the labor cost of engineers, etc. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor test structure, a failure location method and an electronic device, so as to propose a new test structure for detecting whether there is leakage current between the gate layer and the source / drain in the active region, and at the same time, propose a failure location method based on this test structure that can accurately locate the leakage failure position between the gate in the active region and the conductive plugs on both sides thereof for electrically connecting the source / drain, so as to ultimately solve the technical problems of low positioning accuracy, great positioning difficulty and high cost of the existing technology for the leakage failure position.

[0006] In a first aspect, to solve the above technical problems, the present invention provides a semiconductor test structure, which specifically may include the following structures:

[0007] An active region, including a plurality of active region units, and the plurality of active region units are arranged at intervals in sequence along a first direction;

[0008] A gate layer, including a plurality of polysilicon lines, and the plurality of polysilicon lines are arranged at intervals in sequence along a second direction perpendicular to the first direction on the active region and at least penetrate the active region along the first direction, so as to divide the active region into a plurality of interleaved active region array sub-units along the first direction and the second direction;

[0009] A plurality of first conductive plugs, located on a plurality of active region units between adjacent polysilicon lines, and two discrete first conductive plugs are respectively arranged on the active region units corresponding to each active region array sub-unit formed by dividing the active region by the plurality of polysilicon lines;

[0010] A first metal layer, including a plurality of first sub-metal lines, and each first sub-metal line respectively covers the surfaces of the two first conductive plugs corresponding to each active region array sub-unit;

[0011] A second metal layer, including a plurality of second sub-metal lines, and each second sub-metal line covers the surfaces of all the first conductive plugs arranged on an active region unit along the second direction, and extends to cover the remaining surfaces corresponding to the active region unit.

[0012] Furthermore, the semiconductor test structure provided by the present invention may further include a plurality of first vias, wherein the plurality of first vias are specifically located between the first sub-metal lines and the second sub-metal lines covering their surfaces, for respectively electrically connecting each first sub-metal line and the corresponding second sub-metal line, and two discrete first vias are included between each first sub-metal line and the second sub-metal line covering its surface.

[0013] Further, the semiconductor test structure provided by the present invention may further include: a gate region, the gate region is arranged in parallel with the active region in the direction along the first direction, and the multiple polysilicon lines arranged on the active region at intervals in sequence also extend along the first direction and cover the gate region.

[0014] Further, the semiconductor test structure further includes a plurality of second conductive plugs, and the plurality of second conductive plugs are located on the surfaces of the multiple polysilicon lines extending into the gate region.

[0015] Further, the semiconductor test structure provided by the present invention may further include: a third metal layer covering the surfaces of the second conductive plugs and a fourth metal layer covering the surface of the third metal layer, wherein the third metal layer and the first metal layer, and the fourth metal layer and the second metal layer are respectively in the same horizontal plane.

[0016] Further, the semiconductor test structure provided by the present invention may further include: test pads electrically connected to the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer respectively.

[0017] Further, the semiconductor test structure provided by the present invention may further include a plurality of second vias, and the plurality of second vias are located on partial surfaces of the third metal layer extending along the second direction for electrically connecting the third metal layer and the fourth metal layer.

[0018] In a second aspect, based on the same inventive concept as the semiconductor test structure provided by the present invention described above and based on this test structure, the present invention further provides a failure location method, which is characterized in that it may at least include the following steps:

[0019] Provide a planar sample having the semiconductor test structure as described above;

[0020] Perform a first grinding and layer removal process on the planar sample to remove the second metal layer and the fourth metal layer of the semiconductor test structure included in the planar sample;

[0021] Perform electron beam induced current technology or active voltage contrast technology on the semiconductor test structure after the first grinding and layer removal process to determine the first sub-metal line short-circuited with the polysilicon line;

[0022] Further perform a second grinding and layer removal process on the semiconductor test structure to remove the determined first sub-metal line and expose two first conductive plugs located below the first sub-metal line;

[0023] Perform a morphological analysis on a planar sample or a cross-sectional sample containing the two first conductive plugs exposed below the first sub-metal line to determine the exact location and failure mechanism of the leakage failure.

[0024] Further, before the first grinding and delamination treatment of the planar sample, the failure location method provided by the present invention may further include: performing an electrical failure analysis on the semiconductor test structure through the test pad.

[0025] In a third aspect, based on the same inventive concept as the failure location method described in the above content of the present invention, the present invention further provides an electronic device, which may specifically include a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus;

[0026] The memory is used to store a computer program;

[0027] The processor is used to implement the method steps of the failure location method described in any one of the first aspects when executing the program stored on the memory.

[0028] In a fourth aspect, based on the same inventive concept as the failure location method described in the above content of the present invention, the present invention further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method steps of the failure location method described in any one of the first aspects are implemented.

[0029] In a fifth aspect, based on the same inventive concept as the failure location method described in the above content of the present invention, the present invention further provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the method steps of the failure location method described in any one of the first aspects.

[0030] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0031] 1. The present invention provides a new test structure for testing whether there is a short circuit between the polysilicon gate in the active region and the conductive plugs (first conductive plugs) located on both sides thereof for electrically connecting the source and drain electrodes, which causes a leakage failure problem. Specifically, in the semiconductor test structure provided by the present invention, in the active region including multiple polysilicon lines serving as the polysilicon gate and multiple first conductive plugs located on the active region, the active region is first divided by using the multiple polysilicon lines, so as to divide the active region into an active region array sub-unit arranged in a staggered manner. Then, two of the first conductive plugs are respectively formed on the active region corresponding to each of the active region array sub-units. After that, a first sub-metal line is formed on each two of the first conductive plugs (there is a one-to-one correspondence between the active region array sub-unit and the first sub-metal line). Finally, a second sub-metal line is respectively arranged along the direction of each active region unit.

[0032] Obviously, in the semiconductor test structure provided by the present invention, before forming the conventional metal layers (second metal layer and fourth metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading them out to the test pads, a new metal layer (first metal layer and third metal layer) is formed to respectively block and electrically connect the multiple polysilicon lines in the gate region and the first conductive plugs in the active region in the form of the active region array sub-units and lead them out to the upper layer. Thus, after finding the polysilicon line with a short circuit through the third metal layer, only a limited number of first sub-metal lines of the polysilicon line in the corresponding active region need to be tested, so as to more accurately determine which two first conductive plugs corresponding to the active region array sub-units in the active region have a short circuit problem, that is, the number of tests and the test range of the leakage failure position are reduced, the positioning accuracy of the leakage failure position is improved, and the positioning difficulty and cost are reduced.

[0033] 2. In a failure location method proposed by the present invention, by using the test structure provided by the present invention, without exposing the first conductive plug (i.e., exposing the first metal layer), in combination with the active voltage contrast (AVC) technology or the electron beam absorption current (EBAC) technology, the range of the leakage failure position can be greatly reduced. And by further grinding only the reduced range to expose the first conductive plug located thereunder, that is, the purpose of quickly and accurately determining the leakage failure position can be achieved only by the operator performing artificial test analysis on the region where the leakage failure position range is reduced. Description of the Drawings

[0034] Figure 1It is a layout schematic diagram of a test structure in the prior art for determining whether there is a leakage defect caused by the short circuit between a polysilicon gate and metal plugs in the active regions on both sides of it;

[0035] Figure 2 It is a hot spot map of the hot spots located by OBIRCH;

[0036] Figure 3 It is a SEM plan view of the abnormal first metal plug located by VC;

[0037] Figure 4 It is a SEM plan view of the verification result of the electrical test on the abnormal first metal plug of VC again;

[0038] Figure 5a It is a layout schematic diagram of a test structure provided in an embodiment of the present invention, in which the semiconductor test structure only includes a first conductive plug and a second conductive plug;

[0039] Figure 5b In an embodiment of the present invention, Figure 5a It is a layout schematic diagram of a test structure in which a special structure first metal layer designed by the present invention is formed on the basis of the semiconductor test structure;

[0040] Figure 5c In an embodiment of the present invention, Figure 5b It is a layout schematic diagram of a test structure in which a first via hole and a second via hole are formed on the above-mentioned structure;

[0041] Figure 5d In an embodiment of the present invention, Figure 5c It is a layout schematic diagram of a test structure in which a second metal layer (i.e., the complete structure of the semiconductor test structure designed by the present invention) is formed on the above-mentioned structure;

[0042] Figure 6 It is a flow schematic diagram of a failure location method provided in an embodiment of the present invention. Detailed implementation manners

[0043] As described in the background art, currently, with the increasingly advanced semiconductor process technology, test structures for testing are not only large in area, high in density but also more complex. Leakage current caused by failure in many test structures becomes very small, and defects causing failure also become very small. In the conventional failure analysis process, it usually uses on-line machines to perform on-line tests on common test structures, and this test process requires the use of test pads. If the common test structure is first ground, manual tests need to be carried out after grinding. Obviously, the former on-line test method cannot accurately locate the failure position on the test structure, while the latter manual test method after grinding increases the positioning difficulty and the labor cost of engineers and others.

[0044] Figure 1 It is a layout schematic diagram of a test structure in the prior art for determining whether there is a leakage defect caused by the short circuit between a polysilicon gate and metal plugs in the active regions on both sides of it. Among them, 100 is a polysilicon gate bar, 120 is a first metal plug located in the active region and electrically connected to the active region, 130 is a second metal plug located in the non-active region for electrically connecting the polysilicon gate bar 100, and 140a and 140b are metal layers for respectively electrically connecting the first metal plug 120 and the second metal plug 130. And the metal layers 140a and 140b are connected to external pads (not shown).

[0045] Currently, for Figure 1 the layout of the test structure shown, the second metal plug 130 of the polysilicon gate bar 100 is led to the test pad through the metal layer 140b, and the two first metal plugs 120 located in the active region are also respectively led to different test pads through the metal layer 140a to monitor the leakage problem between the polysilicon gate bar 100 and the first metal plug 120.

[0046] Obviously, in the prior art, using Figure 1The test structure determined by the layout shown has the metal layers 140a and 140b on the same horizontal plane leading to different test pads, which are formed in patches in the active region along the second direction (which can also be understood as the X direction) defined by the present invention. That is, for all regions included in each active region unit along the second direction, only one metal layer 140a is formed, rather than, as in the semiconductor test structure provided by the present invention, before the metal layers (the second metal layer and the fourth metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading them to the test pads, a new metal layer (the first metal layer and the third metal layer) is formed to electrically connect and lead to the upper layer in a unit-by-unit manner the multiple polysilicon lines in the gate region and the first conductive plugs in the active region respectively. This is the main difference in the design of the test structure proposed by the present invention and the prior art.

[0047] Furthermore, in the prior art, for the Figure 1 test structure corresponding to the layout to which it belongs, the conventional analysis process is to first capture points with OBIRCH / EBIRCH, but only a rough positioning can be achieved through the hot spots. For example, Figure 1 the size of the test structure corresponding to the test structure layout shown is approximately 60um * 120um, and the number of polysilicon gate bars 100 and metal plugs included in the corresponding test structure is in the tens of thousands (approximately five hundred 100s and five hundred thousand 120s). Such hot spots are simply not sufficient to find the leakage failure location. The measurement sample needs to be further processed to the CT layer (metal plug layer), and the probe of the NanoProber device is stabbed on the first metal plug of five hundred polysilicon gate bars near the hot spot, and an appropriate voltage is applied to the probe. The secondary electron image is viewed using the SEM mode. According to the principle of AVC, the first metal plug with polysilicon gate bar leakage will show a different voltage contrast from other first metal plugs in the SEM image, and the first metal plug with polysilicon gate bar leakage is marked out, so as to accurately locate the defect location. However, this method has a large workload and a low success rate. Firstly, the hot spot position is inaccurate and multiple tests are required. Secondly, the contrast difference brought by VC is not obvious, and rich experience of engineers is needed.

[0048] Taking an actual case as an example, Figure 2 is the hot spot map of the hot spot located by OBIRCH. In the test structure with a size of 60um * 120um, after roughly measuring the distance between the hot spot and the edge of the structure, the measurement sample is ground to the metal plug layer, and one needle of the NanoProber is stabbed on the second metal plug of the polysilicon gate bar. Using the principle of AVC, with the hot spot as the center and combined with SEM observation, repeated attempts are made until the first metal plug with abnormal VC is found. Figure 3It is a SEM plan view in which the VC locates the abnormal first metal plug. It can be seen that the VC difference is very weak, and this step places very high requirements on engineers. Figure 4 It is a SEM plan view of the re-electrical test of the first metal plug for the VC anomaly to verify the result, which shows that the first metal plug with the VC anomaly has indeed short-circuited with the polysilicon gate bar, that is, the exact position where the leakage failure occurred has been located. Next, TEM analysis is carried out. Obviously, the failure analysis method adopted by the prior art has technical problems such as great difficulty, long time consumption, high cost, and difficult to grasp the analysis accuracy.

[0049] For this reason, the present invention provides a semiconductor test structure, a failure location method, and an electronic device, so as to propose a new test structure for detecting whether there is a leakage current between the gate layer and the source / drain in the active region, and at the same time propose a failure location method based on this test structure that can accurately locate the leakage failure position between the gate in the active region and the conductive plugs on both sides thereof for electrically connecting the source / drain, so as to ultimately solve the technical problems of low positioning accuracy, great positioning difficulty, and high cost of the prior art for the leakage failure position.

[0050] The following further details the semiconductor test structure, failure location method, and electronic device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, so the present invention is not limited by the specific embodiments disclosed below.

[0051] As shown in the present application and the claims, unless the context clearly indicates otherwise, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. When detailing the embodiments of the present invention, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0052] Refer to Figures 5a to 5d , Figures 5a to 5d is a schematic structural diagram of a semiconductor test structure provided in an embodiment of the present invention, where Figure 5aSchematic layout diagram of the test structure of the semiconductor test structure provided in an embodiment of the present invention, which only includes a first conductive plug and a second conductive plug. Figure 5b In an embodiment of the present invention, Figure 5a Schematic layout diagram of the test structure in which a first metal layer with a special structure designed by the present invention is formed on the basis of the semiconductor test structure; Figure 5c In an embodiment of the present invention, Figure 5b Schematic layout diagram of the test structure in which a first via hole and a second via hole are formed on the above-mentioned structure; Figure 5d In an embodiment of the present invention, Figure 5c Schematic layout diagram of the test structure in which a second metal layer (i.e., the complete structure of the semiconductor test structure designed by the present invention) is formed on the above-mentioned structure.

[0053] It should be noted that in the embodiment of the present invention, the first direction can be understood as the Y direction, the second direction can be understood as the second direction, and the first direction and the second direction are perpendicular to each other.

[0054] Specifically, as Figures 5a to 5d shown, the semiconductor test structure provided by the present invention may specifically include: an active region 1, including a plurality of active region units 11, and the plurality of active region units 11 are arranged at intervals in sequence along the first direction;

[0055] A gate layer 12, including a plurality of polysilicon lines P1 to Pn, and the plurality of polysilicon lines P1 to Pn are arranged at intervals in sequence along a second direction perpendicular to the first direction on the active region 1 and at least penetrate the active region 1 along the first direction, so as to divide the active region 1 into a plurality of interleaved active region array sub-units a along the first direction and the second direction;

[0056] A plurality of first conductive plugs CT1 are located on a plurality of active region units 11 between adjacent polysilicon lines P1 to Pn, and two discrete first conductive plugs CT1 are respectively arranged on the active region units 11 corresponding to each active region array sub-unit a divided by the plurality of polysilicon lines P1 to Pn in the active region 1;

[0057] A first metal layer M1, including a plurality of first sub-metal lines M1.1, and each of the first sub-metal lines M1.1 respectively covers the surfaces of the two first conductive plugs CT1 corresponding to each active region array sub-unit a;

[0058] The second metal layer M2 includes a plurality of second sub-metal lines M2.2. Each of the second sub-metal lines M2.2 covers the surfaces of all the first conductive plugs CT1 provided on one of the active region units 11 along the second direction, and extends to cover the remaining surfaces corresponding to the active region unit 11.

[0059] Further, specifically referring to Figures 5a to 5d any of the structural schematic diagrams in, the semiconductor test structure provided by the present invention further includes:

[0060] The gate region 2, the gate region 2 is arranged in parallel with the active region 1 in the direction along the first direction, and the plurality of polysilicon lines P1 to Pn arranged on the active region 1 at intervals in sequence also extend along the first direction to cover the gate region 2.

[0061] Further, specifically referring to Figure 5a , the semiconductor test structure provided by the present invention may further include a plurality of second conductive plugs CT2, and the plurality of second conductive plugs CT2 are located on the surfaces of the plurality of polysilicon lines extending into the gate region 2.

[0062] In this embodiment, the first conductive plug CT1 is mainly used to electrically lead out the source and drain electrodes formed in the active region 1 on each active region array sub-unit a, so as to be used to determine whether there is leakage between the polysilicon line and the source and drain electrodes in the subsequent failure location analysis method, while the second conductive plug CT2 is used to electrically lead out each polysilicon line to realize electrical testing through CTI and CT2.

[0063] Further, specifically referring to Figure 5c , the semiconductor test structure provided by the present invention may further include a plurality of first vias Via1. Specifically, the plurality of first vias Via1 are located between the first sub-metal line M1.1 and the second sub-metal line M2.2 covering its surface, so as to be used to electrically connect each first sub-metal line M1.1 and the corresponding second sub-metal line M2.2 respectively, and two discrete first vias Via1 are included between each first sub-metal line M1.1 and the second sub-metal line M2.2 covering its surface.

[0064] In this embodiment, since two first conductive plugs CT1 are formed in each active region array sub-unit a, and the first sub-metal line M1.1 is conductive, therefore, in order to electrically lead out the two first conductive plugs CT1 outward respectively, two first vias Via1 are correspondingly formed on the surface of each first sub-metal line M1.1 corresponding to the two first conductive plugs CT1, and then the second metal layer M2 is formed.

[0065] Further, specifically referring to Figure 5c and Figure 5d , the gate region 2 of the semiconductor test structure according to the present invention may further include:

[0066] A third metal layer M3 covering the surface of the second conductive plug CT2 and a fourth metal layer M4 covering the surface of the third metal layer M3; and a plurality of second vias Via2 located on a partial surface of the third metal layer M3 extending along the second direction (X direction) for electrically connecting the third metal layer M3 and the fourth metal layer M4.

[0067] Wherein, the third metal layer M3 and the first metal layer M1, and the fourth metal layer M4 and the second metal layer M2 are respectively in the same horizontal plane.

[0068] In this embodiment, after forming the first conductive plug CT1 in the active region 1 and the second conductive plug CT2 in the gate region 2, a metal layer can be formed in both the active region 1 and the gate region 2 by a deposition process, that is, the first metal layer M1 in the active region 1 and the third metal layer M3 in the gate region 2. Therefore, the third metal layer M3 and the first metal layer M1 are in the same horizontal plane. After that, the first via Via1 and the second via Via2 are formed. Finally, the second metal layer M2 and the fourth metal layer M4 are formed. Therefore, similarly, the fourth metal layer M4 and the second metal layer M2 are also in the same horizontal plane.

[0069] In addition, the semiconductor test structure provided by the present invention may further include test pads (not shown) electrically connected to the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 respectively.

[0070] Obviously, by using the semiconductor test structure provided by the present invention, when performing electrical tests on metal layers above M2, each item of on-line electrical tests can be directly carried out by using the test pads through the first metal layer M1, the second metal layer M2, and other metal layers located thereon; and when determining whether there is a leakage failure problem caused by a short circuit between the polysilicon lines and the first conductive plugs in the active region, since the semiconductor test structure provided by the present invention forms a new layer that electrically connects and leads to the upper metal layer (the first metal layer and the third metal layer) in a unitized manner for the multiple polysilicon lines in the gate region and the first conductive plugs in the active region respectively before forming the conventional metal layers (the second metal layer and the fourth metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading them to the test pads, after the polysilicon line where the short circuit occurs can be found through the third metal layer, only a limited number of first sub-metal lines of the polysilicon line in the corresponding active region need to be tested, so as to more accurately determine which two first conductive plugs corresponding to the active region array sub-units in the active region have a short circuit problem, that is, the number of tests and the test range of the leakage failure position are reduced, the positioning accuracy of the leakage failure position is improved, and the positioning difficulty and cost are reduced.

[0071] In addition, based on the semiconductor test structure corresponding to the layout shown in Figures 5a to 5d , the present invention also provides a failure location method. Refer to Figure 6 , Figure 6 which is a flowchart of a failure location method provided in an embodiment of the present invention.

[0072] As shown in Figure 6 , the failure location method provided by the present invention may at least include the following steps:

[0073] Step S601: Provide a planar sample having the semiconductor test structure as described above;

[0074] Step S602: Perform a first grinding and layer removal process on the planar sample to remove the second metal layer and the fourth metal layer of the semiconductor test structure included in the planar sample;

[0075] Step S603: Perform an electron beam induced current technique or an active voltage contrast technique on the semiconductor test structure after the first grinding and layer removal process to determine the first sub-metal line short-circuited with the polysilicon line;

[0076] Step S604: Further perform a second grinding and layer removal process on the semiconductor test structure to remove the determined first sub-metal line and expose the two first conductive plugs located below the first sub-metal line;

[0077] Step S605: Perform morphological analysis on a planar sample or a cross-sectional sample containing the two first conductive plugs exposed under the first sub-metal line to determine the exact location and failure mechanism of the leakage failure.

[0078] In this embodiment, first, on a currently commonly used semiconductor material, such as a silicon wafer, form the semiconductor test structure as Figure 5d described. Then, form a planar sample containing the semiconductor test structure. After that, use the grinding and delayer process to first remove the top second metal layer and fourth metal layer to expose the first via hole and the second via hole, that is, obtain the test structure corresponding to the layout shown in Figure 5c . Then, use the electron beam induced current technique or the active voltage contrast technique to perform electrical analysis on the obtained test structure. The problem of which first conductive plug corresponding to the first sub-metal line has a problem can be determined through the bright spot area in the obtained image. After that, further perform a second grinding and delayer process on the bright spot area to expose the first conductive plug covered under the bright spot area. Furthermore, through TEM planar sample analysis and then TEM cross-sectional sample analysis, the exact location and failure mechanism of the leakage failure can be accurately determined.

[0079] In summary, 1. The present invention provides a new test structure for testing whether there is a short circuit between a polysilicon gate in an active region and a conductive plug (first conductive plug) for electrically connecting source and drain electrodes on both sides thereof, resulting in a leakage failure problem. Specifically, in the semiconductor test structure provided by the present invention, in the active region containing multiple polysilicon lines serving as polysilicon gates and multiple first conductive plugs on the active region, first use the multiple polysilicon lines to divide the active region, so as to divide the active region into an array of active region sub-units arranged in a staggered manner. Then, form two of the first conductive plugs on the active region corresponding to each of the active region array sub-units. After that, form a first sub-metal line on each of the two first conductive plugs (there is a one-to-one correspondence between the active region array sub-units and the first sub-metal lines). Finally, along the direction of each active region unit, respectively set a second sub-metal line.

[0080] Obviously, in the semiconductor test structure provided by the present invention, before forming the conventional metal layers (the second metal layer and the fourth metal layer) for electrically connecting the first conductive plug and the second conductive plug and leading them out to the test pads, a new layer is formed to blockwise electrically connect and lead out to the upper metal layers (the first metal layer and the third metal layer) the multiple polysilicon lines in the gate region and the first conductive plugs in the active region respectively in the form of the active region array sub-units. Thus, after the short-circuited polysilicon line can be found through the third metal layer, only a limited number of first sub-metal lines of the polysilicon line in the corresponding active region need to be tested, and then it can be more accurately determined which two first conductive plugs corresponding to the active region array sub-units in the active region have a short-circuit problem, that is, the number of tests and the test range of the leakage failure position are reduced, the positioning accuracy of the leakage failure position is improved, and the positioning difficulty and cost are reduced.

[0081] 2. In a failure positioning method proposed by the present invention, by using the test structure provided by the present invention, without exposing the first conductive plug (i.e., exposing the first metal layer), in combination with the active voltage contrast (AVC) technology or the electron beam induced current (EBIC) technology, the range of the leakage failure position can be greatly reduced, and further only the reduced range is polished to expose the first conductive plug located thereunder. That is, it is only necessary for the operator to perform manual test analysis on the area where the range of the leakage failure position is reduced, and then the purpose of quickly and accurately determining the leakage failure position can be achieved.

[0082] In addition, an embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus.

[0083] The memory is used to store a computer program.

[0084] When the processor is used to execute the program stored in the memory, the method steps described in the above failure positioning method are implemented.

[0085] For the specific implementation of each step of the method and the related explanatory content, reference can be made to the method embodiment shown above. Figure 6 Details are not described herein again.

[0086] In addition, other implementation manners of the application setting method implemented by the processor executing the program stored in the memory are the same as those mentioned in the method embodiment part above, and are not described herein again.

[0087] In another embodiment provided by the present invention, the embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned failure location method are implemented.

[0088] In another embodiment provided by the present invention, the embodiment of the present invention further provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the above-mentioned failure location method.

[0089] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more integrated available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example,), or a semiconductor medium (for example, solid state disk (SSD)).

[0090] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0091] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, user terminal, computer-readable storage medium, and computer program product, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0092] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor test structure, characterized in that, Comprising: An active region, including a plurality of active region units, which are arranged at intervals in sequence along a first direction; A gate layer, including a plurality of polysilicon lines, which are arranged at intervals in sequence along a second direction perpendicular to the first direction on the active region and penetrate through the active region at least along the first direction, so as to divide the active region into a plurality of interleaved active region array sub-units along the first direction and the second direction; A plurality of first conductive plugs, located on a plurality of active region units between adjacent polysilicon lines, and two discrete first conductive plugs are respectively provided on the active region units corresponding to each active region array sub-unit formed by dividing the active region by the plurality of polysilicon lines; A first metal layer, including a plurality of first sub-metal lines, and each first sub-metal line respectively covers the surfaces of the two first conductive plugs corresponding to each active region array sub-unit; A second metal layer, including a plurality of second sub-metal lines, each second sub-metal line covers the surfaces of all the first conductive plugs provided on one active region unit along the second direction and extends to cover the remaining surfaces corresponding to the active region unit; A gate region, the gate region is arranged in parallel with the active region in the direction along the first direction, and the plurality of polysilicon lines arranged at intervals in sequence on the active region also extend along the first direction to cover the gate region; and, A plurality of second conductive plugs, the plurality of second conductive plugs are located on the surfaces of the plurality of polysilicon lines extending into the gate region.

2. The semiconductor test structure according to claim 1, characterized in that, The semiconductor test structure further includes a plurality of first vias, the plurality of first vias are located between the first sub-metal lines and the second sub-metal lines covering their surfaces, for respectively electrically connecting each first sub-metal line and the second sub-metal line corresponding to it, and two discrete first vias are included between each first sub-metal line and the second sub-metal line covering its surface.

3. The semiconductor test structure according to claim 1, characterized in that, The semiconductor test structure further includes: a third metal layer covering the surface of the second conductive plug and a fourth metal layer covering the surface of the third metal layer, wherein the third metal layer and the first metal layer, and the fourth metal layer and the second metal layer are respectively in the same horizontal plane.

4. The semiconductor test structure according to claim 3, wherein The semiconductor test structure further includes: test pads electrically connected to the first metal layer, the second metal layer, the third metal layer and the fourth metal layer respectively.

5. The semiconductor test structure according to claim 3, characterized in that, The semiconductor test structure further includes a plurality of second vias, the plurality of second vias are located on a part of the surface of the third metal layer extending along the second direction, for electrically connecting the third metal layer and the fourth metal layer.

6. A failure location method, characterized in that, Including the following steps: Providing a planar sample having the semiconductor test structure according to any one of claims 1-5; Performing a first grinding and delamination process on the planar sample to remove the second metal layer and the fourth metal layer of the semiconductor test structure included in the planar sample; Perform electron beam induced current technique or active voltage contrast technique on the semiconductor test structure after the first grinding and delayer treatment to determine the first sub-metal wire shorted to the polysilicon wire; Further perform a second grinding and delayer treatment on the semiconductor test structure to remove the determined first sub-metal wire and expose two first conductive plugs located below the first sub-metal wire; Perform morphological analysis on a planar sample or a cross-sectional sample containing the two first conductive plugs exposed below the first sub-metal wire to determine the exact location and failure mechanism of the leakage failure.

7. The failure location method according to claim 6, characterized in that, Before the first grinding and delayer treatment on the planar sample, the failure location method further includes: performing electrical failure analysis on the semiconductor test structure through the test pad.

8. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used to store computer programs; The processor is used to implement the method steps of the failure location method described in any one of claims 6 to 7 when executing the program stored on the memory.

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