An oscillation circuit with voltage and temperature compensation

Abstract

The present invention discloses an oscillation circuit with voltage and temperature compensation, which includes a trigger circuit U1. The trigger circuit U1 includes PMOS transistors and NMOS transistors. The PMOS transistors include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. The NMOS transistors include a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5. The trigger circuit U1 in the present invention includes a circuit structure with temperature and voltage compensation functions. This circuit structure can significantly reduce the frequency deviation of the oscillation circuit output at different operating temperatures and operating voltages. The present invention can meet application scenarios with high requirements for frequency accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to an oscillation circuit with voltage and temperature compensation. Background Art

[0002] A Schmitt trigger circuit (Schmitt trigger) can be used as a waveform shaping circuit, which can shape an analog signal waveform into a square wave waveform that can be processed by a digital circuit. Moreover, due to the hysteresis characteristic of the Schmitt trigger, it can be used for anti-interference. Its applications include anti-interference in an open-loop configuration and realizing a multivibrator in a closed-loop positive feedback / negative feedback configuration.

[0003] In the prior art, a Schmitt trigger circuit, such as Figure 1 shown, has a large frequency deviation in the output of the oscillation circuit under different operating temperatures and different operating voltages, and cannot meet the application scenarios with high requirements for frequency accuracy. How to develop a Schmitt trigger circuit for an oscillation circuit with a small frequency deviation in the output under different operating temperatures and different operating voltages is a technical problem generally concerned and solved by those skilled in the art. Summary of the Invention

[0004] Aiming at the above deficiencies of the prior art, the present invention discloses an oscillation circuit with voltage and temperature compensation. This technical solution includes a circuit structure with temperature and voltage compensation functions, which can greatly reduce the frequency deviation in the output under different operating temperatures and operating voltages when used in an oscillation circuit, and output a frequency with a small output deviation and high accuracy.

[0005] The specific technical solution of the present invention is as follows:

[0006] An oscillation circuit with voltage and temperature compensation includes a trigger circuit U1.

[0007] The trigger circuit U1 includes a trigger circuit U1, which includes PMOS transistors and NMOS transistors. The PMOS transistors include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. The NMOS transistors include a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.

[0008] In this technical solution, the source of the first PMOS transistor MP1 is connected to the VDD power supply, the drain of the source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded.

[0009] The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are connected together to be the input terminal of the trigger circuit U1.

[0010] The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the connection terminal of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2. The source of the third PMOS transistor MP3 is connected to the connection terminal of the drain of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2. The drain of the third NMOS transistor MN3 is connected to the connection terminal of the source of the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1.

[0011] The drain of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is grounded. The gate of the fourth NMOS transistor MN4 is connected to the VDD power supply.

[0012] The drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4. The source of the fourth PMOS transistor MP4 is connected to the VDD power supply. The gate of the fourth PMOS transistor MP4 is grounded.

[0013] The gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are connected together. The drain of the fifth PMOS transistor MP5 is connected to the source of the third PMOS transistor MP3. The source of the fifth PMOS transistor MP5 is connected to the VDD power supply. The drain of the fifth NMOS transistor MN5 is connected to the source of the third NMOS transistor MN3. The source of the fifth NMOS transistor MN5 is grounded.

[0014] The trigger circuit U1 further includes a first inverter I1. The input terminal of the first inverter I1 is connected to the common terminal of the third PMOS transistor MP3 and the third NMOS transistor MN3. The output terminal of the first inverter I1 is connected to the common terminal of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 and the output terminal of the trigger circuit U1.

[0015] In this technical solution, in addition to the trigger circuit U1, the oscillation circuit further includes a NAND gate U2, a second inverter I2, a first capacitor C1, and a first resistor R1.

[0016] One end of the first capacitor C1 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the trigger circuit U1.

[0017] The input terminal of the NAND gate U2 is connected to the output terminal of the trigger circuit U1, the output terminal is connected to the input terminal of the second inverter I2, and the output terminal of the second inverter I2 is the output terminal of the oscillation circuit;

[0018] One end of the first resistor R1 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the NAND gate U2.

[0019] In a more optimal technical solution of the present invention, in addition to the trigger circuit U1, the oscillation circuit further includes a third inverter I3, a fourth inverter I4, an AND gate U3, a fifth inverter I5, a sixth inverter I6, a second capacitor C2, and a second resistor R2.

[0020] One end of the second capacitor C2 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the trigger circuit U1.

[0021] The input terminal of the third inverter I3 is connected to the output terminal of the trigger circuit U1, the output terminal is connected to the input terminal of the fourth inverter I4, the output terminal of the fourth inverter I4 is connected to the input terminal of the AND gate U3, and the output terminal of the AND gate U3 is connected to the input terminal of the fifth inverter I5.

[0022] One end of the second resistor R2 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the fifth inverter I5.

[0023] The input terminal of the sixth inverter I6 is connected to the common terminal of the third inverter I3 and the fourth inverter I4, and the output terminal of the sixth inverter I6 is the output terminal of the oscillation circuit.

[0024] An oscillation circuit with voltage and temperature compensation according to the present invention. The trigger circuit U1 in this technical solution includes a circuit structure with temperature and voltage compensation functions. This circuit structure can significantly reduce the frequency deviation of the oscillation circuit output under different operating temperatures and voltages. The present invention can meet application scenarios with high requirements for frequency accuracy. Description of the Drawings

[0025] Figure 1 Schematic diagram of the circuit structure of a Schmitt trigger circuit in the prior art.

[0026] Figure 2 Schematic diagram of the circuit structure of the trigger circuit U1 in an oscillation circuit with voltage and temperature compensation according to the present invention.

[0027] Figure 3 Schematic diagram of the structure of an embodiment of an oscillation circuit with voltage and temperature compensation according to the present invention.

[0028] Figure 4 Schematic diagram of the structure of another embodiment of an oscillation circuit with voltage and temperature compensation according to the present invention.

[0029] Figure 5 An oscillation circuit in the prior art that includes Figure 1 Frequency simulation data table of the oscillation circuit with the Schmitt trigger circuit described in

[0030] Figure 6 An oscillation circuit with voltage and temperature compensation according to the present invention and Figure 5 Frequency simulation data table at different operating voltages under the same operating conditions.

[0031] Figure 7 An oscillation circuit in the prior art that includes Figure 1 Frequency simulation data table of the oscillation circuit with the Schmitt trigger circuit described in

[0032] Figure 8 An oscillation circuit with voltage and temperature compensation according to the present invention and Figure 7 Frequency simulation data table at different operating temperatures under the same operating conditions. Detailed implementation manners

[0033] The present invention will be further described in detail below with reference to the accompanying drawings.

[0034] To better illustrate this embodiment, some components in the drawings are omitted, enlarged or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, the omission of some well-known structures and their descriptions in the drawings can be understood. The same or similar reference numerals correspond to the same or similar components.

[0035] The Schmitt trigger circuit (Schmitt trigger) is mostly used in oscillation circuits, and the oscillation circuit provides a stable frequency output for the system. There are various Schmitt trigger circuits in the prior art. Figure 1 is a common Schmitt trigger circuit in the prior art, and the prior art in this embodiment takes Figure 1 as an example.

[0036] The Schmitt trigger circuit in the prior art is used in an oscillation circuit, and the frequency deviation of the output is relatively large at different operating temperatures and different operating voltages.

[0037] Then, how to develop a Schmitt trigger circuit for an oscillator circuit so that the frequency deviation of the output under different operating temperatures and voltages is not large is a technical problem that those skilled in the art generally pay attention to and solve.

[0038] The present invention discloses an oscillator circuit structure with voltage and temperature compensation. The circuit structure can greatly reduce the frequency deviation of the output under different operating temperatures and voltages, enabling the present invention to stably output a frequency with small deviation and high precision.

[0039] The specific embodiments of the present invention are as follows:

[0040] Embodiment 1

[0041] In this embodiment, an oscillator circuit with voltage and temperature compensation includes a trigger circuit U1, as Figure 2 shown. The trigger circuit U1 includes PMOS transistors and NMOS transistors. The PMOS transistors include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. The NMOS transistors include a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.

[0042] The fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 in this embodiment, as well as their connection structure in the trigger circuit U1, have the function of temperature and voltage compensation, which is the key technology to implement the technical solution of the present invention.

[0043] Specifically, in this embodiment, the source of the first PMOS transistor MP1 is connected to the VDD power supply. The drain of the source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is grounded.

[0044] The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are connected together as the input terminal of the trigger circuit U1.

[0045] In this embodiment, the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the connection terminal of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2. The source of the third PMOS transistor MP3 is connected to the connection terminal of the drain of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2. The drain of the third NMOS transistor MN3 is connected to the connection terminal of the source of the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1.

[0046] The drain of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is grounded, and the gate of the fourth NMOS transistor MN4 is connected to the VDD power supply.

[0047] The drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4. The source of the fourth PMOS transistor MP4 is connected to the VDD power supply, and the gate of the fourth PMOS transistor MP4 is grounded.

[0048] The gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are connected together. The drain of the fifth PMOS transistor MP5 is connected to the source of the third PMOS transistor MP3. The source of the fifth PMOS transistor MP5 is connected to the VDD power supply. The drain of the fifth NMOS transistor MN5 is connected to the source of the third NMOS transistor MN3, and the source of the fifth NMOS transistor MN5 is grounded.

[0049] In a more preferred technical solution of this embodiment, the trigger circuit U1 further includes a first inverter I1. The input terminal of the first inverter I1 is connected to the common terminal of the third PMOS transistor MP3 and the third NMOS transistor MN3. The output terminal of the first inverter I1 is connected to the common terminal of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 and the output terminal of the trigger circuit U1.

[0050] As shown in this embodiment Figure 3 In addition to the trigger circuit U1, the oscillation circuit further includes a NAND gate U2, a second inverter I2, a first capacitor C1, and a first resistor R1.

[0051] One end of the first capacitor C1 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the trigger circuit U1.

[0052] The input terminal of the NAND gate U2 is connected to the output terminal of the trigger circuit U1, and the output terminal is connected to the input terminal of the second inverter I2. The output terminal of the second inverter I2 is the output terminal of the oscillation circuit;

[0053] In this embodiment, one end of the first resistor R1 is connected to the input end of the trigger circuit U1, and the other end is connected to the output end of the NAND gate U2.

[0054] It should be noted that the NAND gate U2 further includes an enable terminal and is connected to the enable signal emitting terminal, and the operating state of the NAND gate U2 is controlled by the enable signal.

[0055] Embodiment 2

[0056] As shown in this embodiment Figure 4 The oscillation circuit, in addition to including the trigger circuit U1, further includes a third inverter I3, a fourth inverter I4, an AND gate U3, a fifth inverter I5, a sixth inverter I6, a second capacitor C2 and a second resistor R2.

[0057] One end of the second capacitor C2 is connected to the input end of the trigger circuit U1, and the other end is connected to the output end of the trigger circuit U1.

[0058] The input end of the third inverter I3 is connected to the output end of the trigger circuit U1, the output end is connected to the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected to the input end of the AND gate U3, and the output end of the AND gate U3 is connected to the input end of the fifth inverter I5.

[0059] It should be noted that the AND gate U3 further includes an enable terminal and is connected to the enable signal emitting terminal, and the operating state of the AND gate U3 is controlled by the enable signal.

[0060] One end of the second resistor R2 is connected to the input end of the trigger circuit U1, and the other end is connected to the output end of the fifth inverter I5.

[0061] In this embodiment, the input end of the sixth inverter I6 is connected to the common terminal of the third inverter I3 and the fourth inverter I4, and the output end of the sixth inverter I6 is the output end of the oscillation circuit.

[0062] It should be particularly noted that the present invention has temperature and voltage compensation functions, which can greatly reduce the frequency deviation of the output under different operating temperatures and operating voltages, as shown in Tables 5 - 8.

[0063] Tables 5 - 8 are simulation data tables of the Schmitt trigger circuit in Figure 1 and the trigger circuit U1 described in Embodiment 1, based on the oscillation circuit structure described in Embodiment 2, under different operating voltages and operating temperatures. Specifically:

[0064] Table 5 is Figure 1Frequency simulation data at different operating voltages in the case of the Schmitt trigger circuit in []. Table 6 shows the frequency simulation data at different operating voltages in the case of trigger circuit U1 described in Embodiment 1 (with the same other operating conditions).

[0065] The headers of Table 5 and Table 6 include VDD (operating voltage), Freq (frequency), and Offset (frequency deviation). By comparing Table 5 and Table 6, it can be seen that at the same operating voltage, the reduction in the corresponding frequency deviation in Table 6 is huge. For example, when the operating voltage is 1.8V, the corresponding frequency deviation in Table 5 is -16.8%, and the corresponding frequency deviation in Table 6 is -2.9%. Using the trigger circuit U1 described in the present invention in the oscillator circuit can significantly reduce the frequency deviation at different operating voltages.

[0066] Table 7 is Figure 1 Frequency simulation data at different operating temperatures in the case of the Schmitt trigger circuit in []. Table 8 shows the frequency simulation data at different operating temperatures in the case of trigger circuit U1 described in Embodiment 1 (with the same other operating conditions).

[0067] The headers of Table 7 and Table 8 include Temp (operating temperature), Freq (frequency), and Offset (frequency deviation). By comparing Table 7 and Table 8, it can be seen that at the same operating temperature, the reduction in the corresponding frequency deviation in Table 8 is huge. For example, when the operating temperature is -20°C, the corresponding frequency deviation in Table 7 is -1.3%, and the corresponding frequency deviation in Table 8 is -0.3%. Using the trigger circuit U1 described in the present invention in the oscillator circuit can significantly reduce the frequency deviation at different operating temperatures.

[0068] Therefore, the present invention can significantly reduce the frequency deviation of the output at different operating temperatures and operating voltages, and can meet application scenarios with high requirements for frequency accuracy.

[0069] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. An oscillation circuit with voltage and temperature compensation, comprising a trigger circuit U1, characterized in that : The trigger circuit U1 includes PMOS transistors and NMOS transistors. The PMOS transistors include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. The NMOS transistors include a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5; The source of the first PMOS transistor MP1 is connected to the VDD power supply. The drain of the source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1. The source of the first NMOS transistor MN1 is grounded; The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 are connected together as the input terminal of the trigger circuit U1; The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the connection terminal of the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2. The source of the third PMOS transistor MP3 is connected to the connection terminal of the drain of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2. The drain of the third NMOS transistor MN3 is connected to the connection terminal of the source of the second NMOS transistor MN2 and the drain of the first NMOS transistor MN1; The drain of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is grounded. The gate of the fourth NMOS transistor MN4 is connected to the VDD power supply; The drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4. The source of the fourth PMOS transistor MP4 is connected to the VDD power supply. The gate of the fourth PMOS transistor MP4 is grounded; The gates of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are connected together. The drain of the fifth PMOS transistor MP5 is connected to the source of the third PMOS transistor MP3. The source of the fifth PMOS transistor MP5 is connected to the VDD power supply. The drain of the fifth NMOS transistor MN5 is connected to the source of the third NMOS transistor MN3. The source of the fifth NMOS transistor MN5 is grounded; The trigger circuit U1 further includes a first inverter I1. The input terminal of the first inverter I1 is connected to the common terminal of the third PMOS transistor MP3 and the third NMOS transistor MN3. The output terminal of the first inverter I1 is connected to the common terminal of the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 and the output terminal of the trigger circuit U1; The described oscillator circuit further includes a NAND gate U2, a second inverter I2, a first capacitor C1, and a first resistor R1. One end of the first capacitor C1 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the trigger circuit U1. The input terminal of the NAND gate U2 is connected to the output terminal of the trigger circuit U1, and the output terminal is connected to the input terminal of the second inverter I2. The output terminal of the second inverter I2 is the output terminal of the oscillator circuit. One end of the first resistor R1 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the NAND gate U2; or the described oscillator circuit further includes a third inverter I3, a fourth inverter I4, an AND gate U3, a fifth inverter I5, a sixth inverter I6, a second capacitor C2, and a second resistor R2. One end of the second capacitor C2 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the trigger circuit U1. The input terminal of the third inverter I3 is connected to the output terminal of the trigger circuit U1, and the output terminal is connected to the input terminal of the fourth inverter I4. The output terminal of the fourth inverter I4 is connected to the input terminal of the AND gate U3. The output terminal of the AND gate U3 is connected to the input terminal of the fifth inverter I5. One end of the second resistor R2 is connected to the input terminal of the trigger circuit U1, and the other end is connected to the output terminal of the fifth inverter I5. The input terminal of the sixth inverter I6 is connected to the common terminal of the third inverter I3 and the fourth inverter I4, and the output terminal of the sixth inverter I6 is the output terminal of the oscillator circuit; The described NAND gate U2 includes an enable terminal and is connected to an enable signal emitting terminal, and the operating state of the NAND gate U2 is controlled by the enable signal; The described AND gate U3 includes an enable terminal and is connected to an enable signal emitting terminal, and the operating state of the AND gate U3 is controlled by the enable signal.

Images