An electrostatic protection device and its preparation method

Abstract

The present invention relates to an electrostatic protection device and a method for preparing the same, and relates to the field of semiconductor technology. The device comprises: a substrate, an epitaxial layer, a buried layer, sequentially adjacent first to fifth well regions, at least two lightly doped injection regions, a heavily doped well region, first to seventh injection regions, a dielectric layer, and a metal layer. The bottoms of the first and fifth well regions are in contact with both the substrate and the buried layer; the bottoms of the second to fourth well regions are in contact with the buried layer. The electrostatic protection device provided by the present invention has lower trigger voltage and breakdown voltage, stronger current flow capacity, higher electrostatic discharge capability, higher stability and reliability, and does not increase the area of ​​the electrostatic protection device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic protection device with low trigger voltage and stronger current carrying capacity and a preparation method thereof. Background Art

[0002] Electrostatic discharge (ESD) is a ubiquitous phenomenon that can occur between any two objects. ESD can severely damage the proper functioning of integrated circuits (ICs) in electrical equipment and, in severe cases, can even burn them out, causing them to fail. As integrated circuits (ICs) develop toward ultra-miniaturization, ultra-high integration, and multifunctionality, they are becoming increasingly sensitive to ESD. Improving the ESD protection capabilities of ICs is crucial and urgent.

[0003] Existing semiconductor devices for ESD protection come in a wide variety of types, typically using diodes, transistors, gate-grounded NMOS (GGNMOS), or silicon controlled rectifiers (SCRs) as basic protection units. Compared to SCR-based protection devices, transistor-based ESD protection devices offer higher current capabilities, making them safer and more flexible to use. This is because SCRs have very low holding voltages and currents, making them susceptible to latch-up, which can damage downstream circuits.

[0004] The current higher requirements for electrostatic protection devices are mainly reflected in the following aspects: on the one hand, it is necessary to reduce the trigger voltage of the electrostatic protection device, especially for integrated circuits with lower operating voltages. In order to avoid the integrated circuit being damaged before the electrostatic protection device is turned on and discharges the current, the trigger voltage of the electrostatic protection device used should be as low as possible. On the other hand, it is necessary to improve the current carrying capacity of the device. The existing technology usually increases the chip area to obtain a larger current carrying capacity, but this method is not conducive to the miniaturization of the device and its application scenarios are relatively limited. Therefore, in response to the above problems, it is necessary to design an electrostatic protection device with a low trigger voltage, stronger current carrying capacity, and suitable for miniaturization, and its preparation method to meet the needs of specific application scenarios. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides an electrostatic protection device and a preparation method thereof, which has a lower trigger voltage, a stronger current-carrying capacity, does not increase the chip area, and is suitable for device miniaturization.

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0007] An electrostatic protection device, comprising: a substrate of a first conductive type and an epitaxial layer located on the substrate;

[0008] A buried layer of a second conductivity type is formed in a predetermined area of ​​the substrate, and the buried layer diffuses upward into the epitaxial layer;

[0009] At least five well regions are sequentially and adjacently formed in the epitaxial layer, including a first well region, a third well region, and a fifth well region of a first conductivity type, wherein the bottoms of the first well region and the fifth well region are in contact with the upper surface of the substrate and the buried layer in the epitaxial layer; and a second well region and a fourth well region of a second conductivity type, wherein the bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer.

[0010] At least two lightly doped implant regions of the second conductivity type are formed in the third well region, including a first lightly doped implant region and a second lightly doped implant region;

[0011] A heavy well region of the first conductivity type is formed between the first lightly doped implant region and the second lightly doped implant region;

[0012] a plurality of heavily doped implant regions, including first to fifth implant regions of the second conductivity type, wherein the first implant region is formed in the second well region, the second implant region is formed in the first lightly doped implant region, the third implant region is formed in the heavily well region, the fourth implant region is formed in the second lightly doped implant region, and the fifth implant region is formed in the fourth well region; a sixth implant region and a seventh implant region of the first conductivity type are formed in the third well region;

[0013] a dielectric layer formed above the epitaxial layer, wherein the dielectric layer is provided with contact holes corresponding to the first to seventh injection regions;

[0014] The metal layer includes a first grounding metal layer, which is respectively connected to the first injection area, the sixth injection area, and the second injection area; an IO end metal layer, which is connected to the third injection area; and a second grounding metal layer, which is respectively connected to the fourth injection area, the seventh injection area, and the fifth injection area.

[0015] In the electrostatic protection device described in the present invention, a first field oxide layer is provided above the first well region and on the left edge of the second well region; the second to seventh field oxide layers are respectively and sequentially arranged between two adjacent heavily doped injection regions; and an eighth field oxide layer is provided on the right edge of the fourth well region and above the fifth well region.

[0016] In the electrostatic protection device of the present invention, the resistivity of the epitaxial layer is greater than 10Ω*cm and the thickness is 3 to 10μm;

[0017] The epitaxial layer is of the first conductivity type or the second conductivity type;

[0018] When the first conductivity type is N-type, the second conductivity type is P-type; and

[0019] When the first conductivity type is P type, the second conductivity type is N type.

[0020] In the electrostatic protection device of the present invention, the distances from the heavy well region to the first lightly doped injection region and the second lightly doped injection region are the same.

[0021] The present invention also provides a method for preparing an electrostatic protection device, which is used to prepare the electrostatic protection device as described above, comprising:

[0022] Step S1, providing a substrate of a first conductivity type, growing a first thin oxide layer on the substrate, then forming a buried layer of a second conductivity type by photolithography, ion implantation, and thermal process advancement, and then removing the first thin oxide layer on the surface by wet etching;

[0023] Step S2, growing an epitaxial layer on the surface, wherein the epitaxial layer is grown at a high temperature so that the buried layer diffuses upward into the epitaxial layer;

[0024] Step S3, sequentially performing photolithography and ion implantation on the surface of the epitaxial layer to form a first well region, a third well region, and a fifth well region of the first conductivity type, and photolithography and ion implantation on the second well region and the fourth well region of the second conductivity type, and then performing high-temperature advancement, so that the first to fifth well regions are sequentially adjacent, and the bottoms of the first well region and the fifth well region are in contact with the substrate and the buried layer in the epitaxial layer at the same time, and the bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer;

[0025] Step S4, growing a field oxide layer on the surface of the epitaxial layer through a local oxidation process;

[0026] Step S5, forming a first lightly doped implantation region and a second lightly doped implantation region of a second conductivity type on the surface of the third well region by photolithography and ion implantation, and then performing high temperature driving;

[0027] Step S6, forming a heavy well region on the surface of the third well region by photolithography and ion implantation, wherein the heavy well region is at the same distance from the first lightly doped implant region and the second lightly doped implant region, and then performing high-temperature implantation, so that the heavy well region laterally diffuses to below the field oxide layer after implantation;

[0028] Step S7, forming first to fifth implantation regions of the second conductivity type on the surface by photolithography and ion implantation, forming a first implantation region in the second well region, forming a second implantation region in the first lightly doped implantation region, forming a third implantation region in the heavily well region, forming a fourth implantation region in the second lightly doped implantation region, and forming a fifth implantation region in the fourth well region;

[0029] Step S8, forming a sixth implantation region and a seventh implantation region of the first conductivity type in the third well region by photolithography and ion implantation;

[0030] Step S9, depositing a dielectric layer on the upper surface of the epitaxial layer, and then forming contact holes corresponding to the first to seventh implantation regions by photolithography and etching;

[0031] Step S10, depositing a metal layer on the upper surface of the dielectric layer and the contact hole, so that the first grounding metal layer is connected to the first injection area, the sixth injection area, and the second injection area, and the IO end metal layer is connected to the third injection area; the second grounding metal layer is connected to the fourth injection area, the seventh injection area, and the fifth injection area.

[0032] The method for preparing the electrostatic protection device of the present invention, wherein the growth thickness of the first thin oxide layer is

[0033] In the preparation method of the electrostatic protection device described in the present invention, in step S1, the ion implantation element of the buried layer is antimony or arsenic, the implantation energy is 60 to 100 KeV, the implantation dose is 5E14 to 8E15 per square centimeter, and the implantation angle is 7 degrees; the furnace tube advancement temperature is 1050°C to 1200°C, and the time is 60 to 120 minutes, so that the junction depth of the buried layer in the substrate is 2 to 3 μm.

[0034] In the method for preparing an electrostatic protection device according to the present invention, in step S3, the implanted element in the first well region, the third well region, and the fifth well region is boron, the implantation dose is 2E12 to 5E13 per square centimeter, the implantation energy is 60 to 100 KeV, and the implantation angle is 7 degrees;

[0035] The implantation element of the second well region and the fourth well region is phosphorus, the implantation dose is 1E14-1E15 per square centimeter, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees;

[0036] Then, high-temperature advancement is carried out, with the advancement temperature being 1000-1150° C. and the advancement time being 60-360 minutes.

[0037] In the preparation method of the electrostatic protection device described in the present invention, in step S5, the implantation element of the first lightly doped implantation region and the second lightly doped implantation region is phosphorus, the implantation dose is 1E13-1E14 per square centimeter, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees; the advancement temperature is 1000-1100°C, and the advancement time is 60-120 minutes, so that the junction depth of the first lightly doped implantation region and the second lightly doped implantation region is 1.5-3um, but does not contact the buried layer in the vertical direction.

[0038] In the method for preparing an electrostatic protection device according to the present invention, in step S6, the implanted element in the heavy well region is boron or boron difluoride, the implantation dose is 1E14 to 8E14 per square centimeter, the implantation energy is 80 to 120 KeV, the implantation temperature is 950 to 1050°C, and the implantation time is 30 to 60 minutes.

[0039] In the method for preparing an electrostatic protection device according to the present invention, in step S7, the implanted element in the first to fifth implantation regions is phosphorus or arsenic, the implantation dose is 2E15 to 1E16 per square centimeter, and the implantation energy is 80 to 120 KeV;

[0040] The implantation element of the sixth implantation region and the seventh implantation region is boron or boron difluoride, the implantation dosage is 1E15-8E15 cm2, and the implantation energy is 40-80 KeV.

[0041] In the method for preparing an electrostatic protection device according to the present invention, in step S7, an annealing process or a rapid thermal annealing process is used after the first to seventh implantation regions are implanted;

[0042] If the annealing process is used, the annealing temperature is 850℃~950℃ and the annealing time is 30~60 minutes;

[0043] If a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050° C., and the rapid thermal annealing time is 10-30 seconds.

[0044] In the method for preparing an electrostatic protection device according to the present invention, step S4 comprises:

[0045] Step S41, growing a second thin oxide layer on the surface of the epitaxial layer, and then depositing a silicon nitride layer;

[0046] Step S42, sequentially performing photolithography and silicon nitride dry etching, removing the photoresist, and then forming a first field oxide layer above the first well region and on the left edge of the second well region, forming second to seventh field oxide layers respectively between two adjacent heavily doped implanted regions, and forming an eighth field oxide layer on the right edge of the fourth well region and above the fifth well region;

[0047] Step S43: removing the remaining silicon nitride layer by a wet etching process.

[0048] The preparation method of the electrostatic protection device of the present invention, the thickness of the second thin oxide layer is

[0049] The preparation method of the electrostatic protection device of the present invention, the thickness of the silicon nitride layer is

[0050] The beneficial effects of the technical solution of the present invention are:

[0051] The electrostatic protection device provided by the present invention has lower trigger voltage and breakdown voltage, stronger current carrying capacity, higher electrostatic discharge capacity, higher stability and reliability, and at the same time does not increase the area of ​​the electrostatic protection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figures 1-9 1 is a schematic diagram of the steps of a method for preparing an electrostatic protection device in a preferred embodiment of the present invention;

[0053] Figure 10-11 1 is a schematic structural diagram of an electrostatic protection device in a preferred embodiment of the present invention;

[0054] Figure 12 FIG. 4 is an equivalent circuit diagram of an electrostatic protection device in a preferred embodiment of the present invention.

[0055] Reference numerals:

[0056] 1. Substrate; 2. Buried layer; 3. Epitaxial layer; 41. First well region; 42. Second well region; 43. Third well region; 44. Fourth well region; 45. Fifth well region; 51. First field oxide layer; 52. Second field oxide layer; 53. Third field oxide layer; 54. Fourth field oxide layer;

[0057] 55, fifth field oxide layer; 56, sixth field oxide layer; 57, seventh field oxide layer;

[0058] 58. Eighth field oxide layer; 61. First lightly doped implantation region;

[0059] 62, second lightly doped implantation region; 7, heavy well region; 81, first implantation region;

[0060] 82, second injection region; 83, third injection region; 84, fourth injection region;

[0061] 85. Fifth injection region; 86. Sixth injection region; 87. Seventh injection region; 9. Dielectric layer; 101. First ground metal layer; 102. Second ground metal layer;

[0062] 103. IO end metal layer. DETAILED DESCRIPTION

[0063] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0064] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0065] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0066] In the embodiment of the present invention, the conductive type includes a first conductive type and a second conductive type, and the first conductive type and the second conductive type are opposite, for example:

[0067] If the first conductivity type is N-type, the second conductivity type is P-type;

[0068] If the first conductivity type is P-type, the second conductivity type is N-type (this is taken as an example in the following embodiment 1).

[0069] Among them, the different situations of the average doping concentrations of N+ type, N type, N- type, P+ type, P type and P- type mentioned below, specifically, the doping concentration of N- type is less than that of N type, the doping concentration of N type is less than that of N+ type, the doping concentration of P- type is less than that of P type, and the doping concentration of P type is less than that of P+ type.

[0070] Example 1

[0071] The embodiment of the present invention provides an electrostatic protection device, see Figure 10 , providing a substrate 1 of a first conductivity type and an epitaxial layer 3 located on the substrate 1, comprising:

[0072] A buried layer 2 of the second conductivity type is formed in a predetermined area of ​​the substrate 1 and diffused upward into the epitaxial layer 3;

[0073] At least five well regions are sequentially and adjacently formed in the epitaxial layer 3, including a first well region 41, a third well region 43, and a fifth well region 45 of the first conductivity type, wherein the bottoms of the first well region 41 and the fifth well region 45 are in contact with the upper surface of the substrate 1 and the buried layer 2 in the epitaxial layer 3; a second well region 42 and a fourth well region 44 of the second conductivity type, wherein the bottoms of the second well region 42, the third well region 43, and the fourth well region 44 are in contact with the buried layer 2;

[0074] At least two lightly doped implant regions of the second conductivity type are formed in the third well region 43 , including a first lightly doped implant region 61 and a second lightly doped implant region 62 ;

[0075] A heavy well region 7 of the first conductivity type is formed between the first lightly doped implant region 61 and the second lightly doped implant region 62;

[0076] a plurality of heavily doped implant regions, including first to fifth implant regions of the second conductivity type, wherein the first implant region 81 is formed in the second well region 42, the second implant region 82 is formed in the first lightly doped implant region 61, the third implant region 83 is formed in the heavily well region 7, the fourth implant region 84 is formed in the second lightly doped implant region 62, and the fifth implant region 85 is formed in the fourth well region 44; a sixth implant region 86 and a seventh implant region 87 of the first conductivity type are formed in the third well region 43;

[0077] A dielectric layer 9 is formed above the epitaxial layer 3 and has contact holes corresponding to the first to seventh injection regions.

[0078] The metal layer includes a first grounding metal layer 101, which is respectively connected to the first injection area 81, the sixth injection area 86, and the second injection area 82; an IO end metal layer 103, which is connected to the third injection area 83; and a second grounding metal layer 102, which is respectively connected to the fourth injection area 84, the seventh injection area 87, and the fifth injection area 85.

[0079] As a preferred embodiment, a first field oxide layer 51 is provided above the first well region 41 and on the left edge of the second well region 42; the second to seventh field oxide layers are respectively arranged between two adjacent heavily doped injection regions, that is, the second field oxide layer 52 is arranged between the first injection region 81 and the sixth injection region 86, the third field oxide layer 53 is arranged between the sixth injection region 86 and the second injection region 82, the fourth field oxide layer 54 is arranged between the second injection region 82 and the third injection region 83, the fifth field oxide layer 55 is arranged between the third injection region 83 and the fourth injection region 84, the sixth field oxide layer 56 is arranged between the fourth injection region 84 and the seventh injection region 87, and the seventh field oxide layer 57 is arranged between the seventh injection region 87 and the fifth injection region 85; an eighth field oxide layer 58 is provided at the right edge of the fourth well region 44 and above the fifth well region 45.

[0080] As a preferred embodiment, the ion implantation element of the buried layer 2 is antimony or arsenic, the implantation energy is 60 to 100 KeV, the implantation dose is 5E14 to 8E15 per square centimeter, and the implantation angle is 7 degrees; the furnace tube advancement temperature is 1050°C to 1200°C, and the time is 60 to 120 minutes, so that the junction depth of the buried layer 2 in the substrate 1 is 2 to 3 μm.

[0081] As a preferred embodiment, the resistivity of the epitaxial layer 3 is greater than 10Ω*cm and the thickness is 3 to 10μm;

[0082] The epitaxial layer 3 is of the first conductivity type or the second conductivity type.

[0083] As a preferred embodiment, the implantation element of the first well region 41, the third well region 43 and the fifth well region 45 is boron, the implantation dose is 2E12-5E13 per square centimeter, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees;

[0084] The implantation element of the second well region 42 and the fourth well region 44 is phosphorus, the implantation dose is 1E14-1E15 per square centimeter, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees;

[0085] Then, high-temperature advancement is carried out, with the advancement temperature being 1000-1150° C. and the advancement time being 60-360 minutes.

[0086] As a preferred embodiment, the implantation element of the first lightly doped implantation region 61 and the second lightly doped implantation region 62 is phosphorus, the implantation dose is 1E13 to 1E14 per square centimeter, the implantation energy is 60 to 100 KeV, and the implantation angle is 7 degrees; the advancement temperature is 1000 to 1100°C, and the advancement time is 60 to 120 minutes, so that the junction depth of the first lightly doped implantation region 61 and the second lightly doped implantation region 62 is 1.5 to 3 um, but does not contact the buried layer 2 in the vertical direction.

[0087] As a preferred embodiment, the distances from the heavy well region 7 to the first lightly doped injection region 61 and the second lightly doped injection region 62 are the same.

[0088] As a preferred embodiment, the implanted element of the heavy well region 7 is boron or boron difluoride, the implantation dose is 1E14 to 8E14 per square centimeter, the implantation energy is 80 to 120 KeV, the implantation temperature is 950 to 1050° C., and the implantation time is 30 to 60 minutes.

[0089] As a preferred embodiment, the implantation elements of the first to fifth implantation regions are phosphorus or arsenic, the implantation dose is 2E15-1E16 per square centimeter, and the implantation energy is 80-120 KeV.

[0090] As a preferred embodiment, the implantation element of the sixth implantation region 86 and the seventh implantation region 87 is boron or boron difluoride, the implantation dose is 1E15 to 8E15 cm2, and the implantation energy is 40 to 80 KeV.

[0091] As a preferred embodiment, wherein the multiple heavily doped implanted regions are implanted using an annealing process or a rapid thermal annealing process;

[0092] If the annealing process is used, the annealing temperature is 850℃~950℃ and the annealing time is 30~60 minutes;

[0093] If a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050° C., and the rapid thermal annealing time is 10-30 seconds.

[0094] Example 2

[0095] See also Figure 1-10 The present invention also provides a method for preparing an electrostatic protection device, which is used to prepare the electrostatic protection device as described above, comprising:

[0096] Step S1, such as Figure 1 As shown, a substrate 1 of a first conductivity type is provided, a first thin oxide layer is grown on the upper surface of the substrate 1, and then an NBL region is defined by NBL lithography, and ion implantation is performed to form a buried layer 2 of a second conductivity type. Then, a thermal process is performed in a furnace tube to make the buried layer 2 have a certain depth, and then the first thin oxide layer on the surface is removed by wet etching.

[0097] In a specific embodiment, the substrate 1 is a P-type substrate with a low doping concentration, and the growth thickness of the first thin oxide layer is Furthermore, the buried layer 2 is an N-type buried layer, the ion implantation element of the N-type buried layer is antimony or arsenic, the implantation energy is 60 to 100 KeV, the implantation dose is 5E14 to 8E15 per square centimeter, and the implantation angle is 7 degrees; it is implanted in a furnace tube at a temperature of 1050°C to 1200°C for 60 to 120 minutes, so that the junction depth of the buried layer 2 in the substrate 1 is 2 to 3 μm.

[0098] Step S2, such as Figure 2 As shown, an epitaxial layer 3 is grown on the surface. The epitaxial layer 3 is grown at a high temperature so that the buried layer 2 diffuses upward into the epitaxial layer 3.

[0099] In a specific embodiment, the epitaxial layer 3 can be N-type or P-type.

[0100] Step 2: Perform epitaxial growth on the upper surface of the silicon wafer.

[0101] Preferably, epitaxial growth can be performed, but the resistivity of the epitaxial layer 3 should be higher, preferably, the resistivity should be greater than 10Ω*cm, and the thickness should be 3 to 10μm; more preferably, the thickness of the epitaxial layer 3 should be 3 to 5μm.

[0102] Furthermore, since the epitaxial layer 3 is grown at a high temperature, the buried layer 2 will diffuse upward and enter the epitaxial layer 3 .

[0103] Step S3, such as Figure 3As shown, photolithography and ion implantation of the first well region 41, the third well region 43, and the fifth well region 45 of the first conductivity type are sequentially performed on the surface of the epitaxial layer 3, and photolithography and ion implantation of the second well region 42 and the fourth well region 44 of the second conductivity type are performed, and then a high-temperature push-in is performed, so that the first to fifth well regions are sequentially adjacent, and the bottoms of the first well region 41 and the fifth well region 45 are in contact with the substrate 1 and the buried layer 2 in the epitaxial layer 3 at the same time, and the bottoms of the second well region 42, the third well region 43, and the fourth well region 44 are in contact with the buried layer 2;

[0104] Preferably, the first well region 41, the third well region 43 and the fifth well region 45 are all P-type well regions, and the implanted element is boron with an implantation dose of 2E12-5E13 cm -2 , the injection energy is 60-100 KeV, and the injection angle is 7 degrees;

[0105] The second well region 42 and the fourth well region 44 are both N-type well regions, and the implanted element is phosphorus with an implantation dose of 1E14-1E15 cm -2 The injection energy is 80-120 KeV and the injection angle is 7 degrees.

[0106] After the above-mentioned ion implantation, it enters the furnace tube for advancement, the advancement temperature is 1000-1150°C, and the advancement time is 60-360 minutes, so that the first to fifth well regions are adjacent to each other in sequence, and the bottoms of the first well region 41 and the fifth well region 45 are in contact with the upper surface of the substrate 1, the right edge of the first well region 41 and the left edge of the fifth well region 45 are in contact with the part of the buried layer 2 diffused into the epitaxial layer 3, and the bottoms of the second to fourth well regions are all in contact with the buried layer 2; preferably, the second well region 42 and the fourth well region 44 are connected to the two ends of the buried layer 2.

[0107] Step S4, as Figure 4 As shown, a field oxide layer (FOX) is grown on the surface of the epitaxial layer 3 through a local oxidation process;

[0108] In a specific embodiment, step S4 includes:

[0109] Step S41, growing a second thin oxide layer on the surface of the epitaxial layer 3, and then depositing a silicon nitride layer;

[0110] Step S42, sequentially performing photolithography, silicon nitride dry etching, and removing the photoresist, a first field oxide layer 51 is formed above the first well region 41 and on the left edge of the second well region 42, second to seventh field oxide layers are formed in sequence between two adjacent heavily doped implant regions, and an eighth field oxide layer 58 is formed on the right edge of the fourth well region 44 and above the fifth well region 45;

[0111] Step S43: removing the remaining silicon nitride layer by a wet etching process.

[0112] Furthermore, the thickness of the second thin oxide layer is

[0113] Furthermore, the thickness of the silicon nitride layer is

[0114] Step S5, as Figure 5 As shown, a first lightly doped implantation region 61 and a second lightly doped implantation region 62 of the second conductivity type are formed on the surface of the third well region 43 by photolithography and ion implantation, and then a high temperature push-in is performed;

[0115] In a specific embodiment, the first lightly doped implantation region 61 and the second lightly doped implantation region 62 are both N-type implantation regions, the implantation element is phosphorus, and the implantation dose is 1E13-1E14 cm -2 The implantation energy is 60-100 KeV, and the implantation angle is 7 degrees. The first lightly doped implantation region 61 and the second lightly doped implantation region 62 are both within the third well region 43 and above the buried layer 2. The device is placed in a high-temperature furnace tube for advancement at a temperature of 1000-1100°C for 60-120 minutes, so that the N-type implantation region has a certain junction depth and lateral diffusion. Preferably, the junction depth of the N-type implantation region is 1.5-3 μm, and there is a certain distance in the vertical direction from the buried layer 2, so that the two cannot be connected.

[0116] Step S6, as Figure 6 As shown, a heavy well region 7 is formed on the surface of the third well region 43 by photolithography and ion implantation. The distance between the heavy well region 7 and the first lightly doped implantation region 61 and the second lightly doped implantation region 62 is the same. Then, a high temperature push-in is performed. After the push-in, the heavy well region diffuses laterally to the bottom of the field oxide layer.

[0117] In a specific embodiment, the heavy well region 7 is between the first lightly doped injection region 61 and the second lightly doped injection region 62, and the distance between the heavy well region 7 and the first lightly doped injection region 61 is the same as the distance between the heavy well region 7 and the second lightly doped injection region 62. The implanted element is boron or boron difluoride, and the implantation dose is 1E14 to 8E14 cm -2 The implantation energy is 80-120 KeV. After the high temperature furnace tube is pushed forward, the heavy well region 7 is laterally diffused to the bottom of the fourth field oxide layer and the fifth field oxide layer.

[0118] Step S7, as Figure 7 As shown, first to fifth implantation regions of the second conductivity type are formed on the above surface by photolithography and ion implantation, a first implantation region 81 is formed in the second well region 42, a second implantation region 82 is formed in the first lightly doped implantation region 61, a third implantation region 83 is formed in the heavy well region 7, a fourth implantation region 84 is formed in the second lightly doped implantation region 62, and a fifth implantation region 85 is formed in the fourth well region 44;

[0119] In a specific embodiment, the first to fifth implantation regions are all N+ implantation regions, the implantation element is phosphorus or arsenic, and the implantation dose is 2E15-1E16 cm -2 , the injection energy is 80~120KeV.

[0120] Step S8, as Figure 8 As shown, a sixth implantation region 86 and a seventh implantation region 87 of the first conductivity type are formed in the third well region 43 by photolithography and ion implantation;

[0121] In a specific embodiment, the sixth implantation region 86 and the seventh implantation region 87 are both P+ implantation regions. P+ photolithography and P+ ion implantation are performed on the above surface. The implantation element is boron or boron difluoride. The implantation dose is 1E15-8E15 cm -2 The implantation energy is 40 to 80 KeV, and then an annealing process is performed to repair the implantation damage.

[0122] Furthermore, the annealing process may be performed using a furnace annealing process or a rapid thermal annealing process;

[0123] If a furnace tube is used for annealing, the annealing temperature is 850°C to 950°C and the annealing time is 30 to 60 minutes;

[0124] If a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050° C., and the rapid thermal annealing time is 10-30 seconds.

[0125] Step S9, as Figure 9 As shown, a dielectric layer 9 is deposited on the upper surface of the epitaxial layer 3, and then contact holes corresponding to the first to seventh implantation regions are formed by photolithography and etching;

[0126] In a specific embodiment, the dielectric layer 9 may be an oxide layer, or borophosphorus glass, or a composite layer formed by multiple insulating films.

[0127] Step S10, as Figure 10 As shown, metal layers are deposited on the upper surface of the dielectric layer 9 and in the contact holes, so that the first grounding metal layer 101 is simultaneously connected to the first injection area 81, the sixth injection area 86, and the second injection area 82, and the IO end metal layer 103 is connected to the third injection area 83; the second grounding metal layer 102 is simultaneously connected to the fourth injection area 84, the seventh injection area 87, and the fifth injection area 85.

[0128] Preferably, the metal layer can be pure aluminum or aluminum silicon compound; more preferably, it is a three-layer composite structure, which is titanium, titanium nitride, and aluminum silicon copper from bottom to top, wherein the thickness of titanium is The thickness of titanium nitride is The thickness of aluminum silicon copper is 2 to 4 μm.

[0129] In a specific embodiment, Figure 11 As shown, the IO terminal metal layer 103 is connected to the IO terminal, and the IO terminal metal layer 103 is only connected to the third injection region 83 in contact with the heavy well region 7; the first ground terminal metal layer 101 and the second ground terminal metal layer 102 are both connected to the Gnd terminal.

[0130] As a preferred embodiment, Figure 12 As shown, it is an equivalent circuit diagram of the electrostatic protection device disclosed in an embodiment of the present invention, wherein the first diode D1 is a reverse diode, formed by the third injection region 83 and the heavy well region 7; the second diode D2 is a forward diode, formed by the third well region 43 and the heavy well region 7; the first transistor T1 is an NPN transistor, formed by the first injection region 81, the third well region 43, the first lightly doped injection region 61, and the second injection region 82 on the left; the second transistor T2 is an NPN transistor, formed by the fifth injection region 85, the third well region 43, the second lightly doped injection region 62, and the fourth injection region 84 on the right; the third well region 43 is the base region of the first transistor T1, and the first resistor R1 is the parasitic resistance of the third well region 43; the third well region 43 is the base region of the second transistor T2, and the second resistor R2 is the parasitic resistance of the third well region 43.

[0131] Among them, the cathode of the first diode D1 is connected to the IO terminal, the anode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the Gnd terminal; the bases of the first transistor T1 and the second transistor T2 are both connected to the connection between the anode of the first diode D1 and the anode of the second diode D2, the collectors of the first transistor T1 and the second transistor T2 are connected to the IO terminal, and the emitters of the first transistor T1 and the second transistor T2 are connected to the Gnd terminal; the first resistor R1 is connected between the base and emitter of the first transistor T1, and the second resistor R2 is connected between the base and emitter of the second transistor T2.

[0132] When an electrostatic discharge (ESD) event occurs in the device, since the heavy well region 7 is heavily doped, the reverse breakdown voltage of the first diode D1 is low, which can quickly assist in triggering the junction between the second injection region 82 and the third well region 43 of the first transistor T1 and the junction between the fourth injection region 84 and the third well region 43 of the second transistor T2 to breakdown. The electrostatic current flows through the third well region 43, then flows out of the first ground terminal metal layer 101 from the sixth injection region 86, and flows out of the second ground terminal metal layer 102 from the seventh injection region 87 to the Gnd terminal. Since the third well region 43 is lightly doped, its The resistance is relatively high, so the voltage difference generated by the electrostatic current from the third well region 43 to the sixth injection region 86 can easily reach 0.7V, causing the third well region 43 and the first lightly doped injection region 61 to be forward-conducted. At this time, a bipolar transistor effect will be generated, and a large amount of electrostatic current will enter the first lightly doped injection region 61 and then flow out from the second injection region 82; similarly, a large amount of electrostatic current will enter the second lightly doped injection region 62 and then flow out from the fourth injection region 84, presenting a significant negative resistance characteristic, and the current-voltage curve will have a significant snapback, so the pulse voltage can be clamped at a lower level.

[0133] In addition, since the first diode D1 and the second diode D2 are connected in series, they are essentially also NPN transistors, consisting of the third injection region 83, the heavy well region 7, the third well region 43, and the buried layer 2. When its transistor effect occurs, a large amount of electrostatic current enters from the third injection region 83 at the IO end, passes through the heavy well region 7 and the third well region 43, and then passes through the buried layer 2, the second well region 42 and the fourth well region 44 on both sides, and finally flows out from the first injection region 81 in the second well region 42 and the fifth injection region 85 in the fourth well region 44, thereby also realizing the discharge of electrostatic current.

[0134] Therefore, the electrostatic current of the embodiment of the present invention can not only be discharged from the IO terminal to the second injection area 82 and the fourth injection area 84 on both sides of the third well area 43, but also can be discharged from the bottom buried layer 2 to the first injection area 81 and the fifth injection area 85 on both sides of the device. Both of them utilize the negative resistance snapback characteristics when the transistor effect is generated, so their breakdown voltage and trigger voltage are lower, and the protection response is faster; at the same time, the on-resistance and the clamping voltage are smaller, and the protection capability for the subsequent integrated circuit is stronger.

[0135] Example 2

[0136] See also Figure 11 In the embodiment of the present invention, based on the embodiment one, the type of each doping region is changed in the embodiment two, all N-type is changed to P-type, and all P-type is changed to N-type. The steps of the preparation method are the same as those in the above embodiment, and the doping element type and doping process parameters of each doping region are adaptively adjusted. The embodiment two has the same characteristics as the embodiment one and will not be repeated here.

[0137] The above technical solution has the following advantages or beneficial effects: the electrostatic protection device provided by the present invention has lower trigger voltage and breakdown voltage, stronger current-carrying capacity, higher electrostatic discharge capacity, higher stability and reliability, and at the same time does not increase the area of ​​the electrostatic protection device.

[0138] Through the description and drawings, typical embodiments of the specific structure of the specific implementation are given. Based on the spirit of the present invention, other transformations can be made. Although the above invention has proposed the existing preferred embodiments, however, these contents are not intended to be limiting.

[0139] Various changes and modifications will undoubtedly become apparent to those skilled in the art upon reading the foregoing description. Therefore, the appended claims should be construed to encompass all changes and modifications within the true intent and scope of the present invention. Any and all equivalents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims

1. An electrostatic protection device, comprising a substrate of a first conductive type and an epitaxial layer located on the substrate, characterized in that: include: A buried layer of a second conductivity type is formed in a predetermined area of ​​the substrate, and the buried layer diffuses upward into the epitaxial layer; At least five well regions are sequentially and adjacently formed in the epitaxial layer, including a first well region, a third well region, and a fifth well region of the first conductivity type, wherein bottoms of the first well region and the fifth well region are in contact with the upper surface of the substrate and the buried layer in the epitaxial layer at the same time; a second well region and a fourth well region of a second conductivity type, wherein bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer; At least two lightly doped implant regions of the second conductivity type are formed in the third well region, including a first lightly doped implant region and a second lightly doped implant region; A heavy well region of the first conductivity type is formed between the first lightly doped implant region and the second lightly doped implant region; a plurality of heavily doped implant regions, including first to fifth implant regions of the second conductivity type, wherein the first implant region is formed in the second well region, the second implant region is formed in the first lightly doped implant region, the third implant region is formed in the heavily well region, the fourth implant region is formed in the second lightly doped implant region, and the fifth implant region is formed in the fourth well region; a sixth implant region and a seventh implant region of the first conductivity type are formed in the third well region; a dielectric layer formed above the epitaxial layer, wherein the dielectric layer is provided with contact holes corresponding to the first to seventh injection regions; The metal layer includes a first grounding metal layer, connected to the first injection region, the sixth injection region, and the second injection region respectively; The IO terminal metal layer is connected to the third injection area; the second ground terminal metal layer is connected to the fourth injection area, the seventh injection area, and the fifth injection area respectively.

2. The electrostatic protection device according to claim 1, characterized in that: A first field oxide layer is provided above the first well region and on the left edge of the second well region; the second to seventh field oxide layers are respectively arranged between two adjacent heavily doped injection regions; and an eighth field oxide layer is provided on the right edge of the fourth well region and above the fifth well region.

3. The electrostatic protection device according to claim 1, characterized in that: The resistivity of the epitaxial layer is greater than 10Ω*cm and the thickness is 3 to 10μm; The epitaxial layer is of the first conductivity type or the second conductivity type; When the first conductivity type is N-type, the second conductivity type is P-type; and When the first conductivity type is P type, the second conductivity type is N type.

4. The electrostatic protection device according to claim 1, characterized in that: The distances from the heavy well region to the first lightly doped injection region and the second lightly doped injection region are the same.

5. A method for preparing an electrostatic protection device, characterized in that: For preparing the electrostatic protection device according to any one of claims 1 to 4, comprising: Step S1, providing a substrate of a first conductivity type, growing a first thin oxide layer on the substrate, then forming a buried layer of a second conductivity type by photolithography, ion implantation, and thermal process advancement, and then removing the first thin oxide layer on the surface by wet etching; Step S2, growing an epitaxial layer on the surface, wherein the epitaxial layer is grown at a high temperature so that the buried layer diffuses upward into the epitaxial layer; Step S3, sequentially performing photolithography and ion implantation on the surface of the epitaxial layer to form a first well region, a third well region, and a fifth well region of the first conductivity type, and photolithography and ion implantation on the second well region and the fourth well region of the second conductivity type, and then performing high-temperature advancement, so that the first to fifth well regions are sequentially adjacent, and the bottoms of the first well region and the fifth well region are in contact with the substrate and the buried layer in the epitaxial layer at the same time, and the bottoms of the second well region, the third well region, and the fourth well region are in contact with the buried layer; Step S4, growing a field oxide layer on the surface of the epitaxial layer through a local oxidation process; Step S5, forming a first lightly doped implantation region and a second lightly doped implantation region of a second conductivity type on the surface of the third well region by photolithography and ion implantation, and then performing high temperature driving; Step S6, forming a heavy well region on the surface of the third well region by photolithography and ion implantation, wherein the heavy well region is at the same distance from the first lightly doped implant region and the second lightly doped implant region, and then performing high-temperature implantation, so that the heavy well region laterally diffuses to below the field oxide layer after implantation; Step S7, forming first to fifth implantation regions of the second conductivity type on the surface by photolithography and ion implantation, forming a first implantation region in the second well region, forming a second implantation region in the first lightly doped implantation region, forming a third implantation region in the heavily well region, forming a fourth implantation region in the second lightly doped implantation region, and forming a fifth implantation region in the fourth well region; Step S8, forming a sixth implantation region and a seventh implantation region of the first conductivity type in the third well region by photolithography and ion implantation; Step S9, depositing a dielectric layer on the upper surface of the epitaxial layer, and then forming contact holes corresponding to the first to seventh implantation regions by photolithography and etching; Step S10, depositing a metal layer on the upper surface of the dielectric layer and the contact hole, so that the first grounding metal layer is connected to the first injection area, the sixth injection area, and the second injection area, and the IO end metal layer is connected to the third injection area; the second grounding metal layer is connected to the fourth injection area, the seventh injection area, and the fifth injection area.

6. The method for preparing an electrostatic protection device according to claim 5, wherein: The growth thickness of the first thin oxide layer is 7. The method for preparing an electrostatic protection device according to claim 5, wherein: In step S1, the ion implantation element of the buried layer is antimony or arsenic, the implantation energy is 60-100 KeV, the implantation dose is 5E14-8E15 per square centimeter, and the implantation angle is 7 degrees; the furnace tube advancement temperature is 1050°C-1200°C, and the time is 60-120 minutes, so that the junction depth of the buried layer in the substrate is 2-3 μm.

8. The method for preparing an electrostatic protection device according to claim 5, wherein: In step S3, the implantation element of the first well region, the third well region, and the fifth well region is boron, the implantation dose is 2E12-5E13 per square centimeter, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees; The implantation element of the second well region and the fourth well region is phosphorus, the implantation dose is 1E14-1E15 per square centimeter, the implantation energy is 80-120 KeV, and the implantation angle is 7 degrees; Then, high-temperature advancement is carried out, with the advancement temperature being 1000-1150° C. and the advancement time being 60-360 minutes.

9. The method for preparing an electrostatic protection device according to claim 5, wherein: In step S5, the implantation element of the first lightly doped implantation region and the second lightly doped implantation region is phosphorus, the implantation dose is 1E13-1E14 per square centimeter, the implantation energy is 60-100 KeV, and the implantation angle is 7 degrees; the advancement temperature is 1000-1100°C, and the advancement time is 60-120 minutes, so that the junction depth of the first lightly doped implantation region and the second lightly doped implantation region is 1.5-3um, but does not contact the buried layer in the vertical direction.

10. The method for preparing an electrostatic protection device according to claim 5, wherein: In step S6, the implanted element in the heavy well region is boron or boron difluoride, the implantation dose is 1E14-8E14 per square centimeter, the implantation energy is 80-120 KeV, the implantation temperature is 950-1050° C., and the implantation time is 30-60 minutes.

11. The method for preparing an electrostatic protection device according to claim 5, wherein: In step S7, the implantation elements of the first to fifth implantation regions are phosphorus or arsenic, the implantation dose is 2E15-1E16 per square centimeter, and the implantation energy is 80-120 KeV; The implantation element of the sixth implantation region and the seventh implantation region is boron or boron difluoride, the implantation dosage is 1E15-8E15 cm2, and the implantation energy is 40-80 KeV.

12. The method for preparing an electrostatic protection device according to claim 5, wherein: In the step S7, an annealing process or a rapid thermal annealing process is used after the first to seventh implantation regions are implanted; If the annealing process is used, the annealing temperature is 850℃~950℃ and the annealing time is 30~60 minutes; If a rapid thermal annealing process is used, the rapid thermal annealing temperature is 950-1050° C., and the rapid thermal annealing time is 10-30 seconds.

13. The method for preparing an electrostatic protection device according to claim 5, wherein: The step S4 comprises: Step S41, growing a second thin oxide layer on the surface of the epitaxial layer, and then depositing a silicon nitride layer; Step S42, sequentially performing photolithography and silicon nitride dry etching, removing the photoresist, and then forming a first field oxide layer above the first well region and on the left edge of the second well region, forming second to seventh field oxide layers respectively between two adjacent heavily doped implanted regions, and forming an eighth field oxide layer on the right edge of the fourth well region and above the fifth well region; Step S43: removing the remaining silicon nitride layer by a wet etching process.

14. The method for preparing an electrostatic protection device according to claim 13, wherein: The thickness of the second thin oxide layer is 15. The method for preparing an electrostatic protection device according to claim 13, wherein: The thickness of the silicon nitride layer is

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