Epitaxial structure for LED flip chip and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and specifically discloses an epitaxial structure for LED flip chips and a preparation method thereof, comprising: providing a substrate; epitaxially growing an epitaxial layer on the substrate; the epitaxial layer comprising a multi-quantum well layer and a p-type layer sequentially deposited along the epitaxial direction; the multi-quantum well layer comprising a BGaN pre-well protective layer, an InGaN well layer, a BGaN post-well protective layer, and an N-GaN barrier layer that are periodically and alternately grown; the p-type layer comprising an insulating protective layer and a P-GaN layer sequentially deposited along the epitaxial direction, wherein the insulating protective layer is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities. The preparation method of the present invention can effectively improve the crystal quality of the epitaxial structure, reduce dislocation density, reduce leakage and electron overflow, and increase the series resistance under low current, thereby increasing the turn-on voltage of the LED flip chip under low current, and solving the problem of uneven brightness of the LED flip chip under low current (current less than 1uA) in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an epitaxial structure for an LED flip chip and a preparation method thereof. Background Art

[0002] LED flip-chips offer advantages over regular chips in terms of light output, brightness, heat dissipation, physical size limits, and packaging process efficiency. They are primarily used in automotive headlights and mobile phone flashlights. However, existing LED flip-chips exhibit uneven brightness at low currents (less than 1uA). This means that some LEDs light up first while others remain dimmed, resulting in significant brightness discrepancies. This is primarily due to the fact that at low currents, the LED chip generates a certain amount of brightness, creating a soft-start phenomenon when the LED is turned on. Summary of the Invention

[0003] The purpose of the present invention is to provide an epitaxial structure for LED flip chips and a preparation method thereof in response to the existing technical status. The preparation method of the present invention can effectively improve the crystal quality of the epitaxial structure, reduce dislocation density, reduce leakage and electron overflow, and increase the series resistance under low current, thereby increasing the turn-on voltage of the LED flip chip under low current, thereby solving the problem of uneven brightness of LED flip chips under low current (current less than 1uA) in the prior art.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] As one of the objects of the present invention, the present invention provides a method for preparing an epitaxial structure for an LED flip chip, comprising:

[0006] providing a substrate;

[0007] epitaxially growing an epitaxial layer on a substrate;

[0008] The epitaxial layer includes a multi-quantum well layer and a P-type layer sequentially deposited along the epitaxial direction;

[0009] The multi-quantum well layer includes a BGaN front-well protection layer, an InGaN well layer, a BGaN rear-well protection layer and an N-GaN barrier layer that are periodically and alternately grown in sequence;

[0010] The P-type layer includes an insulating protection layer and a P-GaN layer sequentially deposited along the epitaxial direction. The insulating protection layer is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities.

[0011] In some embodiments, including:

[0012] After the BGaN well rear protective layer is deposited, the BGaN well rear protective layer is subjected to H2 treatment;

[0013] After the N-GaN barrier layer is deposited, the N-GaN barrier layer is subjected to H2 treatment.

[0014] In some embodiments, during the H2 treatment, the H2 introduction time is 5 to 20 s, and the introduction flow rate is 10 to 20 l / min.

[0015] In some embodiments, a GaN layer is further provided between the insulating protection layer and the P-GaN layer.

[0016] In some embodiments, the BGaN / GaN superlattice structure includes BGaN sublayers and GaN sublayers that are grown alternately and periodically, with the number of periods being 3 to 10. The thickness of the BGaN sublayer in each period is 1 to 2 nm, and the thickness of the GaN sublayer is 3 to 5 nm; the thickness of the P-GaN layer is 50 to 100 nm; and the thickness of the GaN layer is 50 to 100 nm.

[0017] In some embodiments, the growth temperature of the InGaN well layer is 750-800°C, the growth temperature of the N-GaN barrier layer is 840-900°C, and the growth temperature of the BGaN front well protection layer and the BGaN rear well protection layer is 780-840°C.

[0018] In some embodiments, the rotation speed of the multi-quantum well layer is 500-700 r / min, the growth temperature of the P-type layer is 900-1000°C, the rotation speed of the BGaN / GaN superlattice structure is 700-1000 r / min, and the rotation speed of the P-GaN layer is 900-1200 r / min.

[0019] In some embodiments, the growth atmosphere of the InGaN well layer is N2.

[0020] In some embodiments, the B component content in the BGaN pre-well protection layer and the BGaN post-well protection layer is 0.01-0.2, and the B component content in the BGaN / GaN superlattice structure is 0.01-0.2.

[0021] As another object of the present invention, the present invention further provides an epitaxial structure for LED flip chip, which is prepared according to the above-mentioned preparation method.

[0022] The beneficial effects of the present invention are:

[0023] The present invention improves the multi-quantum well layer and the P-type layer. The multi-quantum well layer adopts an InGaN well layer and an N-GaN barrier layer, and inserts a BGaN well front protection layer and a BGaN well rear protection layer before and after the InGaN well layer respectively. A BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities is inserted into the P-type layer as an insulating protection layer, which effectively improves the crystal quality of the epitaxial structure, reduces the dislocation density, reduces leakage and electron overflow, and increases the series resistance under low current, effectively improving the turn-on voltage of the LED flip chip under low current (current less than 1uA), thereby solving the problem of uneven brightness of the LED flip chip under low current in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of the epitaxial structure for LED flip chip of the present invention.

[0025] Figure 2 Schematic diagram of the process of preparing a multi-quantum well layer according to Example 1 of the present invention.

[0026] Figure 3 Schematic diagram of the process of preparing the P-type layer according to Example 1 of the present invention.

[0027] Figure 4 This is the brightness display of each experimental group in the brightness and darkness unevenness test. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention is further described in detail below:

[0029] See Figure 1 As shown, the present invention discloses a method for preparing an epitaxial structure for an LED flip chip, comprising:

[0030] Providing a substrate 1;

[0031] epitaxially growing an epitaxial layer on a substrate 1;

[0032] The epitaxial layer includes a multi-quantum well layer 4 and a P-type layer 6 sequentially deposited along the epitaxial direction;

[0033] The multi-quantum well layer 4 includes a BGaN front-well protection layer 41, an InGaN well layer 42, a BGaN rear-well protection layer 43 and an N-GaN barrier layer 44 that are periodically and alternately grown.

[0034] The P-type layer 6 includes an insulating protection layer 61 and a P-GaN layer 63 sequentially deposited along the epitaxial direction. The insulating protection layer 61 is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities.

[0035] In the present invention, for the multi-quantum well layer 4, a BGaN front-well protective layer 41 and a BGaN rear-well protective layer 43 are respectively inserted before and after the InGaN well layer 42. On the one hand, they protect the InGaN well layer 42, reduce the influence of the reaction chamber environment on the InGaN well layer 42 during the growth of the N-GaN barrier layer 44, avoid surface re-evaporation and analytical separation of the In component, ensure the growth of high-quality N-GaN barrier layer 44 in a suitable environment, and ensure the crystal quality of the InGaN well layer 42; on the other hand, BGaN can alleviate the stress mismatch and lattice mismatch between InGaN and N-GaN, reduce the defect problems caused by stress and lattice mismatch, reduce defect density, block the extension of defects, and reduce leakage; furthermore, IBGaN can also increase the potential barrier, prevent carrier localization caused by uneven distribution of In components, and avoid incomplete recombination and electron overflow. For the P-type layer 6, a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities is inserted before the P-GaN layer 63. Since the BGaN / GaN superlattice structure is not conductively doped, it can effectively increase the series resistance under low current and play an insulating protection role.

[0036] An ideal diode volt-ampere characteristic curve is that when forward bias is applied, the current is almost zero when VD (forward voltage drop) is very small. When VD increases to a certain threshold, the current begins to increase rapidly, exponentially. The present invention improves the multi-quantum well layer 4 and the P-type layer 6 to effectively improve the crystal quality of the epitaxial structure, reduce dislocation density, minimize leakage and electron overflow, and increase the series resistance at low currents. This effectively increases the turn-on voltage of the LED flip chip at low currents (currents less than 1uA), thereby solving the problem of uneven dimming and brightness of LED flip chips at low currents in the prior art.

[0037] The substrate 1 may be any one of a sapphire substrate 1, a silicon carbide substrate 1, a silicon substrate 1, an aluminum nitride substrate 1, a gallium nitride substrate 1 or gallium oxide.

[0038] An electron blocking layer 5 is further provided between the multi-quantum well layer 4 and the P-type layer 6 , and the epitaxial layer further includes a buffer layer 2 and an N-type layer 3 sequentially deposited along the epitaxial direction.

[0039] Among them, including:

[0040] After the BGaN well rear protection layer 43 is deposited, the BGaN well rear protection layer 43 is subjected to H2 treatment;

[0041] After the deposition of the N-GaN barrier layer 44 is completed, the N-GaN barrier layer 44 is subjected to H 2 treatment.

[0042] Through H2 treatment, impurities in the material layer can be reduced, interface quality can be improved, defect density can be further reduced, and leakage can be reduced.

[0043] In which, during H2 treatment, the H2 introduction time is 5 to 20 s, and exemplarily, the introduction time is 10 s, 13 s, 16 s or 20 s, but not limited thereto, and the introduction flow rate is 10 to 20 l / min, and exemplarily, the introduction flow rate is 10 l / min, 13 l / min, 16 l / min or 20 l / min, but not limited thereto.

[0044] A GaN layer 62 is further provided between the insulating protection layer 61 and the P-GaN layer 63 . The GaN layer 62 is not intentionally doped with P-type impurities, thereby further improving the insulating protection effect.

[0045] Among them, the BGaN / GaN superlattice structure includes BGaN sublayers and GaN sublayers that are periodically grown alternately, with the number of periods being 3 to 10. The thickness of the BGaN sublayer in each period is 1 to 2 nm, and the thickness of the GaN sublayer is 3 to 5 nm. Exemplarily, the thickness of the BGaN sublayer in each period is 1 nm, 1.3 nm, 1.6 nm, 1.9 nm or 2 nm, but not limited thereto, and the thickness of the GaN sublayer is 3 nm, 4 nm or 5 nm, but not limited thereto. The thickness of the P-GaN layer 63 is 50 to 100 nm. Exemplarily, the thickness of the P-GaN layer 63 is 55 nm, 75 nm, 85 nm or 95 nm, but not limited thereto. The thickness of the GaN layer 62 is 50 to 100 nm. Exemplarily, the thickness of the GaN layer 62 is 55 nm, 65 nm, 85 nm, 90 nm or 100 nm, but not limited thereto.

[0046] Among them, the number of periods of the multi-quantum well layer 4 is 5 to 15, the thickness of the BGaN pre-well protection layer 41 is 0.1 to 1 nm, and the thickness of the InGaN well layer 42 is 2 to 5 nm. If the thickness of the InGaN well layer 42 is too large, it is easy to increase dislocation defects and cause leakage problems. The thickness of the BGaN post-well protection layer 43 is 0.1 to 1 nm. If the thickness of the BGaN pre-well protection layer 41 and the BGaN post-well protection layer 43 are too small, the protection effect is insufficient, and the improvement effect on stress and lattice mismatch is insufficient. The thickness of the N-GaN barrier layer 44 is 5 to 10 nm.

[0047] The P-type impurity doping concentration in the P-GaN layer 63 is 1*10 18 / cm 3 ~1*10 20 / cm 3 , a high concentration of P-type impurities can easily lead to poor crystal quality.

[0048] Among them, the growth temperature of the InGaN well layer 42 is 750-800°C. Exemplarily, the growth temperature of the InGaN well layer 42 is 750°C, 770°C, 790°C or 800°C, but not limited to this. In the present invention, the InGaN well layer 42 is grown at a low temperature. Under low temperature conditions, the incorporation of the In component is easier. If the temperature is too low, the crystal quality is easily reduced. If the temperature is too high, the incorporation of the In component is difficult. In addition, since the BGaN well front protection layer 41 and the BGaN well rear protection layer 43 are inserted before and after the InGaN well layer 42, B doping in GaN can block the defects formed by low-temperature growth and the defect extension caused by lattice mismatch stress. The growth temperature of the N-GaN barrier layer 44 is 840-900°C. Exemplarily, the growth temperature of the N-GaN barrier layer 44 is 840°C, 860°C, 880°C or 900°C, but not limited to this. In the present invention, the InGaN well layer 42 is grown at a low temperature. Under low temperature conditions, the incorporation of the In component is easier. If the temperature is too low, the crystal quality is easily reduced. If the temperature is too high, the incorporation of the In component is difficult. In addition, since the BGaN well front protection layer 41 and the BGaN well rear protection layer 43 are inserted before and after the InGaN well layer 42, B doping in GaN can block the defects formed by low-temperature growth and the defect extension caused by lattice mismatch stress. The growth temperature of the N-GaN barrier layer 44 is 840-900°C. Exemplarily, the growth temperature of the N-GaN barrier layer 44 is 840°C, 860°C, 880 The N-GaN barrier layer 44 is grown at high temperature. The higher temperature can promote the lateral growth ability of the crystal and easily generate high-quality crystals. Since the BGaN pre-well protective layer 41 and the BGaN post-well protective layer 43 are inserted before and after the InGaN well layer 42, the damage to the InGaN well layer 42 caused by the high temperature of the N-GaN barrier layer 44 can be effectively avoided, and the surface re-evaporation and decomposition separation of the In component in the InGaN well layer 42 caused by the high temperature can be avoided. The growth temperature of the BGaN pre-well protective layer 41 and the BGaN post-well protective layer 43 is 780-840°C. Exemplarily, the growth temperature of the BGaN pre-well protective layer 41 and the BGaN post-well protective layer 43 is 780°C, 790°C, 820°C or 840°C, but not limited to this. The temperature of the BGaN pre-well protective layer 41 and the BGaN post-well protective layer 43 should not be too high to avoid damage to the InGaN well layer 42 caused by high temperature.

[0049] Among them, the rotation speed of the multi-quantum well layer 4 is 500~700r / min, and exemplarily, the rotation speed of the quantum well layer is 500r / min, 550r / min, 650r / min or 700r / min, but not limited to this. The growth temperature of the P-type layer 6 is 900~1000℃, the rotation speed of the BGaN / GaN superlattice structure is 700~1000r / min, and exemplarily, the rotation speed of the BGaN / GaN superlattice structure is 750r / min, 850r / min, 950r / min or 1000r / min, but not limited to this. The rotation speed of the GaN layer 62 and the P-GaN layer 63 is 900~1200r / min, and exemplarily, the rotation speed of the P-GaN layer 63 and the GaN layer 62 is 900r / min, 1000r / min, 1100r / min or 1200r / min, but not limited to this.

[0050] In the present invention, the P-GaN layer 63 adopts a higher growth temperature than the multi-quantum well layer 4, which makes it easy to improve the quality of the crystal of the P-GaN layer 63, reduce leakage, and enhance the insulation protection effect of the BGaN / GaN superlattice structure. It also adopts a higher rotation speed than the multi-quantum well layer 4 to accelerate the growth and avoid damage to the InGaN well layer 42 due to long-term high temperature.

[0051] The growth atmosphere of the InGaN well layer 42 is N2. Since H2 is a by-product of the generation of InN, the H2 partial pressure will inhibit the production of InN. Therefore, the use of N2 as the growth atmosphere is conducive to the growth of the InGaN well layer 42.

[0052] Among them, the B component content in the BGaN pre-well protective layer 41 and the BGaN post-well protective layer 43 is 0.01~0.2, and exemplarily, the B component content is 0.01, 0.05, 0.1, 0.15, 0.18 or 0.2, but not limited to this. In the BGaN / GaN superlattice structure, the B component content is 0.01~0.2, and exemplarily, the B component content is 0.01, 0.05, 0.1, 0.15, 0.18 or 0.2, but not limited to this.

[0053] The doping concentration of N-type impurities in the N-GaN barrier layer 44 is 1*10 17 / cm 3 ~5*10 17 / cm 3 For example, the doping concentration of N-type impurities is 1*10 17 / cm 3 , 2*10 17 / cm 3 , 4*10 17 / cm 3 or 5*10 17 / cm 3 , but not limited to this.

[0054] The present invention also provides an epitaxial structure for an LED flip chip, which is prepared according to the above-mentioned preparation method.

[0055] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0056] Example 1

[0057] This embodiment discloses a method for preparing an epitaxial structure for an LED flip chip, comprising:

[0058] S10. Providing a substrate;

[0059] S20. epitaxially growing an epitaxial layer on the substrate;

[0060] The epitaxial layer includes a buffer layer, an N-type layer, a multi-quantum well layer, an electron blocking layer and a P-type layer which are sequentially deposited along the epitaxial direction;

[0061] The multi-quantum well layer includes a BGaN front-well protection layer, an InGaN well layer, a BGaN rear-well protection layer and an N-GaN barrier layer that are periodically and alternately grown;

[0062] The P-type layer includes an insulating protection layer and a P-GaN layer sequentially deposited along the epitaxial direction. The insulating protection layer is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities.

[0063] The specific steps of step S20 are as follows:

[0064] S100. Depositing a buffer layer on the epitaxial layer.

[0065] S200 . Depositing an N-type layer on the buffer layer.

[0066] S300. See Figure 2 As shown, a multi-quantum well layer is deposited on the N-type layer, as follows:

[0067] S310. Deposit a BGaN pre-well protective layer with a growth atmosphere of N2, a growth temperature of 800°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 0.5 nm, and a B component content of 0.15.

[0068] S320. Deposit an InGaN well layer on the BGaN front well protection layer, with a growth atmosphere of N2, a growth temperature of 780°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 3 nm, and an In component content of 0.2.

[0069] S330. Deposit a BGaN post-well protective layer on the InGaN well layer, with a growth atmosphere of N2, a growth temperature of 800°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 0.5 nm, and a B component content of 0.15.

[0070] S331. After the BGaN well rear protective layer is deposited, the BGaN well rear protective layer is treated with H2, with the H2 introduction time being 10s and the introduction flow rate being 10l / min.

[0071] S340. Deposit an N-GaN barrier layer on the BGaN well back protection layer in an N2 growth atmosphere, at a growth temperature of 870°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 7 nm, and an N-type impurity doping concentration of 3*10 17 / cm 3 .

[0072] S341. After the N-GaN barrier layer is deposited, the N-GaN barrier layer is treated with H2. The H2 introduction time is 10s and the introduction flow rate is 10l / min.

[0073] Among them, steps S310 to S341 are performed periodically, and the number of cycles is 5.

[0074] S400. Depositing an electron blocking layer on the multi-quantum well layer.

[0075] S500. See Figure 3 As shown, a P-type layer is deposited on the electron blocking layer as follows:

[0076] S510. Deposit an insulating protective layer, which is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities. The BGaN / GaN superlattice structure includes BGaN sublayers and GaN sublayers that are grown alternately and periodically. The number of periods is 6. The thickness of the BGaN sublayer in each period is 1.5 nm, and the thickness of the GaN sublayer is 4 nm. The growth temperature is 950°C, the rotation speed is 800 r / min, and the growth pressure is 200 Torr.

[0077] S520. Deposit a GaN layer on the insulating protective layer with a thickness of 60 nm, a growth temperature of 950° C., and a rotation speed of 1100 r / min.

[0078] S530. Deposit a P-GaN layer on the GaN layer with a thickness of 80 nm, a growth temperature of 950°C, a rotation speed of 1100 r / min, and a P-type impurity doping concentration of 1*10 19 / cm 3 .

[0079] Comparative Example 1

[0080] The difference between this comparative example and Example 1 is that the multi-quantum well layer does not include a BGaN pre-well protective layer and a BGaN post-well protective layer, and the steps of step S300 are as follows:

[0081] S320. Deposit an InGaN well layer with a growth atmosphere of N2, a growth temperature of 780°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 3 nm, and an In component content of 0.2.

[0082] S331. After the InGaN well layer is deposited, the InGaN well layer is treated with H2. The H2 introduction time is 10s and the introduction flow rate is 10l / min.

[0083] S340. Deposit an N-GaN barrier layer on the InGaN well layer in an N2 growth atmosphere, at a temperature of 870°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 7 nm, and an N-type impurity doping concentration of 3*10 17 / cm 3 .

[0084] S341. After the N-GaN barrier layer is deposited, the N-GaN barrier layer is treated with H2. The H2 introduction time is 10s and the introduction flow rate is 10l / min.

[0085] Among them, steps S310 to S341 are performed periodically, and the number of cycles is 5.

[0086] The P-type layer does not include an insulating protective layer. The steps of step S500 are as follows:

[0087] S520. Deposit a GaN layer on the electron blocking layer with a thickness of 60 nm, a growth temperature of 950° C., and a rotation speed of 1100 r / min.

[0088] S530. Deposit a P-GaN layer on the GaN layer with a thickness of 80 nm, a growth temperature of 950°C, a rotation speed of 1100 r / min, and a P-type impurity doping concentration of 1*10 19 / cm 3 .

[0089] Comparative Example 2

[0090] The difference between this comparative example and Example 1 is that the multi-quantum well layer does not include a BGaN pre-well protective layer and a BGaN post-well protective layer, and the steps of step S300 are as follows:

[0091] S320. Deposit an InGaN well layer with a growth atmosphere of N2, a growth temperature of 780°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 3 nm, and an In component content of 0.2.

[0092] S331. After the InGaN well layer is deposited, the InGaN well layer is treated with H2. The H2 introduction time is 10s and the introduction flow rate is 10l / min.

[0093] S340. Deposit an N-GaN barrier layer on the InGaN well layer in an N2 growth atmosphere, at a temperature of 870°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 7 nm, and an N-type impurity doping concentration of 3*10 17 / cm 3 .

[0094] S341. After the N-GaN barrier layer is deposited, the N-GaN barrier layer is treated with H2. The H2 introduction time is 10s and the introduction flow rate is 10l / min.

[0095] Among them, steps S310 to S341 are performed periodically, and the number of cycles is 5.

[0096] Comparative Example 3

[0097] The difference between this comparative example and Example 1 is that the P-type layer does not include an insulating protective layer, and the steps of step S500 are as follows:

[0098] S520. Deposit a GaN layer on the electron blocking layer with a thickness of 60 nm, a growth temperature of 950° C., and a rotation speed of 1100 r / min.

[0099] S530. Deposit a P-GaN layer on the GaN layer with a thickness of 80 nm, a growth temperature of 950°C, a rotation speed of 1100 r / min, and a P-type impurity doping concentration of 1*10 19 / cm 3 .

[0100] Comparative Example 4

[0101] The difference between this comparative example and Example 1 is that the multi-quantum well layer does not include a BGaN pre-well protection layer and a BGaN post-well protection layer.

[0102] Furthermore, after the BGaN rear well protective layer is deposited, the BGaN rear well protective layer is not subjected to H2 treatment; and after the N-GaN barrier layer is deposited, the N-GaN barrier layer is not subjected to H2 treatment.

[0103] The steps of step S300 are as follows:

[0104] S320. Deposit an InGaN well layer with a growth atmosphere of N2, a growth temperature of 780°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 3 nm, and an In component content of 0.2.

[0105] S340. Deposit an N-GaN barrier layer on the InGaN well layer in an N2 growth atmosphere, at a temperature of 870°C, a rotation speed of 600 r / min, a growth pressure of 150 Torr, a thickness of 7 nm, and an N-type impurity doping concentration of 3*10 17 / cm 3 .

[0106] Among them, steps S310 to S341 are performed periodically, and the number of cycles is 5.

[0107] Experiment 1: Uneven brightness and darkness test

[0108] The epitaxial structures prepared in Example 1 and Comparative Examples 1 to 4 were applied to LED flip chips, packaged in three-chip strings, and provided with a driving voltage of 7.2V to check the brightness.

[0109] The experimental results are as follows Figure 4 As shown, based on Figure 4 The brightness of each experimental group is ranked from 1 to 5, where 1 represents the best, the most uniform light emission, and 5 represents the worst, the worst light emission uniformity:

[0110]

[0111] Table 1 Test results of uneven brightness and darkness

[0112] Experiment 2: Turn on voltage test

[0113] The epitaxial structures prepared in Example 1 and Comparative Examples 1 to 4 were applied to an LED flip chip, and a driving current of 10 uA was provided to test the voltage value.

[0114] Experimental group Brightness Example 1 1 Comparative Example 1 5 Comparative Example 2 2 Comparative Example 3 3 Comparative Example 4 4

[0115] Table 1 Test results of uneven brightness and darkness

[0116] Experiment 2: Turn on voltage test

[0117] The epitaxial structures prepared in Example 1 and Comparative Examples 1 to 4 were applied to an LED flip chip, a driving current of 10 uA was provided, and the voltage value was tested.

[0118] The experimental results are shown in Table 2:

[0119] Experimental group Turn-on voltage Example 1 2.12 Comparative Example 1 2.04 Comparative Example 2 2.09 Comparative Example 3 2.07 Comparative Example 4 2.06

[0120] Table 2 Open circuit voltage test results

[0121] The embodiments described above are merely illustrative of the technical concepts and features of the present invention. The descriptions are relatively specific and detailed, and are intended to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. Therefore, they are not intended to limit the scope of the present invention. However, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art may make various modifications and improvements without departing from the spirit of the present invention. That is, any changes made in accordance with the spirit of the present invention should still fall within the scope of the present invention.

Claims

1. A method for preparing an epitaxial structure for an LED flip chip, characterized in that: include: providing a substrate; epitaxially growing an epitaxial layer on a substrate; The epitaxial layer includes a multi-quantum well layer and a P-type layer sequentially deposited along the epitaxial direction; The multi-quantum well layer includes a BGaN front-well protection layer, an InGaN well layer, a BGaN rear-well protection layer and an N-GaN barrier layer that are periodically and alternately grown in sequence; The P-type layer includes an insulating protective layer and a P-GaN layer sequentially deposited along the epitaxial direction. The insulating protective layer is a BGaN / GaN superlattice structure that is not intentionally doped with P-type impurities. The insulating protection layer can increase the series resistance when the current is less than 1 uA, thereby increasing the turn-on voltage of the LED flip chip under this current.

2. The method for preparing an epitaxial structure for an LED flip chip according to claim 1, wherein: include: After the BGaN well rear protective layer is deposited, the BGaN well rear protective layer is subjected to H2 treatment; After the N-GaN barrier layer is deposited, the N-GaN barrier layer is subjected to H2 treatment.

3. The method for preparing an epitaxial structure for an LED flip chip according to claim 2, wherein: During the H2 treatment, the H2 introduction time is 5 to 20 seconds, and the introduction flow rate is 10 to 20 l / min.

4. The method for preparing an epitaxial structure for an LED flip chip according to claim 1, wherein: A GaN layer is further provided between the insulating protection layer and the P-GaN layer.

5. The method for preparing an epitaxial structure for an LED flip chip according to claim 4, wherein: The BGaN / GaN superlattice structure includes BGaN sublayers and GaN sublayers that are grown alternately in a periodic manner, with the number of periods being 3 to 10. The thickness of the BGaN sublayer in each period is 1 to 2 nm, and the thickness of the GaN sublayer is 3 to 5 nm. The thickness of the P-GaN layer is 50 to 100 nm. The thickness of the GaN layer is 50 to 100 nm.

6. The method for preparing an epitaxial structure for an LED flip chip according to claim 1, wherein: The growth temperature of the InGaN well layer is 750-800°C, the growth temperature of the N-GaN barrier layer is 840-900°C, and the growth temperature of the BGaN well front protection layer and the BGaN well rear protection layer is 780-840°C.

7. The method for preparing an epitaxial structure for an LED flip chip according to claim 6, wherein: The rotation speed of the multi-quantum well layer is 500-700 r / min, the growth temperature of the P-type layer is 900-1000° C., the rotation speed of the BGaN / GaN superlattice structure is 700-1000 r / min, and the rotation speed of the P-GaN layer is 900-1200 r / min.

8. The method for preparing an epitaxial structure for an LED flip chip according to claim 1, wherein: The growth atmosphere of the InGaN well layer is N2.

9. The method for preparing an epitaxial structure for an LED flip chip according to claim 1, wherein: The B component content in the BGaN front-well protection layer and the BGaN rear-well protection layer is 0.01-0.2, and the B component content in the BGaN / GaN superlattice structure is 0.01-0.

2.

10. An epitaxial structure for LED flip chip, characterized in that: Prepared according to the preparation method according to any one of claims 1 to 9.

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