Capacitor and its manufacturing method and working method
By designing the connection method of multi-layer dielectric layer and conductive structure in MIM capacitors, the switching of multiple capacitance values of the capacitor is achieved, solving the problems of process complexity, cost and chip area waste in the prior art, and improving the flexibility of the capacitor and breakdown voltage.
Patent Information
- Application Number
- CN202310174138.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-23
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2043-02-23
AI Technical Summary
When existing MIM capacitors are manufactured with multiple capacitance values, they increase process complexity and cost, while also leading to waste of chip area, making it difficult to achieve flexibility of multiple capacitance values.
A capacitor is designed, including a substrate, multi-layer dielectric layer and conductive structure, and the switching of multiple capacitance values is achieved through the connection of different conductive structures, avoiding increasing process complexity and cost, while reducing waste of chip area.
The four variable capacitance values of the capacitor are realized, which avoids process complexity, cost improvement and chip area waste, meets the needs of multiple capacitance values, and increases the breakdown voltage.
Smart Images
Figure CN116207082B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a capacitor and a manufacturing method and a working method thereof. Background Art
[0002] Existing MIM (Metal Insulator Metal) capacitors are manufactured by stacking a metal layer-a dielectric layer-a metal layer. Since the structure of MIM capacitors is fixed, this type of capacitor has only one capacitance value. If MIM capacitors with multiple capacitance values are required, capacitors with different dielectric layer thicknesses need to be prepared. However, preparing dielectric layers with different thicknesses in the same film layer will increase the complexity of the process, increase costs, and cause a waste of chip area.
[0003] Therefore, how to prepare capacitors with various capacitance values while avoiding increasing process complexity, increasing costs, and wasting chip area is an issue that needs to be solved urgently. Summary of the invention
[0004] The object of the present invention is to provide a capacitor and a manufacturing method and a working method thereof, so that the capacitor has four variable capacitance values while avoiding increasing the complexity of the process, raising the cost and causing waste of chip area.
[0005] To achieve the above object, the present invention provides a capacitor, comprising:
[0006] A substrate having a first dielectric layer formed thereon, wherein a metal interconnection line is formed in the first dielectric layer;
[0007] A lower electrode plate, a second dielectric layer and an upper electrode plate are formed from bottom to top on a portion of the first dielectric layer, wherein the lower electrode plate and the second dielectric layer extend to the periphery of the upper electrode plate;
[0008] A first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to the upper electrode plate, the second conductive structure is electrically connected to the lower electrode plate outside the upper electrode plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower electrode plate.
[0009] Optionally, the capacitor further includes:
[0010] The third dielectric layer is formed on the upper electrode plate.
[0011] Optionally, the capacitor further includes:
[0012] A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
[0013] Optionally, the first conductive structure, the second conductive structure and the third conductive structure all include a conductive plug and a pad electrically connected to the conductive plug, and the pad is formed on the fourth dielectric layer; the conductive plug in the first conductive structure passes through the fourth dielectric layer and the third dielectric layer and is electrically connected to the upper electrode plate, the conductive plug in the second conductive structure passes through the fourth dielectric layer and the second dielectric layer at the periphery of the upper electrode plate and is electrically connected to the lower electrode plate, and the conductive plug in the third conductive structure passes through the fourth dielectric layer at the periphery of the lower electrode plate and a partial thickness of the first dielectric layer and is electrically connected to the metal interconnect line.
[0014] Optionally, the material of the upper electrode plate and the lower electrode plate includes metal and / or metal nitride.
[0015] The present invention also provides a method for manufacturing a capacitor, comprising:
[0016] Providing a substrate, on which a first dielectric layer is formed, and in which a metal interconnection line is formed;
[0017] Forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on a portion of the first dielectric layer, wherein the lower electrode plate and the second dielectric layer extend to the periphery of the upper electrode plate;
[0018] A first conductive structure, a second conductive structure and a third conductive structure are formed, wherein the first conductive structure is electrically connected to the upper electrode plate, the second conductive structure is electrically connected to the lower electrode plate outside the upper electrode plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower electrode plate.
[0019] Optionally, before forming the first conductive structure, the second conductive structure and the third conductive structure, the method for manufacturing the capacitor further includes:
[0020] forming a third dielectric layer on the upper plate;
[0021] A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
[0022] The present invention also provides a working method of a capacitor, the capacitor comprising: a first dielectric layer formed on a substrate, a metal interconnection line formed in the first dielectric layer; a lower electrode plate, a second dielectric layer and an upper electrode plate formed from bottom to top on a portion of the first dielectric layer, the lower electrode plate and the second dielectric layer extending to the periphery of the upper electrode plate; a first conductive structure, a second conductive structure and a third conductive structure, the first conductive structure being electrically connected to the upper electrode plate, the second conductive structure being electrically connected to the lower electrode plate at the periphery of the upper electrode plate, and the third conductive structure being electrically connected to the metal interconnection line at the periphery of the lower electrode plate; the working method of the capacitor comprises:
[0023] The first conductive structure and the second conductive structure are connected to the circuit so that the capacitor has a first capacitance value; the second conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a second capacitance value; the first conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a third capacitance value; the first conductive structure and the second conductive structure and the second conductive structure and the third conductive structure are connected to the circuit in parallel so that the capacitor has a fourth capacitance value.
[0024] Optionally, the capacitor further includes:
[0025] The third dielectric layer is formed on the upper electrode plate.
[0026] Optionally, the capacitor further includes:
[0027] A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
[0028] Optionally, the first conductive structure, the second conductive structure and the third conductive structure all include a conductive plug and a pad electrically connected to the conductive plug, and the pad is formed on the fourth dielectric layer; the conductive plug in the first conductive structure passes through the fourth dielectric layer and the third dielectric layer and is electrically connected to the upper electrode plate, the conductive plug in the second conductive structure passes through the fourth dielectric layer and the second dielectric layer at the periphery of the upper electrode plate and is electrically connected to the lower electrode plate, and the conductive plug in the third conductive structure passes through the fourth dielectric layer at the periphery of the lower electrode plate and a partial thickness of the first dielectric layer and is electrically connected to the metal interconnect line.
[0029] Optionally, the material of the upper electrode plate and the lower electrode plate includes metal and / or metal nitride.
[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0031] 1. The capacitor of the present invention comprises a first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to an upper plate, the second conductive structure is electrically connected to a lower plate outside the upper plate, and the third conductive structure is electrically connected to a metal interconnection line outside the lower plate, so that the capacitor has four variable capacitance values while avoiding increasing the complexity of the process, raising the cost and causing a waste of chip area.
[0032] 2. The manufacturing method of the capacitor of the present invention forms a first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to the upper plate, the second conductive structure is electrically connected to the lower plate outside the upper plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower plate, so that the capacitor has four variable capacitance values while avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area.
[0033] 3. The working method of the capacitor of the present invention is as follows: the first conductive structure and the second conductive structure are connected to the circuit so that the capacitor has a first capacitance value; the second conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a second capacitance value; the first conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a third capacitance value; the first conductive structure and the second conductive structure and the second conductive structure and the third conductive structure are connected to the circuit in parallel so that the capacitor has a fourth capacitance value, thereby making the capacitor have four variable capacitance values while avoiding increasing the complexity of the process, increasing the cost and causing waste of chip area. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a schematic structural diagram of a capacitor according to an embodiment of the present invention;
[0035] Figure 2 is a circuit connection diagram of a capacitor according to an embodiment of the present invention;
[0036] Figure 3 is a flow chart of a method for manufacturing a capacitor according to an embodiment of the present invention;
[0037] Figure 4a to Figure 4c yes Figure 3 A device schematic diagram of a capacitor manufacturing method is shown.
[0038] Among them, Figure 1 to Figure 4c The reference numerals are described as follows:
[0039] 11-metal interconnection line; 12-first dielectric layer; 13-lower electrode; 131-lower electrode material layer; 14-second dielectric layer; 141-second dielectric material layer; 15-upper electrode; 151-upper electrode material layer; 16-third dielectric layer; 161-third dielectric material layer; 17-fourth dielectric layer; 181-first conductive plug; 182-second conductive plug; 183-third conductive plug; 191-first pad; 192-second pad; 193-third pad. DETAILED DESCRIPTION
[0040] In order to make the purpose, advantages and features of the present invention more clear, the capacitor and its manufacturing method and working method proposed in the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0041] An embodiment of the present invention provides a capacitor, comprising: a substrate, a first dielectric layer formed on the substrate, and a metal interconnection line formed in the first dielectric layer; a lower electrode plate, a second dielectric layer, and an upper electrode plate formed from bottom to top on a portion of the first dielectric layer, the lower electrode plate and the second dielectric layer extending to the periphery of the upper electrode plate; a first conductive structure, a second conductive structure, and a third conductive structure, the first conductive structure being electrically connected to the upper electrode plate, the second conductive structure being electrically connected to the lower electrode plate at the periphery of the upper electrode plate, and the third conductive structure being electrically connected to the metal interconnection line at the periphery of the lower electrode plate.
[0042] See below Figure 1-2 The capacitor provided by this embodiment is described in detail.
[0043] A first dielectric layer 12 is formed on the substrate, and a metal interconnection line 11 is formed in the first dielectric layer 12 .
[0044] It should be noted that the first dielectric layer 12 is a multi-layer stacked structure. Figure 4a to Figure 4c Only a portion of the first dielectric layer 12 covering the metal interconnection line 11 is shown schematically; in addition, a conductive plug or other structure electrically connected to the metal interconnection line 11 may also be formed in the first dielectric layer 12 .
[0045] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.
[0046] A lower electrode plate 13 , a second dielectric layer 14 and an upper electrode plate 15 are formed on a portion of the first dielectric layer 12 from bottom to top, and the lower electrode plate 13 and the second dielectric layer 14 extend to the periphery of the upper electrode plate 15 .
[0047] The material of the upper plate 15 and the lower plate 13 may include metal or metal nitride, or may include both metal and metal nitride, such as metal or metal compound with metallic properties such as aluminum, copper, tantalum, tantalum nitride, titanium, titanium nitride or tungsten. In this case, the capacitor is a MIM capacitor; or, the material of the upper plate 15 and / or the lower plate 13 may be polysilicon. In this case, the capacitor is a PIP capacitor or a PIM capacitor.
[0048] The material of the second dielectric layer 14 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the second dielectric layer 14 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).
[0049] The capacitor further includes a third dielectric layer 16 formed on the upper plate 15 .
[0050] The capacitor further includes: a fourth dielectric layer 17 formed on the first dielectric layer 12 , and the fourth dielectric layer 17 covers the third dielectric layer 16 , the upper electrode plate 15 , the second dielectric layer 14 and the lower electrode plate 13 .
[0051] The material of the first dielectric layer 12 , the third dielectric layer 16 and the fourth dielectric layer 17 may be at least one of silicon oxide, silicon oxynitride, silicon nitride and ONO (silicon oxide-silicon nitride-silicon oxide).
[0052] Preferably, the thickness of the first dielectric layer 12 covering the metal interconnection line 11 is The thickness of the lower plate 13 is The thickness of the second dielectric layer 14 is The thickness of the upper plate 15 is The thickness of the third dielectric layer 16 is
[0053] The first conductive structure is electrically connected to the upper electrode plate 15 , the second conductive structure is electrically connected to the lower electrode plate 13 outside the upper electrode plate 15 , and the third conductive structure is electrically connected to the metal interconnection line 11 outside the lower electrode plate 13 .
[0054] like Figure 1As shown, the first conductive structure includes a first conductive plug 181 and a first pad 191 electrically connected to the first conductive plug 181, the second conductive structure includes a second conductive plug 182 and a second pad 192 electrically connected to the second conductive plug 182, the third conductive structure includes a third conductive plug 183 and a third pad 193 electrically connected to the third conductive plug 183, the first pad 191, the second pad 192 and the third pad 193 are all formed on the fourth dielectric layer 17; the first conductive plug 181 penetrates the fourth dielectric layer 17 and the third dielectric layer 16 and is electrically connected to the upper electrode plate 15, the second conductive plug 182 penetrates the fourth dielectric layer 17 and the second dielectric layer 14 at the periphery of the upper electrode plate 15 and is electrically connected to the lower electrode plate 13, and the third conductive plug 183 penetrates the fourth dielectric layer 17 at the periphery of the lower electrode plate 13 and a partial thickness of the first dielectric layer 12 and is electrically connected to the metal interconnection line 11.
[0055] When the first conductive structure and the second conductive structure are connected to the circuit, that is, when the upper electrode plate 15 and the lower electrode plate 13 are connected to the circuit through the first pad 191 and the second pad 192, the corresponding Figure 2 The first single-pole double-throw switch S1 shown in the figure is connected to the position L2 and the third single-pole double-throw switch S3 is connected to the position L6, so that the first capacitor C1 composed of the upper plate 15, the second dielectric layer 14 and the lower plate 13 is connected to the circuit, so that the capacitor has a first capacitance value. At this time, the second single-pole double-throw switch S2 is connected to the position L3 or is not connected to any position; when the second conductive structure and the third conductive structure are connected to the circuit, that is, when the lower plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, the corresponding Figure 2 The first single-pole double-throw switch S1 shown in the figure is connected to position L1 and the second single-pole double-throw switch S2 is connected to position L3, so that the second capacitor C2 composed of the lower plate 13, the first dielectric layer 12 and the metal interconnection line 11 is connected to the circuit, so that the capacitor has a second capacitance value. At this time, the third single-pole double-throw switch S3 is connected to position L5 or position L6 or is not connected to any position; when the first conductive structure and the third conductive structure are connected to the circuit, that is, when the upper plate 15 and the metal interconnection line 11 are connected to the circuit through the first pad 191 and the third pad 193, the corresponding Figure 2The first single-pole double-throw switch S1 shown in the figure is connected to position L2 and the third single-pole double-throw switch S3 is connected to position L5, so that the first capacitor C1 and the second capacitor C2 are connected in series to the circuit, so that the capacitor has a third capacitance value. At this time, the second single-pole double-throw switch S2 is connected to position L3 or is not connected to any position; when the first conductive structure and the second conductive structure and the second conductive structure and the third conductive structure are connected in parallel to the circuit, that is, the upper plate 15 and the lower plate 13 are connected to the circuit through the first pad 191 and the second pad 192, and the lower plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, and the two are connected in parallel, corresponding Figure 2 The first single-pole double-throw switch S1 is connected to position L2, the second single-pole double-throw switch S2 is connected to position L4, and the third single-pole double-throw switch S3 is connected to position L6, so that the first capacitor C1 and the second capacitor C2 are connected in parallel to the circuit, so that the capacitor has a fourth capacitance value.
[0056] Therefore, the present invention, on the basis of electrically leading out the upper electrode plate 15 and the lower electrode plate 13, electrically leads out the metal interconnection line 11, and uses a single-pole double-throw switch to switch at least two of the first pad 191, the second pad 192 and the third pad 193 to connect to an external circuit, thereby realizing switching of four capacitance values, so that the capacitor has four different capacitance values to meet customer needs for different capacitance values.
[0057] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor of the present invention only needs to add the metal interconnection line 11 to electrically lead out and switch the pads connected to the external circuit to achieve the capacitor having four variable capacitance values, thereby avoiding increasing the complexity of the process, raising the cost and causing waste of chip area.
[0058] Moreover, for the capacitor with the third capacitance value, the thickness of its dielectric layer is the sum of the thicknesses of the second dielectric layer 14 and the first dielectric layer 12, so that the breakdown voltage of the capacitor with the third capacitance value is greater than the breakdown voltages of the capacitors with the first capacitance value and the second capacitance value.
[0059] In summary, the present invention provides a capacitor, comprising: a substrate, a first dielectric layer formed on the substrate, a metal interconnection line formed in the first dielectric layer; a lower plate, a second dielectric layer and an upper plate formed from bottom to top on a portion of the first dielectric layer, the lower plate and the second dielectric layer extending to the periphery of the upper plate; a first conductive structure, a second conductive structure and a third conductive structure, the first conductive structure being electrically connected to the upper plate, the second conductive structure being electrically connected to the lower plate at the periphery of the upper plate, and the third conductive structure being electrically connected to the metal interconnection line at the periphery of the lower plate. The capacitor provided by the present invention enables the capacitor to have four variable capacitance values while avoiding increasing the complexity of the process, increasing costs and causing waste of chip area.
[0060] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a capacitor, referring to Figure 3 ,from Figure 3 It can be seen that the manufacturing method of the capacitor includes:
[0061] Step S1, providing a substrate, on which a first dielectric layer is formed, and in which a metal interconnection line is formed;
[0062] Step S2, forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on a portion of the first dielectric layer, wherein the lower electrode plate and the second dielectric layer extend to the periphery of the upper electrode plate;
[0063] Step S3, forming a first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to the upper electrode plate, the second conductive structure is electrically connected to the lower electrode plate outside the upper electrode plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower electrode plate.
[0064] See below Figure 2 , Figure 4a to Figure 4c The method for manufacturing the capacitor provided in this embodiment is described in detail.
[0065] According to step S1 , a substrate (not shown) is provided, on which a first dielectric layer 12 is formed, and in which a metal interconnection line 11 is formed.
[0066] It should be noted that the first dielectric layer 12 is a multi-layer stacked structure. Figure 4a to Figure 4c Only a portion of the first dielectric layer 12 covering the metal interconnection line 11 is shown schematically; in addition, a conductive plug or other structure electrically connected to the metal interconnection line 11 may also be formed in the first dielectric layer 12 .
[0067] The material of the substrate can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.
[0068] According to step S2 , a lower plate 13 , a second dielectric layer 14 and an upper plate 15 are formed from bottom to top on a portion of the first dielectric layer 12 , and the lower plate 13 and the second dielectric layer 14 extend to the periphery of the upper plate 15 .
[0069] The material of the upper plate 15 and the lower plate 13 may include metal or metal nitride, or may include both metal and metal nitride, such as metal or metal compound with metallic properties such as aluminum, copper, tantalum, tantalum nitride, titanium, titanium nitride or tungsten. In this case, the capacitor is a MIM capacitor; or, the material of the upper plate 15 and / or the lower plate 13 may be polysilicon. In this case, the capacitor is a PIP capacitor or a PIM capacitor.
[0070] The material of the second dielectric layer 14 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the second dielectric layer 14 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).
[0071] Before subsequently forming the first conductive structure, the second conductive structure and the third conductive structure, the method for manufacturing the capacitor may further include: forming a third dielectric layer 16 on the upper electrode plate 15 .
[0072] The steps of forming the lower plate 13, the second dielectric layer 14, the upper plate 15 and the third dielectric layer 16 may include: first, Figure 4a As shown, a lower plate material layer 131, a second dielectric material layer 141, an upper plate material layer 151 and a third dielectric material layer 161 are sequentially formed to cover the first dielectric layer 12; then, as shown Figure 4b As shown, a portion of the third dielectric material layer 161 and a portion of the upper plate material layer 151 are sequentially etched away to expose the second dielectric material layer 141, and the remaining third dielectric material layer 161 is used as the third dielectric layer 16, and the remaining upper plate material layer 151 is used as the upper plate 15; then, as shown Figure 4bAs shown, the partially exposed second dielectric material layer 141 and the lower electrode material layer 131 are etched away in sequence to expose the first dielectric layer 12, and the remaining second dielectric material layer 141 serves as the second dielectric layer 14, and the remaining lower electrode material layer 131 serves as the lower electrode 13, and the metal layer 13 and the second dielectric layer 14 extend to the periphery of the upper electrode 15.
[0073] Before forming the first conductive structure, the second conductive structure and the third conductive structure, the method for manufacturing the capacitor may further include: Figure 4c As shown, a fourth dielectric layer 17 is formed on the first dielectric layer 12 , and the fourth dielectric layer 17 covers the third dielectric layer 16 , the upper electrode plate 15 , the second dielectric layer 14 and the lower electrode plate 13 .
[0074] The material of the first dielectric layer 12 , the third dielectric layer 16 and the fourth dielectric layer 17 may be at least one of silicon oxide, silicon oxynitride, silicon nitride and ONO (silicon oxide-silicon nitride-silicon oxide).
[0075] Preferably, the thickness of the portion of the first dielectric layer 12 covering the metal interconnection line 11 is The thickness of the lower plate 13 is The thickness of the second dielectric layer 14 is The thickness of the upper plate 15 is The thickness of the third dielectric layer 16 is
[0076] According to step S3, a first conductive structure, a second conductive structure and a third conductive structure are formed, wherein the first conductive structure is electrically connected to the upper electrode plate 15, the second conductive structure is electrically connected to the lower electrode plate 13 outside the upper electrode plate 15, and the third conductive structure is electrically connected to the metal interconnection line 11 outside the lower electrode plate 13.
[0077] like Figure 4cAs shown, the first conductive structure includes a first conductive plug 181 and a first pad 191 electrically connected to the first conductive plug 181, the second conductive structure includes a second conductive plug 182 and a second pad 192 electrically connected to the second conductive plug 182, the third conductive structure includes a third conductive plug 183 and a third pad 193 electrically connected to the third conductive plug 183, the first pad 191, the second pad 192 and the third pad 193 are all formed on the fourth dielectric layer 17; the first conductive plug 181 penetrates the fourth dielectric layer 17 and the third dielectric layer 16 and is electrically connected to the upper electrode plate 15, the second conductive plug 182 penetrates the fourth dielectric layer 17 and the second dielectric layer 14 at the periphery of the upper electrode plate 15 and is electrically connected to the lower electrode plate 13, and the third conductive plug 183 penetrates the fourth dielectric layer 17 at the periphery of the lower electrode plate 13 and a partial thickness of the first dielectric layer 12 and is electrically connected to the metal interconnection line 11.
[0078] When the first conductive structure and the second conductive structure are connected to the circuit, that is, when the upper electrode plate 15 and the lower electrode plate 13 are connected to the circuit through the first pad 191 and the second pad 192, the corresponding Figure 2 The first single-pole double-throw switch S1 shown in the figure is connected to the position L2 and the third single-pole double-throw switch S3 is connected to the position L6, so that the first capacitor C1 composed of the upper plate 15, the second dielectric layer 14 and the lower plate 13 is connected to the circuit, so that the capacitor has a first capacitance value. At this time, the second single-pole double-throw switch S2 is connected to the position L3 or is not connected to any position; when the second conductive structure and the third conductive structure are connected to the circuit, that is, when the lower plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, the corresponding Figure 2 The first single-pole double-throw switch S1 shown in the figure is connected to position L1 and the second single-pole double-throw switch S2 is connected to position L3, so that the second capacitor C2 composed of the lower plate 13, the first dielectric layer 12 and the metal interconnection line 11 is connected to the circuit, so that the capacitor has a second capacitance value. At this time, the third single-pole double-throw switch S3 is connected to position L5 or position L6 or is not connected to any position; when the first conductive structure and the third conductive structure are connected to the circuit, that is, when the upper plate 15 and the metal interconnection line 11 are connected to the circuit through the first pad 191 and the third pad 193, the corresponding Figure 2The first single-pole double-throw switch S1 shown in the figure is connected to position L2 and the third single-pole double-throw switch S3 is connected to position L5, so that the first capacitor C1 and the second capacitor C2 are connected in series to the circuit, so that the capacitor has a third capacitance value. At this time, the second single-pole double-throw switch S2 is connected to position L3 or is not connected to any position; when the first conductive structure and the second conductive structure and the second conductive structure and the third conductive structure are connected in parallel to the circuit, that is, the upper plate 15 and the lower plate 13 are connected to the circuit through the first pad 191 and the second pad 192, and the lower plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, and the two are connected in parallel, corresponding Figure 2 The first single-pole double-throw switch S1 is connected to position L2, the second single-pole double-throw switch S2 is connected to position L4, and the third single-pole double-throw switch S3 is connected to position L6, so that the first capacitor C1 and the second capacitor C2 are connected in parallel to the circuit, so that the capacitor has a fourth capacitance value.
[0079] Therefore, the present invention, on the basis of electrically leading out the upper electrode plate 15 and the lower electrode plate 13, electrically leads out the metal interconnection line 11, and uses a single-pole double-throw switch to switch at least two of the first pad 191, the second pad 192 and the third pad 193 to connect to an external circuit, thereby realizing switching of four capacitance values, so that the capacitor has four different capacitance values to meet customer needs for different capacitance values.
[0080] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor manufacturing method of the present invention only needs to add the metal interconnection line 11 to electrically lead out and switch the pads connected to the external circuit to achieve the capacitor having four variable capacitance values, thereby avoiding increasing the complexity of the process, raising costs and causing waste of chip area.
[0081] Moreover, for the capacitor with the third capacitance value, the thickness of its dielectric layer is the sum of the thicknesses of the second dielectric layer 14 and the first dielectric layer 12, so that the breakdown voltage of the capacitor with the third capacitance value is greater than the breakdown voltages of the capacitors with the first capacitance value and the second capacitance value.
[0082] In summary, the present invention provides a method for manufacturing a capacitor, comprising: providing a substrate, a first dielectric layer formed on the substrate, and metal interconnects formed in the first dielectric layer; forming a lower plate, a second dielectric layer, and an upper plate from bottom to top on part of the first dielectric layer, the lower plate and the second dielectric layer extending to the periphery of the upper plate; forming a first conductive structure, a second conductive structure, and a third conductive structure, the first conductive structure being electrically connected to the upper plate, the second conductive structure being electrically connected to the lower plate at the periphery of the upper plate, and the third conductive structure being electrically connected to the metal interconnects at the periphery of the lower plate. The method for manufacturing a capacitor provided by the present invention allows the capacitor to have four variable capacitance values while avoiding increasing the complexity of the process, increasing costs, and causing waste of chip area.
[0083] Based on the same inventive concept, an embodiment of the present invention provides a working method of a capacitor, the capacitor comprising: a first dielectric layer formed on a substrate, a metal interconnection line formed in the first dielectric layer; a lower electrode plate, a second dielectric layer and an upper electrode plate formed from bottom to top on a portion of the first dielectric layer, the lower electrode plate and the second dielectric layer extending to the periphery of the upper electrode plate; a first conductive structure, a second conductive structure and a third conductive structure, the first conductive structure being electrically connected to the upper electrode plate, the second conductive structure being electrically connected to the lower electrode plate at the periphery of the upper electrode plate, and the third conductive structure being electrically connected to the metal interconnection line at the periphery of the lower electrode plate.
[0084] The specific structure of the capacitor is shown in the above description and will not be repeated here.
[0085] See also Figure 1 and Figure 2 , the working method of the capacitor includes:
[0086] When the first conductive structure and the second conductive structure are connected to the circuit, that is, the upper electrode plate 15 and the lower electrode plate 13 are connected to the circuit through the first pad 191 and the second pad 192, the corresponding Figure 2 The first single-pole double-throw switch S1 shown in FIG. 1 is connected to the position L2 and the third single-pole double-throw switch S3 is connected to the position L6, so that the first capacitor C1 composed of the upper plate 15, the second dielectric layer 14 and the lower plate 13 is connected to the circuit, so that the capacitor has a first capacitance value. At this time, the second single-pole double-throw switch S2 is connected to the position L3 or is not connected to any position;
[0087] When the second conductive structure and the third conductive structure are connected to the circuit, that is, the lower electrode plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, the corresponding Figure 2The first single-pole double-throw switch S1 shown in FIG. 1 is connected to position L1 and the second single-pole double-throw switch S2 is connected to position L3, so that the second capacitor C2 composed of the lower plate 13, the first dielectric layer 12 and the metal interconnection line 11 is connected to the circuit, so that the capacitor has a second capacitance value. At this time, the third single-pole double-throw switch S3 is connected to position L5 or position L6 or is not connected to any position;
[0088] When the first conductive structure and the third conductive structure are connected to the circuit, that is, the upper plate 15 and the metal interconnection line 11 are connected to the circuit through the first pad 191 and the third pad 193, Figure 2 As shown in the figure, the first single-pole double-throw switch S1 is connected to the position L2 and the third single-pole double-throw switch S3 is connected to the position L5, so that the first capacitor C1 and the second capacitor C2 are connected in series to the circuit, so that the capacitor has a third capacitance value, at this time, the second single-pole double-throw switch S2 is connected to the position L3 or is not connected to any position;
[0089] The first conductive structure and the second conductive structure as well as the second conductive structure and the third conductive structure are connected in parallel to the circuit, that is, the upper plate 15 and the lower plate 13 are connected to the circuit through the first pad 191 and the second pad 192, and the lower plate 13 and the metal interconnection line 11 are connected to the circuit through the second pad 192 and the third pad 193, and when the two are connected in parallel, the corresponding Figure 2 The first single-pole double-throw switch S1 is connected to position L2, the second single-pole double-throw switch S2 is connected to position L4, and the third single-pole double-throw switch S3 is connected to position L6, so that the first capacitor C1 and the second capacitor C2 are connected in parallel to the circuit, so that the capacitor has a fourth capacitance value.
[0090] Therefore, the present invention, on the basis of electrically leading out the upper electrode plate 15 and the lower electrode plate 13, electrically leads out the metal interconnection line 11, and uses a single-pole double-throw switch to switch at least two of the first pad 191, the second pad 192 and the third pad 193 to connect to an external circuit, thereby realizing switching of four capacitance values, so that the capacitor has four different capacitance values to meet customer needs for different capacitance values.
[0091] Furthermore, compared with the existing method of preparing capacitors with different dielectric layer thicknesses to make the capacitors have multiple capacitance values, the capacitor of the present invention only needs to add the metal interconnection line 11 to electrically lead out and switch the pads connected to the external circuit to achieve the capacitor having four variable capacitance values, thereby avoiding increasing the complexity of the process, raising the cost and causing waste of chip area.
[0092] Moreover, for the capacitor with the third capacitance value, the thickness of its dielectric layer is the sum of the thicknesses of the second dielectric layer 14 and the first dielectric layer 12, so that the breakdown voltage of the capacitor with the third capacitance value is greater than the breakdown voltages of the capacitors with the first capacitance value and the second capacitance value.
[0093] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A capacitor, characterized in that: include: A substrate having a first dielectric layer formed thereon, wherein a metal interconnection line is formed in the first dielectric layer; A lower plate, a second dielectric layer and an upper plate are formed from bottom to top on a portion of the first dielectric layer, the lower plate and the second dielectric layer extend to the periphery of the upper plate, and the metal interconnection line extends from below the upper plate to the periphery of the lower plate; A first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to the upper electrode plate, the second conductive structure is electrically connected to the lower electrode plate outside the upper electrode plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower electrode plate.
2. The capacitor according to claim 1, wherein: The capacitor further comprises: The third dielectric layer is formed on the upper electrode plate.
3. The capacitor according to claim 2, characterized in that The capacitor further comprises: A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
4. The capacitor according to claim 3, characterized in that The first conductive structure, the second conductive structure and the third conductive structure all include a conductive plug and a pad electrically connected to the conductive plug, and the pad is formed on the fourth dielectric layer; the conductive plug in the first conductive structure penetrates the fourth dielectric layer and the third dielectric layer and is electrically connected to the upper electrode plate, the conductive plug in the second conductive structure penetrates the fourth dielectric layer and the second dielectric layer at the periphery of the upper electrode plate and is electrically connected to the lower electrode plate, and the conductive plug in the third conductive structure penetrates the fourth dielectric layer at the periphery of the lower electrode plate and a partial thickness of the first dielectric layer and is electrically connected to the metal interconnection line.
5. The capacitor according to claim 1, wherein: The material of the upper electrode plate and the lower electrode plate includes metal and / or metal nitride.
6. A method for manufacturing a capacitor, characterized in that: include: Providing a substrate, on which a first dielectric layer is formed, and in which a metal interconnection line is formed; A lower plate, a second dielectric layer and an upper plate are formed from bottom to top on a portion of the first dielectric layer, wherein the lower plate and the second dielectric layer extend to the periphery of the upper plate, and the metal interconnection line extends from below the upper plate to the periphery of the lower plate; A first conductive structure, a second conductive structure and a third conductive structure are formed, wherein the first conductive structure is electrically connected to the upper electrode plate, the second conductive structure is electrically connected to the lower electrode plate outside the upper electrode plate, and the third conductive structure is electrically connected to the metal interconnection line outside the lower electrode plate.
7. The method for manufacturing a capacitor according to claim 6, wherein: Before forming the first conductive structure, the second conductive structure and the third conductive structure, the method for manufacturing the capacitor further includes: forming a third dielectric layer on the upper plate; A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
8. A method for operating a capacitor, characterized in that: The capacitor comprises: a first dielectric layer formed on a substrate, wherein a metal interconnection line is formed in the first dielectric layer; a lower plate, a second dielectric layer and an upper plate formed from bottom to top on a portion of the first dielectric layer, wherein the lower plate and the second dielectric layer extend to the periphery of the upper plate, and the metal interconnection line extends from below the upper plate to the periphery of the lower plate; a first conductive structure, a second conductive structure and a third conductive structure, wherein the first conductive structure is electrically connected to the upper plate, the second conductive structure is electrically connected to the lower plate at the periphery of the upper plate, and the third conductive structure is electrically connected to the metal interconnection line at the periphery of the lower plate; and the working method of the capacitor comprises: The first conductive structure and the second conductive structure are connected to the circuit so that the capacitor has a first capacitance value; the second conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a second capacitance value; the first conductive structure and the third conductive structure are connected to the circuit so that the capacitor has a third capacitance value; the first conductive structure and the second conductive structure and the second conductive structure and the third conductive structure are connected to the circuit in parallel so that the capacitor has a fourth capacitance value.
9. The capacitor operating method according to claim 8, characterized in that: The capacitor further comprises: The third dielectric layer is formed on the upper electrode plate.
10. The capacitor operating method according to claim 9, characterized in that: The capacitor further comprises: A fourth dielectric layer is formed on the first dielectric layer, and the fourth dielectric layer covers the third dielectric layer, the upper electrode plate, the second dielectric layer and the lower electrode plate.
11. The capacitor operating method according to claim 10, characterized in that: The first conductive structure, the second conductive structure and the third conductive structure all include a conductive plug and a pad electrically connected to the conductive plug, and the pad is formed on the fourth dielectric layer; the conductive plug in the first conductive structure penetrates the fourth dielectric layer and the third dielectric layer and is electrically connected to the upper electrode plate, the conductive plug in the second conductive structure penetrates the fourth dielectric layer and the second dielectric layer at the periphery of the upper electrode plate and is electrically connected to the lower electrode plate, and the conductive plug in the third conductive structure penetrates the fourth dielectric layer at the periphery of the lower electrode plate and a partial thickness of the first dielectric layer and is electrically connected to the metal interconnection line.
12. The capacitor operating method according to claim 8, characterized in that: The material of the upper electrode plate and the lower electrode plate includes metal and / or metal nitride.