Semiconductor device and method of manufacturing the same

Abstract

The length of the unit portion (2) in one direction is set to the length of the second impurity region (14) in one direction, and the second impurity region is provided so as to extend from the unit portion (1) to the outer peripheral portion (2) with the contact region (14b). Furthermore, the length of the portion of the second impurity region contact region (14b) that extends to the outer peripheral portion (2) in one direction is set to the protruding length d, the length of the second impurity region (14) in one direction is set to the second impurity region length A, and the ratio of the protruding length d to the second impurity region length A, that is, d / A, is 0.1 or less.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-142629, filed on August 26, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device having a trench gate structure with dual gates and a method of manufacturing the same. Background Technology

[0004] Previously, techniques have been proposed for semiconductor devices having a cell portion and an outer peripheral portion, and forming a trench gate structure with dual gates in the cell portion (see, for example, Patent Document 1). Specifically, such a semiconductor device utilizes n + An n-type drain layer is formed on top of the drain layer. - The device is constructed using a semiconductor substrate with a drift layer. A body region and a source region are formed on the surface of the semiconductor substrate. Furthermore, a trench gate structure is formed in the semiconductor substrate such that the body region and the source region are connected to reach the drift layer. This trench gate structure in the semiconductor device has dual gates. A shielding electrode, set to the source potential, is disposed at the bottom side of the gate trench, separated by a shielding insulating film, and a gate electrode is disposed at the opening side of the gate trench, separated by a gate insulating film. This reduces the parasitic capacitance generated between the gate electrode and the drain electrode. Additionally, an intermediate insulating film is formed between the shielding electrode and the gate electrode.

[0005] Furthermore, an upper electrode electrically connected to the bulk region and the source region is disposed in the semiconductor substrate, and a lower electrode electrically connected to the drain layer is disposed therein.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2013-201361 Summary of the Invention

[0009] Furthermore, in semiconductor devices like those described above, it is known to form a structure in which a contact trench is formed in a semiconductor substrate, and the upper electrode is electrically connected to the body region and the source region via the contact trench.

[0010] In this case, by forming a source region contact area with a higher impurity concentration than the source region along the contact trench, the contact resistance between the upper electrode and the semiconductor substrate can be reduced. Furthermore, the source region contact area is formed around the contact trench, for example, using the same mask as the one used to form the contact trench.

[0011] Furthermore, in such semiconductor devices, parasitic bipolar transistors may operate due to avalanche action. Therefore, by extending the contact trench from the cell portion to the outer periphery when forming a contact trench, the operation of parasitic bipolar transistors formed within the semiconductor device can be suppressed, thereby improving avalanche tolerance.

[0012] Furthermore, in such a semiconductor device, the unit section can be configured to have a main unit region and a sensing unit region having the same structure as the main unit region but with a current flowing through it that is less than the current flowing through the main unit region. Moreover, in the semiconductor device, it is possible to detect the current flowing through the main unit region based on the current flowing through the sensing unit region.

[0013] However, when using a structure that forms contact trenches in a semiconductor substrate and has a cell portion with a main cell region and a sensing cell region, the accuracy of current detection may decrease. Specifically, there are cases where the contact trench extends excessively from the cell portion to the outer periphery, resulting in an excessively long protrusion of the source region from the contact region. In this case, the ratio of current flowing through the outer periphery increases in the sensing cell region, thereby reducing the ratio of current flowing through the sensing cell region. Therefore, the accuracy of current detection may decrease.

[0014] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, which can suppress the decrease in the detection accuracy of current.

[0015] According to one aspect of this disclosure, a semiconductor device having a semiconductor element with a trench gate structure having dual gates includes a cell portion having a semiconductor element and an outer periphery surrounding the cell portion. The cell portion has a main cell region and a sensing cell region having the same structure as the main cell region, through which a current flows less than that flowing through the main cell region. The main cell region and the sensing cell region include: a semiconductor substrate having a drift layer of a first conductivity type; a first impurity region of a second conductivity type formed on the drift layer; a surface portion of the first impurity region formed in the first impurity region with a higher impurity concentration than the drift layer; a plurality of trench gate structures having dual gates, in which shielding electrodes, intermediate insulating films, and gate electrodes are sequentially stacked with an insulating film in a strip-shaped arrangement of multiple gate trenches that extend from the cell portion to the outer periphery in a length direction and extend through the second impurity region to the drift layer; and a second impurity region formed between the trench gate structures, extending from the cell portion to the outer periphery in a length direction and extending through the second impurity region to the drift layer. The system comprises: a contact trench for the impurity region; a contact area for the second impurity region formed along the wall of the contact trench and having a higher impurity concentration than the second impurity region; a high-concentration layer of first or second conductivity type formed on the opposite side of the first impurity region through a drift layer and having a higher impurity concentration than the drift layer; an interlayer insulating film disposed on the trench gate structure, the first impurity region, and the second impurity region and having contact holes connected to the contact trench; a first electrode electrically connected to the contact area for the second impurity region and the first impurity region via contact holes and contact trenches; and a second electrode electrically connected to the high-concentration layer. The length of the unit portion along one direction is set to the length of the second impurity region along one direction. The contact area for the second impurity region extends from the unit portion to the outer periphery. The length along one direction of the portion of the contact area for the second impurity region extending to the outer periphery is defined as the protrusion length d. The length along one direction of the second impurity region is defined as the length A of the second impurity region. The ratio of the protrusion length d to the length A of the second impurity region, i.e., d / A, is 0.1 or less.

[0016] This allows for an increase in avalanche tolerance and a reduction in the deviation in the ratio of current flowing through the main unit region and the sensing unit region. Consequently, it enables an increase in avalanche tolerance and suppresses the decrease in current detection accuracy.

[0017] Furthermore, according to other aspects of this disclosure, in the above-described semiconductor device manufacturing method, the following steps are performed: preparing a semiconductor substrate; forming a contact region for a second impurity region; and forming a contact trench in the semiconductor substrate; in the step of forming the contact region for the second impurity region, the ratio of the protrusion length d to the length A of the second impurity region, i.e., d / A, is 0.1 or less.

[0018] This enables the manufacture of semiconductor devices that improve avalanche tolerance and suppress the decline in current detection accuracy.

[0019] In addition, the parenthesized reference numerals attached to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent element described in the embodiments described later. Attached Figure Description

[0020] Figure 1 This is a schematic diagram showing the overall structure of the semiconductor device according to the first embodiment.

[0021] Figure 2 This is a layout diagram of the upper surface of the semiconductor device according to the first embodiment.

[0022] Figure 3 It is along Figure 2 A cross-sectional view of line III-III in the diagram.

[0023] Figure 4 It is along Figure 2 A cross-sectional view of line IV-IV in the image.

[0024] Figure 5 This is a three-dimensional schematic diagram of the semiconductor device according to the first embodiment.

[0025] Figure 6 This is a schematic diagram showing the current path when a semiconductor device is in the on state.

[0026] Figure 7 This is a graph showing the simulation results of the relationship between the protrusion length and the deviation of the ratio of the current flowing through the main unit region and the sensing unit region.

[0027] Figure 8A This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0028] Figure 8B It means to continue Figure 8A A cross-sectional view of the manufacturing process of a semiconductor device.

[0029] Figure 8C It means to continue Figure 8B A cross-sectional view of the manufacturing process of a semiconductor device.

[0030] Figure 8D It means to continue Figure 8C A cross-sectional view of the manufacturing process of a semiconductor device.

[0031] Figure 9 This is a layout diagram of the upper surface of the semiconductor device according to the second embodiment.

[0032] Figure 10 It is along Figure 9A cross-sectional view of the X-X line in the image.

[0033] Figure 11 This is a layout diagram of the upper surface of the semiconductor device according to the third embodiment.

[0034] Figure 12A This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

[0035] Figure 12B It means to continue Figure 12A A cross-sectional view of the manufacturing process of a semiconductor device. Detailed Implementation

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, in the following embodiments, the same or equivalent parts will be described using the same reference numerals.

[0037] (First Embodiment)

[0038] The first embodiment will be described with reference to the accompanying drawings. The first embodiment will be described as follows. In this embodiment, a semiconductor device having an n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a trench gate structure having dual gates will be described as an example.

[0039] First, the semiconductor device of this embodiment, such as Figure 1 As shown, the device includes a cell portion 1 having a main cell region Rm that serves as a main cell and a sensing cell region Rs that serves as a sensing cell, as well as an outer peripheral portion 2. The main cell region Rm and the sensing cell region Rs are equipped with MOSFETs of the same structure, and the regions are separated by element separation.

[0040] Furthermore, the area ratio of the main cell region Rm and the sensing cell region Rs is adjusted so that the current flowing through the main cell region Rm flows through the sensing cell region Rs at a predetermined rate. While not particularly limited, the sensing cell region Rs is set to a size of several hundred to tens of thousands of times that of the main cell region Rm. In a semiconductor device, since the flowing current is proportional to the area ratio, the current flowing through the main cell region Rm is detected based on the current flowing through the sensing cell region Rs. Furthermore, the semiconductor device of this embodiment has a source region 14, which will be described in detail later. In this embodiment, the cell portion 1 and the outer peripheral portion 2 are divided according to whether the source region 14 is formed; the portion where the source region 14 is formed is designated as the cell portion 1.

[0041] The following, such as Figures 2-5As shown, the structure of the semiconductor device is explained with the width direction of the MOSFET as the x-direction and the depth direction of the MOSFET intersecting the x-direction as the y-direction. Furthermore, as described above, the main cell region Rm and the sensing cell region Rs in cell section 1 have the same structure. Therefore, the structure of cell section 1 described below applies to both the main cell region Rm and the sensing cell region Rs.

[0042] like Figures 3-5 As shown, the semiconductor device of this embodiment utilizes an n-type semiconductor device with a high impurity concentration. + The substrate 11 is formed from a semiconductor substrate 10, which is composed of a silicon substrate or the like. On the surface of the substrate 11, an impurity concentration lower than that of the substrate 11 is formed. - A drift layer 12 of the type. In addition, in this embodiment, the substrate 11 functions as a drain layer, which is equivalent to a high-concentration layer.

[0043] At a desired location on the surface of the drift layer 12, a p-type bulk region 13 with a relatively low impurity concentration is formed. The bulk region 13 is formed, for example, by ion implantation of p-type impurities into the drift layer 12, and also functions as a channel layer forming the channel region. Furthermore, the bulk region 13, as... Figure 2 As shown, multiple trench gate structures described later are formed with the y-direction as the length direction. Furthermore, the volume region 13 is as follows... Figure 2 As shown, it extends from the unit part 1 to the outer periphery part 2. Figure 2 In the diagram, the boundary between the portion forming the volume region 13 and the portion not forming the volume region 13 is represented by a dashed line as the volume region boundary 13a.

[0044] In the surface portion of the bulk region 13, there is an n-type source region 14 with a higher impurity concentration than the drift layer 12. Furthermore, the source region 14... Figure 2 As shown, the trench gate structures described later are formed with the y-direction as the length direction. However, the source region 14 is formed in a manner that terminates within the bulk region 13. Furthermore, in this embodiment, the portion in which the source region 14 is formed is designated as unit portion 1. Figure 2 In this embodiment, the boundary between the portion where the source electrode region 14 is formed and the portion where the source electrode region 14 is not formed is represented as the source electrode region boundary portion 14a. Furthermore, in this embodiment, the body region 13 corresponds to the first impurity region, and the source electrode region 14 corresponds to the second impurity region.

[0045] Furthermore, a plurality of contact trenches 15 are formed in the semiconductor substrate 10, extending from the source region 14 to the body region 13. Consequently, the body region 13 is exposed at the bottom surface of the contact trenches 15. Furthermore, a p-shaped contact portion is formed in the portion of the body region 13 exposed from the bottom surface of the contact trenches 15, serving as a body contact. +The body region of the type uses contact region 13b. In the portion of the source region 14 exposed from the side of the contact trench 15, a source contact portion n is formed. + The source region contact region 14b is of the type. Furthermore, in this embodiment, the source region contact region 14b corresponds to the contact region for the second impurity region.

[0046] Here, contact groove 15, as Figure 2 As shown, the multiple trench gate structures described later are formed with the y-direction as the length direction. Specifically, the contact trenches 15 are formed in the y-direction in a manner that protrudes from the source region 14. That is, the contact trenches 15 are formed from the cell portion 1 to the outer peripheral portion 2. However, the contact trenches 15 are formed in the y-direction in a manner that terminates inside the bulk region 13. Furthermore, the contact trenches 15 are arranged in the x-direction, and are formed between the multiple trench gate structures described later. That is, the contact trenches 15 are arranged in a strip-like layout with equal intervals.

[0047] Furthermore, the source region uses contact region 14b, as shown in the example. Figure 2 and Figure 5 As shown, the source region contact region 14b is formed around the contact trench 15. In other words, the source region contact region 14b is formed in one side 10a of the semiconductor substrate 10 in such a way that it surrounds the contact trench 15. Therefore, in this embodiment, the source region contact region 14b protrudes beyond the source region 14 in the y-direction. That is, the source region contact region 14b extends to the outer periphery 2.

[0048] Between the body region 13 and the source region 14 in the surface portion of the drift layer 12, a plurality of gate trenches 16 are formed with the y-direction (i.e., one direction) as the length direction and arranged along the x-direction. These gate trenches 16 are trenches used to form a trench gate structure. In this embodiment, the gate trenches 16 are arranged in parallel at equal intervals to form a strip-shaped layout.

[0049] Furthermore, each gate trench 16 extends from the cell portion 1 to the outer peripheral portion 2 in the y-direction. In this embodiment, the gate trench 16 is as follows: Figure 2 As shown, the outer peripheral portion 2 is formed in a manner that protrudes beyond the body region 13. In other words, the body region 13 terminates inside the extension direction of the gate trench 16 in the y-direction.

[0050] The gate trench 16 is formed deeper than the body region 13. That is, the gate trench 16 is configured to penetrate the source region 14 and the body region 13 from one side 10a of the semiconductor substrate 10 to the depth of the drift layer 12. Furthermore, in this embodiment, the gate trench 16 gradually narrows towards the bottom, becoming a rounded shape at the bottom.

[0051] Furthermore, the multiple gate trenches 16 are formed such that the gate trenches 16 at both ends in the x-direction are located in the outer peripheral portion 2. Therefore, the gate trenches 16 at both ends in the x-direction are formed to penetrate the body region 13 and reach the drift layer 12.

[0052] The inner wall surface of the gate trench 16 is covered by an insulating film 17. In this embodiment, the insulating film 17 has a shielding insulating film 17a that covers the lower portion of the gate trench 16 and a gate insulating film 17b that covers the upper portion. Specifically, the shielding insulating film 17a is formed to cover the side surface of the lower portion from the bottom of the gate trench 16. The gate insulating film 17b is formed to cover the side surface of the upper portion of the gate trench 16.

[0053] Within the gate trench 16, a shielding electrode 18 and a gate electrode 19, both made of doped polysilicon (Poly-Si), are stacked and disposed with an insulating film 17 in between. That is, a dual gate is disposed within the gate trench 16.

[0054] As described later, the shielding electrode 18 is fixed at the source potential by being connected to the upper electrode 22. Therefore, the semiconductor device of this embodiment can reduce the gate-drain capacitance and improve the electrical characteristics of the MOSFET. The gate electrode 19 performs the switching operation of the MOSFET, and a channel region is formed in the body region 13 on the side of the gate trench 16 when a gate voltage is applied.

[0055] An intermediate insulating film 20 is formed between the shielding electrode 18 and the gate electrode 19. Thus, the shielding electrode 18 is insulated from the gate electrode 19. Furthermore, the gate trenches 16, the insulating film 17, the shielding electrode 18, the gate electrode 19, and the intermediate insulating film 20 constitute a trench gate structure. Because the gate trenches 16 are formed as described above, this trench gate structure... Figure 2 The y-direction of the plane of the paper is the length direction, and the length direction is the horizontal direction. Figure 2 Multiple strips are arranged in the x-direction along the vertical direction on the paper, thus forming a strip-like layout.

[0056] Furthermore, as described above, an active electrode region 14 is formed on the inner side of the trench gate structure along its length, and this portion constitutes the cell section 1 that functions as a MOSFET. In addition, the front end portion of the trench gate structure, which is located on the outer periphery 2, is located on the outer side of the cell section 1.

[0057] At the end of the gate trench 16 along its length, such as Figure 4As shown, the shielding electrode 18 extends outward from the gate electrode 19. Furthermore, these portions are exposed from the surface side of the body region 13 and the source region 14 as a shielding liner 18a. Additionally, at the end of the gate trench 16 along its length, the portion of the shielding electrode 18 extending outward from the gate electrode 19 is also insulated from the front end portion 20a of the intermediate insulating film 20.

[0058] In addition, in this embodiment, the shielding pad 18a is wound around the unit part 1 in a manner that surrounds it. Figure 2 Although not a cross-sectional view, the shielding gasket 18a has been outlined for ease of understanding. Furthermore, in the section described later... Figure 2 In the corresponding diagram, the shielding pad 18a has been highlighted with a shading for easier understanding.

[0059] An interlayer insulating film 21, composed of an oxide film or the like, is formed on one side 10a of the semiconductor substrate 10 to cover the gate electrode 19. In the interlayer insulating film 21, such as... Figure 3 As shown, a first contact hole 21a is formed that communicates with a contact trench 15 formed on the semiconductor substrate 10.

[0060] Furthermore, as will be described in detail later, in this embodiment, the contact trench 15 and the source region contact region 14b are formed as follows: After forming the first contact hole 21a on the interlayer insulating film 21, impurity ions are implanted and thermally diffused through the first contact hole 21a using the interlayer insulating film 21 as a mask to form the source region contact region 14b. Furthermore, the contact trench 15 is formed such that after forming the source region contact region 14b, the source region contact region 14b is again connected to the first contact hole 21a by passing through it using the interlayer insulating film 21 as a mask. That is, in this embodiment, the source region contact region 14b and the contact trench 15 are formed using the same mask, which is the interlayer insulating film 21. Therefore, the source region contact region 14b is formed around the contact trench 15.

[0061] Furthermore, in the interlayer insulating film 21, such as Figure 2 and Figure 4 As shown, a second contact hole 21b is formed in the outer peripheral portion 2 to expose the gate electrode 19 and a third contact hole 21c to expose the shielding pad 18a.

[0062] Furthermore, an upper electrode 22, corresponding to the source electrode, a gate wiring 23, and a shielding wiring 24 are formed on the interlayer insulating film 21. Specifically, the upper electrode 22 is as follows: Figure 2 and Figure 3As shown, in unit 1, it is electrically connected to body region 13 (i.e., body region contact region 13b) and source region 14 (i.e., source region contact region 14b) via connecting portion 22a. Furthermore, connecting portion 22a is made of tungsten (W) inserts or the like and is embedded in the first contact hole 21a and contact trench 15 formed in the interlayer insulating film 21. In this embodiment, the upper electrode 22 corresponds to the first electrode.

[0063] Gate wiring 23 Figure 4 As shown, the shielding wiring 24 is formed such that it is electrically connected to the gate electrode 19 via a W-type connector or similar connection portion 23a embedded in the second contact hole 21b formed in the interlayer insulating film 21. The shielding wiring 24 is formed such that it is electrically connected to the shielding electrode 18 via a W-type connector or similar connection portion 24a embedded in the third contact hole 21c formed in the interlayer insulating film 21. Furthermore, Figure 2 Although not a cross-sectional view, for ease of understanding, shading has been applied to the portions of gate electrode 19 connected to gate wiring 23 and the portions of shield electrode 18 connected to shield wiring 24. Furthermore, in the sections described later... Figure 2 In the corresponding diagram, shading lines have been added to these parts for easier understanding.

[0064] A lower electrode 25, corresponding to the drain electrode, is formed on the side of the substrate 11 opposite to the drift layer 12. That is, the lower electrode 25 is formed on the other side 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 25 corresponds to the second electrode. With this structure, a vertical MOSFET of this embodiment is formed.

[0065] The above describes the structure of the semiconductor device according to this embodiment. Furthermore, in this embodiment, n - Type, n-type, n + p-type is equivalent to the first conductivity type, p-type, p-type + This type corresponds to the second conductivity type. Furthermore, in this embodiment, as described above, the semiconductor substrate 10 is constructed by including the substrate 11, the drift layer 12, the bulk region 13, the source region 14, etc.

[0066] This semiconductor device, similar to a conventional MOSFET, forms a channel in the body region 13 connected to the gate trench 16 by applying a voltage greater than a specified value to the gate electrode 19, allowing current to flow between the source and drain, thus becoming an on-state. Furthermore, if the voltage applied to the gate electrode 19 becomes less than the specified value, the channel formed in the body region 13 disappears, the current is cut off, and it becomes an off-state.

[0067] Furthermore, in such a semiconductor device, a parasitic bipolar transistor is formed by the drift layer 12, the body region 13, and the source region 14. Therefore, in such a semiconductor device, when changing from the on state to the off state, the parasitic bipolar transistor may operate through avalanche action, resulting in an excessive current flowing between the source and drain.

[0068] Therefore, in this embodiment, a contact trench 15 is formed to the outer peripheral portion 2. As a result, when the semiconductor device undergoes an avalanche operation, holes generated in the outer peripheral portion 2 can be extracted from the contact trench 15 formed to the outer peripheral portion 2. Therefore, the operation of parasitic bipolar transistors can be suppressed, and avalanche tolerance can be improved.

[0069] Here, as will be described in detail later, the source region contact area 14b and the contact trench 15 in this embodiment are constructed using the same mask. Therefore, the source region contact area 14b is formed around the contact trench 15. Consequently, when the protrusion length of the contact trench 15 protruding outward to the outer periphery 2 is relatively long, the protrusion length of the source region contact area 14b protruding outward to the outer periphery 2 also becomes longer.

[0070] Furthermore, when the semiconductor device is turned on, current flows between the source and drain. In this case, such as Figure 6 As shown, current flows in the main path R1 in the order of substrate 11, drift layer 12, bulk region 13, source region 14, and source region contact region 14b. Furthermore, current flows in the parasitic path R2 in the order of drift layer 12, bulk region 13, and source region contact region 14b. The main path R1 is where current flows only in the cell portion 1, while the parasitic path R2 is where current flows through the outer periphery 2. Moreover, by making the protrusion length of the source region contact region 14b protruding outwards into the outer periphery 2 longer, the current flowing in the parasitic path R2 increases, while the current flowing through the main path R1 decreases.

[0071] In this case, the sensing unit region Rs is extremely small in area compared to the main unit region Rm, as described above. Compared to the main unit region Rm, the current deviation caused by the increase in current in the parasitic path R2 can no longer be ignored. That is, when the protrusion length of the contact groove 15 protruding outward from the periphery 2 is longer, although the avalanche resistance can be improved, the rate of reduction of the flowing current in the sensing unit region Rs becomes larger.

[0072] Therefore, the inventors of this invention, as Figure 2 and Figure 5As shown, the length of the portion protruding from the cell portion 1 along the y-direction in the contact region 14b of the source region was defined as the protrusion length d, and the following research was conducted. Specifically, the inventors of this invention studied the deviation between the protrusion length d and the ratio of the current flowing through the main cell region Rm and the sensing cell region Rs. Furthermore, the inventors of this invention obtained... Figure 7 The results are shown. Additionally... Figure 7 Is it like this? Figure 2 The experimental results are shown when the length of the source region 14 along the y-direction, i.e., the source region length A, is set to 20 μm. The length of the source region 14 along the y-direction is, in other words, the length of the gate trench 16 along the length of the sensing cell region Rs.

[0073] like Figure 7 As shown, it is confirmed that the longer the protrusion length d, the greater the deviation. Specifically, the deviation increases sharply when the protrusion length d is 2 μm or more. In other words, in the approximate line representing the relationship between the protrusion length d and the deviation, the deviation increases sharply at the intersection of the first tangent S1 at the part where the inclination begins to increase and the second tangent S2 at the part where the inclination is greatest, which is 2 μm or more.

[0074] Here, the influence of the current flowing through the parasitic path R2 on the current flowing through the main path R1 decreases as the current flowing through the main path R1 increases, and decreases as the current flowing through the parasitic path R2 decreases. That is, the influence of the current flowing through the parasitic path R2 on the current flowing through the main path R1 decreases as the length of the sensing unit region Rs along the y-direction increases, and decreases as the protrusion length d decreases. In other words, the length of the sensing unit region Rs along the y-direction corresponding to the deviation (i.e., the length of the source region 14 along the y-direction) is inversely proportional to the protrusion length d.

[0075] therefore, Figure 7 In this embodiment, since the source region length A is 20 μm, it can be said that the deviation increases sharply when the ratio of the protrusion length d to the source region length A, i.e., d / A, is greater than 0.1. Therefore, in this embodiment, the source region length A and the protrusion length d are specified such that the ratio of the protrusion length d to the source region length A, i.e., d / A, is 0.1 or less. In addition, in this embodiment, the source region length A is equivalent to the length of the second impurity region. Furthermore, hereafter, the ratio of the protrusion length d to the source region length A, i.e., d / A, will also be simply referred to as d / A.

[0076] Next, the manufacturing method of the above-mentioned semiconductor device will be described. Additionally, the following will refer to... Figures 8A to 8D This describes the manufacturing method of the contact trench 15 and the contact region 14b for the source region. Additionally, Figures 8A to 8D Equivalent to along Figure 2The cross section of line VIIIA-VIIIA in the middle.

[0077] First, such as Figure 8A As shown, a semiconductor substrate 10 is prepared to form a bulk region 13 and a source region 14, etc.

[0078] Next, as Figure 8B As shown, an interlayer insulating film 21 is formed on one side 10a of the semiconductor substrate 10, and a first contact hole 21a is formed in the interlayer insulating film 21. Next, as... Figure 8C As shown, using the interlayer insulating film 21 as a mask, impurity ions constituting the source region contact region 14b are implanted through the first contact hole 21a and thermally diffused to form the source region contact region 14b. At this time, the source region contact region 14b is formed such that d / A is 0.1 or less. That is, the length of the opening along the y-direction of the first contact hole 21a formed in the interlayer insulating film 21 is defined such that d / A is 0.1 or less. Furthermore, since the source region contact region 14b is formed by thermal diffusion, it is formed in a state that extends below the interlayer insulating film 21.

[0079] Next, as Figure 8D As shown, using the interlayer insulating film 21 as a mask, a contact trench 15 is formed that communicates with the first contact hole 21a and penetrates the source region contact region 14b. Thus, a state is formed around the contact trench 15 where the source region contact region 14b is formed.

[0080] Although not specifically illustrated, using the interlayer insulating film 21 as a mask, impurity ions are implanted into the contact region 13b of the constituent region through the first contact hole 21a and the contact trench 15, and thermal diffusion is performed. This forms the contact region 13b of the constituent region on the bottom side of the contact trench 15. Furthermore, a prescribed semiconductor manufacturing process is performed to form the upper electrode 22, thereby manufacturing the aforementioned semiconductor device.

[0081] According to the embodiment described above, the contact trench 15 extends to the outer periphery 2. Furthermore, the source region is formed with contact region 14b such that d / A is 0.1 or less. Therefore, avalanche tolerance can be improved, and the deviation in the ratio of current flowing through the main cell region Rm and the sensing cell region Rs can be reduced. Thus, in the semiconductor device of this embodiment, avalanche tolerance can be improved, and the decrease in current detection accuracy can be suppressed.

[0082] (Second Implementation)

[0083] The second embodiment will be described. In this embodiment, compared to the first embodiment, the upper electrode 22 is also electrically connected to the body region 13 in the outer peripheral portion 2. Everything else is the same as in the first embodiment, so the description is omitted here.

[0084] In this embodiment, such as Figure 9 and Figure 10 As shown, a fourth contact hole 21d is formed in the outer peripheral portion 2 of the interlayer insulating film 21, exposing the surface of the body region 13. Furthermore, the upper electrode 22 is also connected to the body region 13 in the outer peripheral portion 2 via a connecting portion 22b, such as a W-type plug, embedded within the fourth contact hole 21d formed in the interlayer insulating film 21. That is, a contact portion C connected to the upper electrode 22 is formed in the body region 13 formed in the outer peripheral portion 2.

[0085] According to the embodiment described above, the body region 13 has a contact portion C in the outer peripheral portion 2 that is electrically connected to the upper electrode 22. In other words, the upper electrode 22 is connected to the contact portion C of the body region 13 in the outer peripheral portion 2. Therefore, when the semiconductor device performs an avalanche operation, holes are easily extracted from the upper electrode 22 via the contact portion C in the outer peripheral portion 2. As a result, the avalanche tolerance is further improved, thereby enabling an increase in the withstand voltage of the semiconductor device.

[0086] (Third Implementation)

[0087] The third embodiment will be described. In this embodiment, compared to the first embodiment, the protrusion length d is shorter than the protrusion length of the contact groove 15. Everything else is the same as the first embodiment, so the description is omitted here.

[0088] In this embodiment, such as Figure 11 As shown, the protrusion length d of the source region contact area 14b is shorter than the protrusion length of the contact trench 15. However, in this embodiment, the source region contact area 14b is also formed such that d / A is 0.1 or less. Furthermore, the protrusion length of the contact trench 15 is the length of the portion of the contact trench 15 that protrudes from the unit portion 1 along the y-direction.

[0089] The above describes the structure of the semiconductor device according to this embodiment. Next, referring to... Figure 12A , Figure 12B The manufacturing method of the contact trench 15 and the contact region 14b for the source region of such a semiconductor device will be described in detail. Furthermore, Figure 12A and Figure 12B Equivalent to along Figure 10 A cross-sectional view of the XIIA-XIIA line in the diagram.

[0090] First, such as Figure 12A As shown, after preparing a semiconductor substrate 10 with a bulk region 13 and a source region 14, a source region contact region 14b is formed using a mask (not shown). Furthermore, the source region contact region 14b is formed such that d / A is 0.1 or less.

[0091] Next, as Figure 12B As shown, an interlayer insulating film 21 is formed on one side 10a of the semiconductor substrate 10, and a first contact hole 21a is formed in the interlayer insulating film 21. Furthermore, the first contact hole 21a is formed to protrude beyond the source region contact region 14b in the y-direction. That is, the first contact hole 21a is formed such that the source region contact region 14b and the body region 13 are exposed in the y-direction.

[0092] Although not specifically illustrated thereafter, a contact trench 15 is formed using the interlayer insulating film 21 as a mask, communicating with the first contact hole 21a and penetrating the source region using the contact region 14b. That is, in this embodiment, the source region using the contact region 14b and the contact trench 15 are formed using different masks.

[0093] As explained above, even if the protrusion length d of the source region contact region 14b is shorter than the protrusion length of the contact trench 15, as long as d / A is 0.1 or less, the same effect as in the first embodiment described above can be obtained. Furthermore, by forming the source region contact region 14b and the contact trench 15 with different masks, the protrusion length d of the source region contact region 14b and the protrusion length of the contact trench 15 can be easily made different. Therefore, the protrusion length d of the source region contact region 14b and the protrusion length of the contact trench 15 can be easily adjusted according to the characteristics of the semiconductor device.

[0094] (Other implementation methods)

[0095] This disclosure describes embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and variations within the same range. Furthermore, various combinations and forms, and even combinations and forms containing only one element, or more or less thereof, also fall within the scope and spirit of this disclosure.

[0096] For example, in the embodiments described above, a MOSFET with an n-channel trench gate structure, where the first conductivity type is n-type and the second conductivity type is p-type, has been described as an example of a semiconductor device. However, this is only one example, and other semiconductor devices with different structures may also be used, such as a p-channel trench gate MOSFET where the conductivity types of each component are reversed relative to the n-channel type. Furthermore, in addition to MOSFETs, semiconductor devices may also be IGBTs with the same structure. In the case of IGBTs, in addition to the n-channel type described in the embodiments above, + The substrate 11 of type 11 is changed to P + Apart from the collector layer, it is the same as the vertical MOSFET described in the above embodiments.

[0097] Furthermore, in the third embodiment described above, an example of forming the source region contact region 14b before forming the interlayer insulating film 21 was described. However, it is also possible to do it as follows: After forming the first contact hole 21a in the interlayer insulating film 21, a mask with an opening is disposed on the interlayer insulating film 21 to form the source region contact region 14b. Then, a contact trench 15 can be formed using the interlayer insulating film as a mask.

[0098] Furthermore, it is possible to manufacture a semiconductor device that appropriately combines the above-described embodiments. For example, the second and third embodiments described above can be combined, and the body region 13 can be connected to the upper electrode 22 in the outer peripheral portion 2.

Claims

1. A semiconductor device comprising a semiconductor element having a trench gate structure with dual gates, characterized in that, have: The unit section is formed with the aforementioned semiconductor element; and The outer periphery surrounds the aforementioned unit portion. The aforementioned unit section includes a main unit region and a sensing unit region having the same structure as the main unit region, through which a smaller current flows than that flowing through the main unit region. The aforementioned main unit region and the aforementioned sensing unit region have: A semiconductor substrate having a drift layer of the first conductivity type; The first impurity region of the second conductivity type is formed on the aforementioned drift layer; The second impurity region of the first conductivity type is formed on the surface portion of the first impurity region within the first impurity region, and the impurity concentration is higher than that of the drift layer. The above-mentioned trench gate structures are configured as dual gates by sequentially stacking a shielding electrode, an intermediate insulating film, and a gate electrode in a strip-shaped arrangement of multiple gate trenches arranged in a length direction that extends from the second impurity region to the drift layer. Contact grooves are formed between the aforementioned groove grid structures, extending from the aforementioned unit portion to the aforementioned outer periphery in one of the aforementioned directions as the length direction, and penetrating the aforementioned second impurity region to reach the aforementioned first impurity region. The second impurity region is formed by a contact region along the wall of the contact groove, and the impurity concentration is higher than that of the second impurity region. A high-concentration layer of the first or second conductivity type is formed on the opposite side of the first impurity region, separated from the drift layer, and the impurity concentration is higher than that of the drift layer. An interlayer insulating film is disposed on the above-mentioned trench gate structure, the above-mentioned first impurity region and the above-mentioned second impurity region, and has contact holes connected to the above-mentioned contact trenches. The first electrode is electrically connected to the second impurity region and the first impurity region via the contact hole and the contact trench; and The second electrode is electrically connected to the aforementioned high-concentration layer. The length of the aforementioned unit portion along the aforementioned one direction is set as the length of the aforementioned second impurity region along the aforementioned one direction. The second impurity region is provided by a contact region extending from the unit portion to the outer periphery. Let the length of the portion of the second impurity region extended from the contact region to the outer periphery along the aforementioned direction be the protrusion length d, and let the length of the second impurity region along the aforementioned direction be the length A of the second impurity region. The ratio of the protrusion length d to the length A of the second impurity region, i.e., d / A, is 0.1 or less.

2. The semiconductor device as claimed in claim 1, characterized in that, The first impurity region extends from the aforementioned unit portion to the aforementioned outer periphery portion. In the aforementioned interlayer insulating film, a contact hole is formed in the portion of the outer periphery that is closer to the aforementioned unit portion in one direction, exposing the aforementioned first impurity region. The first electrode is electrically connected to the first impurity region in the outer peripheral portion via the contact hole.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The second impurity region is formed by a contact region that surrounds the contact trench.

4. A method for manufacturing a semiconductor device, The aforementioned semiconductor device includes: The unit section is formed with a semiconductor element; and The outer periphery surrounds the aforementioned unit portion. The aforementioned unit section includes a main unit region and a sensing unit region having the same structure as the main unit region, through which a smaller current flows than that flowing through the main unit region. The aforementioned main unit region and the aforementioned sensing unit region have: A semiconductor substrate having a drift layer of the first conductivity type; The first impurity region of the second conductivity type is formed on the aforementioned drift layer; The second impurity region of the first conductivity type is formed on the surface portion of the first impurity region within the first impurity region, and the impurity concentration is higher than that of the drift layer. Multiple trench gate structures are configured as dual gates by sequentially stacking shielding electrodes, intermediate insulating films, and gate electrodes in multiple gate trenches arranged in a strip shape with one direction as the length direction and penetrating from the second impurity region to the drift layer. Contact grooves are formed between the aforementioned groove grid structures, extending from the aforementioned unit portion to the aforementioned outer periphery in one of the aforementioned directions as the length direction, and penetrating the aforementioned second impurity region to reach the aforementioned first impurity region. The second impurity region is formed by a contact region along the wall of the contact groove, and the impurity concentration is higher than that of the second impurity region. A high-concentration layer of the first or second conductivity type is formed on the opposite side of the first impurity region, separated from the drift layer, and the impurity concentration is higher than that of the drift layer. An interlayer insulating film is disposed on the above-mentioned trench gate structure, the above-mentioned first impurity region and the above-mentioned second impurity region, and has contact holes connected to the above-mentioned contact trenches. The first electrode is electrically connected to the second impurity region and the first impurity region via the contact hole and the contact trench; and The second electrode is electrically connected to the aforementioned high-concentration layer. The length of the aforementioned unit portion along the aforementioned one direction is set as the length of the aforementioned second impurity region along the aforementioned one direction. The second impurity region is provided by a contact region extending from the unit portion to the outer periphery. Let the length of the portion of the second impurity region extending from the contact region to the outer periphery along the aforementioned direction be the protrusion length d, and let the length of the second impurity region along the aforementioned direction be the length A of the second impurity region. The ratio of the protrusion length d to the length A of the second impurity region, i.e., d / A, is 0.1 or less. The manufacturing method of the above-mentioned semiconductor device is characterized by performing the following steps: Prepare the aforementioned semiconductor substrate; The contact area used to form the second impurity region mentioned above; and The aforementioned contact trenches are formed in the aforementioned semiconductor substrate. In the process of forming the contact area for the second impurity region, the ratio of the protrusion length d to the length A of the second impurity region, i.e., d / A, is 0.1 or less.

5. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The process of forming the contact area for the second impurity region is performed using the same mask as the process of forming the contact trench.

6. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that, After the process of preparing the semiconductor substrate, the process of forming the interlayer insulating film on the semiconductor substrate is performed. After the process of forming the interlayer insulating film described above, a process of forming the contact holes in the interlayer insulating film is performed. In the process of forming the contact region for the second impurity region, using the interlayer insulating film as a mask, impurity ions are implanted into the semiconductor substrate through the contact holes, and the impurities are thermally diffused to form the contact region for the second impurity region. In the process of forming the contact trench, the interlayer insulating film is used as a mask to form the contact trench that communicates with the contact hole and penetrates the second impurity region through the contact area.

7. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The process of forming the contact area for the second impurity region and the process of forming the contact trench are performed using different masks.

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