Undervoltage protection circuit

Abstract

The present disclosure provides an undervoltage protection circuit, which utilizes a reference voltage generating module to respond to an indication signal, generates a first reference voltage according to the power supply voltage connected to the power supply end, and provides the first reference voltage through the reference voltage generating module, and adjusts its own circuit state according to the first reference voltage and the first reference voltage to generate a second reference voltage, and the second reference voltage is proportional to the first reference voltage. Its output module can respond to the aforementioned indication signal, generate an output voltage signal according to the first voltage signal generated by comparing the first reference voltage and the first reference voltage, and logically control the second voltage signal generated according to the second reference voltage control. In this way, by establishing a logical association between the voltage indication signal and the generated reference voltage, it can be ensured that the establishment of the output voltage signal will not be affected by any parasitic parameters, and at the same time, it can correctly indicate the subsequent circuit to improve the accuracy and stability of the circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an undervoltage protection circuit. Background Art

[0002] Conventional undervoltage protection circuit 100, such as Figure 1 As shown, some key nodes, such as the reference voltage Vbg, are selected by the voltage indication signal EN. After the power supply is powered on, the voltage indication signal EN is powered on again. At the same time, two conditions are judged. The comparator COMP establishes the correct indication level at the node A, and the reference voltage Vbg establishes the correct indication level at the node B, so as to ensure that the delay time at the node C is normally established, so that the output signal of the undervoltage protection circuit 100 at the output node E can be correctly indicated, and theoretically, it is guaranteed that there will be no errors.

[0003] However, errors may occur in some cases because both the reference voltage Vreg and the reference voltage Vbg are controlled by the voltage indication signal EN. The higher the reference voltage Vbg, the higher the reference voltage Vreg. When the reference voltage Vbg is stable at 1.2V, the reference voltage Vreg is stable at 5V. In fact, the reference voltage Vbg is established faster than the reference voltage Vreg. Due to the influence of parasitic parameters, the reference voltage Vbg may be established enough to turn on the NMOS transistor M1, but the reference voltage Vreg is not enough to allow the undervoltage protection circuit 100 to work normally. In this case, the NMOS transistor M1 will lose its function during the rising process of the reference voltage Vreg. If this happens, If the comparator COMP malfunctions, the NMOS transistor M2 behind it will not turn on. At this time, since the reference voltage Vreg has just been powered on, there is a parasitic capacitance to the ground at node D, which is initially in a low-level state, causing the PMOS transistor M3 to turn on instantly (the PMOS transistor M3 cannot be removed because the voltage at node C rises slowly. The positive feedback structure it constructs can prevent the inverter INV1 behind node C from jittering near the threshold). The capacitor C1 can be fully charged. When the above conditions are triggered at the same time, the output of the undervoltage protection circuit 100 is always in a high-level state during the process of establishing the reference voltage Vreg, and there is no clearing action for the subsequent circuits. Figure 2 As shown, this will eventually cause the chip to malfunction during power-on.

[0004] Therefore, traditional undervoltage protection circuits involve many signals. In actual chips, various parasitic factors may cause errors in some signals, which may eventually lead to the undervoltage protection circuit outputting incorrect signals, causing malfunctions and power-on failures. Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides an undervoltage protection circuit.

[0006] The present disclosure provides an undervoltage protection circuit, comprising:

[0007] a reference voltage generating module, which generates a first reference voltage according to a power voltage connected to the power terminal in response to an indication signal;

[0008] a reference voltage generating module, configured to provide a first reference voltage and adjust its own circuit state according to the first reference voltage and the first reference voltage to generate a second reference voltage, wherein the second reference voltage is proportional to the first reference voltage;

[0009] The output module has a first input terminal connected to a first reference voltage, a second input terminal connected to the first reference voltage, a third input terminal connected to a second reference voltage, and an output terminal for providing an output voltage signal.

[0010] The output module generates the aforementioned output voltage signal in response to the aforementioned indication signal, based on logic control of a first voltage signal generated by comparing the first base voltage and the first reference voltage, and a second voltage signal generated by controlling the second reference voltage.

[0011] Preferably, the high level of the aforementioned indication signal is valid, and the low level is invalid.

[0012] Preferably, the aforementioned indication signal maintains its high level state in a stable state after the power supply voltage is powered on.

[0013] Preferably, the aforementioned reference voltage generating module includes:

[0014] a driving transistor, wherein a first terminal of the driving transistor is connected to the power supply terminal and receives a power supply voltage, and a second terminal of the driving transistor provides the aforementioned first reference voltage;

[0015] a resistor string connected between the second terminal of the driving transistor and ground;

[0016] an error amplifier, wherein the positive input terminal of the error amplifier is connected to the first reference voltage, the negative input terminal is connected to one of the connection nodes between the resistor strings, and the output terminal is connected to the control terminal of the driving transistor.

[0017] One of the connection nodes between the resistor strings is used to provide the aforementioned second reference voltage.

[0018] Preferably, the aforementioned output module includes:

[0019] A comparator, wherein the positive input terminal of the comparator is connected to the output terminal of the reference voltage generating module as the aforementioned second input terminal and is connected to the first reference voltage, the negative input terminal is connected to the second terminal of the driving transistor as the aforementioned first input terminal and is connected to the first reference voltage, and the output terminal is used to provide the aforementioned first voltage signal.

[0020] Preferably, the aforementioned output module further includes:

[0021] A first current source and a first transistor are connected in series between the aforementioned first input terminal and the ground, and a connection node between the two provides the aforementioned second voltage signal. The control terminal of the first transistor is connected to the second reference voltage as the aforementioned third input terminal.

[0022] Preferably, the aforementioned output module further includes:

[0023] A NOR gate, a first NOT gate, and a second transistor, wherein the NOR gate and the first NOT gate are sequentially connected in series between the output terminal of the comparator and the control terminal of the second transistor, and the input terminals of the NOR gate are respectively connected to the first voltage signal and the second voltage signal, the first terminal of the second transistor provides a third voltage signal, and the second terminal is grounded;

[0024] The second current source and the first capacitor are connected in series between the first input terminal and the ground, and a connection node therebetween is connected to the third voltage signal.

[0025] Preferably, the aforementioned output module further includes:

[0026] a second NOT gate and a third NOT gate, wherein the input end of the second NOT gate is connected to the aforementioned third voltage signal, the output end of the second NOT gate is connected to the third NOT gate, and the output end of the third NOT gate is used to provide the aforementioned output voltage signal;

[0027] A third transistor has a first end connected to the aforementioned first input end, a second end connected to the input end of the second NOT gate, and a control end connected to the output end of the second NOT gate.

[0028] Preferably, any one of the aforementioned driving transistor, the first transistor, the second transistor and the third transistor is a metal oxide semiconductor field effect transistor.

[0029] Preferably, the aforementioned driving transistor and the third transistor are P-channel metal oxide semiconductor field effect transistors.

[0030] The first transistor and the second transistor are N-channel metal oxide semiconductor field effect transistors.

[0031] The present disclosure provides an undervoltage protection circuit, which utilizes a reference voltage generation module to respond to an indication signal, generates a first reference voltage based on the power supply voltage connected to the power supply terminal, and provides the first reference voltage through the reference voltage generation module, and adjusts its own circuit state based on the first reference voltage and the first reference voltage to generate a second reference voltage, and the second reference voltage is proportional to the first reference voltage. Its output module can respond to the aforementioned indication signal, generate an output voltage signal based on the first voltage signal generated by comparing the first reference voltage and the first reference voltage, and logically control the second voltage signal generated based on the second reference voltage control. By establishing a logical association between the voltage indication signal and the generated reference voltage, it can be ensured that the establishment of the output voltage signal will not be affected by any parasitic parameters, so that the signal output by the undervoltage protection circuit can correctly indicate the subsequent circuit, thereby improving the accuracy and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram showing the structure of an undervoltage protection circuit in the prior art is shown;

[0034] Figure 2 Show Figure 1 Schematic diagram of waveforms of signals at various nodes in the undervoltage protection circuit shown;

[0035] Figure 3 A schematic structural diagram of an undervoltage protection circuit provided by an embodiment of the present disclosure is shown;

[0036] Figure 4 Show Figure 3 Schematic diagram of the waveforms of signals at each node in the undervoltage protection circuit shown. DETAILED DESCRIPTION

[0037] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to facilitate a more thorough and comprehensive understanding of the present disclosure.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0039] Modern, efficient, and precise motor control is implemented using computers. A complete motion control system is formed by the motor chip, a main processor, a motor, and an incremental encoder. When the power supply voltage falls below the chip's normal operating range, some internal circuits may malfunction. This can cause internal logic errors and render the external switch in an indeterminate state. If the external switch is on while the rest of the chip is malfunctioning, it could burn out or damage external circuits. Therefore, an undervoltage protection circuit is essential. This ensures that when the power supply voltage falls below the set operating threshold, the external power transistors and most internal modules are shut down.

[0040] When the undervoltage protection circuit is working, the chip bandgap reference circuit and linear regulator (LDO) module are not working properly, that is, the undervoltage protection circuit must have a reference voltage.

[0041] To ensure that the trigger voltage remains stable over time due to process and temperature fluctuations, the reference voltage must be constant. Existing undervoltage protection circuits often include a reference circuit to generate a reference voltage. A comparator is used to compare the sampled power supply voltage signal with the reference voltage signal generated by the reference circuit. However, these existing undervoltage protection circuits are susceptible to interference from the reference circuit used to generate the reference voltage, requiring the design of a specialized comparator circuit, resulting in a relatively complex structure.

[0042] Based on this, the undervoltage protection circuit shown in the embodiment of the present disclosure is proposed. By establishing a logical association between the voltage indication signal and the generated reference voltage, it can be ensured that the establishment of the output voltage signal will not be affected by any parasitic parameters, so that the signal output by the undervoltage protection circuit can correctly indicate the subsequent circuit, thereby improving the accuracy and stability of the circuit.

[0043] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 3 FIG. 1 shows a schematic diagram of the structure of the undervoltage protection circuit provided by an embodiment of the present disclosure. Figure 4 Show Figure 3 Schematic diagram of the waveforms of signals at each node in the undervoltage protection circuit shown.

[0045] refer to Figure 3 , an embodiment of the present disclosure provides an undervoltage protection circuit 200, which includes:

[0046] A reference voltage generating module 210, which generates a first reference voltage Vbg according to a power supply voltage VDD connected to a power supply terminal in response to an indication signal EN;

[0047] a reference voltage generating module 220 for providing a first reference voltage Vreg and adjusting its own circuit state according to the first reference voltage Vbg and the first reference voltage Vreg to generate a second reference voltage Vbg2, wherein the second reference voltage Vbg2 is proportional to the first reference voltage Vreg;

[0048] The output module 230 has a first input terminal connected to the first reference voltage Vreg, a second input terminal connected to the first reference voltage Vbg, a third input terminal connected to the second reference voltage Vbg2, and an output terminal providing an output voltage signal Vout.

[0049] In which, the output module 230 responds to the aforementioned indication signal EN, generates the aforementioned output voltage signal Vout according to the logic control of the first voltage signal Va generated by comparing the first reference voltage Vreg and the first reference voltage Vbg, and the second voltage signal Vb generated by controlling the second reference voltage Vbg2.

[0050] In this embodiment, the reference voltage generating module 210 is, for example, a conventional bandgap reference circuit, which is intended to provide the aforementioned first reference voltage Vbg. The specific circuit structure and principle thereof are not described in detail herein.

[0051] Furthermore, in this embodiment, the high level of the indication signal EN is valid, and the low level is invalid.

[0052] For further reference, Figure 4 In this embodiment, the indication signal EN maintains its high level state in a stable state after the power supply voltage VDD is powered on.

[0053] Furthermore, in this embodiment, the aforementioned reference voltage generating module 220 includes:

[0054] A driving transistor Q1 , wherein a first terminal of the driving transistor Q1 is connected to a power supply terminal and receives a power supply voltage VDD, and a second terminal of the driving transistor Q1 provides the aforementioned first reference voltage Vreg;

[0055] a resistor string connected between the second end of the driving transistor Q1 and ground. Specifically, the resistor string includes, for example, a first resistor R1, a second resistor R2, and a third resistor R3 sequentially connected between the second end of the driving transistor Q1 and ground;

[0056] The error amplifier EA1 has a positive input terminal connected to the first reference voltage Vbg, a negative input terminal connected to the connection node of the second resistor R2 and the third resistor R3, and an output terminal connected to the control terminal of the driving transistor Q1, wherein the connection node between the first resistor R1 and the second resistor R2 is used to provide the aforementioned second reference voltage Vbg2.

[0057] Furthermore, in this embodiment, the output module 230 includes a comparator COMP1, a first current source I1, a first transistor M1, a NOR gate 201, a first NOT gate 202, a second transistor M2, a second current source I2, and a first capacitor C1.

[0058] Among them, the positive input terminal of the comparator COMP1 is connected to the output terminal of the reference voltage generating module 210 as the aforementioned second input terminal, and is connected to the first reference voltage Vbg, and the negative input terminal is connected to the second end of the driving transistor Q1 as the aforementioned first input terminal, and is connected to the first reference voltage Vreg, and the output node A is used to provide the aforementioned first voltage signal Va.

[0059] The first current source I1 and the first transistor M1 are connected in series between the first input terminal and the ground, and a connection node B therebetween provides the second voltage signal Vb. The control terminal of the first transistor M1 serves as the third input terminal to access the second reference voltage Vbg2.

[0060] The NOR gate 201 and the first NOT gate 202 are connected in series between the output terminal of the comparator COMP1 and the control terminal of the second transistor M2, and the input terminal of the NOR gate 201 is respectively connected to the first voltage signal Va and the second voltage signal Vb. The first terminal of the second transistor M2 serves as a connection node C to provide a third voltage signal Vc, and the second terminal is grounded.

[0061] The second current source I2 and the first capacitor C1 are connected in series between the first input terminal and the ground, and a connection node C therebetween is connected to the third voltage signal Vc.

[0062] Furthermore, in this embodiment, the output module 230 further includes:

[0063] A second NOT gate 203 and a third NOT gate 204, wherein the input terminal of the second NOT gate 203 is connected to the aforementioned third voltage signal Vc, and the output terminal of the second NOT gate 203 is connected to the third NOT gate 204 as a connection node D. The output terminal of the third NOT gate 203 is used as an output node E to provide the aforementioned output voltage signal Vout;

[0064] The third transistor M3 has a first terminal connected to the aforementioned first input terminal, a second terminal connected to the input terminal of the second NOT gate 203 , and a control terminal connected to the connection node D.

[0065] Furthermore, in this embodiment, any one of the aforementioned driving transistor Q1 , the first transistor M1 , the second transistor M2 and the third transistor M3 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET, hereinafter referred to as MOS transistor).

[0066] Furthermore, in this embodiment, the aforementioned driving transistor Q1 and the third transistor M3 are P-channel MOS transistors, and the first transistor M1 and the second transistor M2 are N-channel MOS transistors.

[0067] Combined with the above Figure 1 The description of the present disclosure and the embodiments of the present disclosure Figure 3 To understand, after the power supply voltage VDD is powered on, the indication signal EN is powered on again. It is necessary to judge two conditions at the same time, and the first reference voltage Vreg and the first reference voltage Vbg are both controlled by the indication signal EN. The higher the first reference voltage Vbg is, the higher the first reference voltage Vreg is. In fact, the establishment of the first reference voltage Vbg is faster than the first reference voltage Vreg. In this embodiment, the driving signal of the first transistor M1 is replaced from the first reference voltage Vbg to the second reference voltage Vbg2 generated by the resistor voltage division of the first reference voltage Vreg. In this way, similar to Figure 1 In the described scenario, when the first reference voltage Vreg is established at 5V, the corresponding second reference voltage Vbg2 is 1.25V. Thus, when the second reference voltage Vbg2 is established, the first transistor M1 is turned on, which also indicates that the first reference voltage Vbg is established. The voltage values of the first reference voltage Vreg and the second reference voltage Vbg2 have a certain ratio. Even if the turn-on threshold voltage Vth of the first transistor M1 is the minimum in a certain case, the corresponding voltage Vreg can reach more than 2V when it is only 700mV. Therefore, when the first transistor M1 is turned on, Before, the first reference voltage Vreg can allow the subsequent logic to work normally. At this time, the potential of the second voltage signal Vb at the node B is H due to the pull-up current source (the first current source I1). When the second transistor M2 is turned on, the third voltage signal Vc at the node C will be cleared. Because the size of the second transistor M2 is large enough, even if the parasitic PMOS is turned on, the third voltage signal Vc at the node C will be pulled down. Finally, the node C will gradually rise from 0V, and the output voltage signal Vout of the undervoltage protection circuit 200 will also become H after experiencing the delay of the two-stage inverter. Figure 4Therefore, the undervoltage protection circuit 200 provided in the embodiment of the present disclosure can ensure that the establishment of the output voltage signal Vout is not affected by any parasitic parameters, so that the signal output by the undervoltage protection circuit 200 can correctly indicate the subsequent circuit, thereby improving the accuracy and stability of the circuit and preventing chip failure during the power-on process.

[0068] It should be noted that in the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "inner", etc., which indicate orientation or positional relationships, are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0069] In addition, as used herein, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0070] Finally, it should be noted that the above embodiments are merely examples for the purpose of illustrating the present disclosure and are not intended to limit the embodiments. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to provide an exhaustive list of all embodiments. Obvious variations or modifications arising therefrom remain within the scope of protection of the present disclosure.

Claims

1. An undervoltage protection circuit, characterized in that: include: a reference voltage generating module, wherein the reference voltage generating module generates a first reference voltage according to a power voltage connected to the power terminal in response to an indication signal; a reference voltage generating module, configured to provide a first reference voltage and adjust its own circuit state according to the first reference voltage and the first reference voltage to generate a second reference voltage, wherein the second reference voltage is proportional to the first reference voltage; an output module having a first input terminal connected to the first reference voltage, a second input terminal connected to the first reference voltage, a third input terminal connected to the second reference voltage, and an output terminal for providing an output voltage signal, The output module generates the output voltage signal in response to the indication signal by logically controlling a first voltage signal generated by comparing the first base voltage with the first reference voltage and a second voltage signal generated by controlling the second reference voltage. The output module includes: a comparator, wherein the positive input terminal of the comparator is connected to the output terminal of the reference voltage generating module as the second input terminal and is connected to the first reference voltage, the negative input terminal of the comparator is connected to the first reference voltage as the first input terminal, and the output terminal is used to provide the first voltage signal; a first current source and a first transistor, wherein the first current source and the first transistor are connected in series between the first input terminal and ground, and a connection node between the first current source and the first transistor provides the second voltage signal, and a control terminal of the first transistor serves as the third input terminal and is connected to the second reference voltage; a NOR gate, a first NOT gate, and a second transistor, wherein the NOR gate and the first NOT gate are sequentially connected in series between the output terminal of the comparator and the control terminal of the second transistor, and the input terminals of the NOR gate are respectively connected to the first voltage signal and the second voltage signal, the first terminal of the second transistor provides a third voltage signal, and the second terminal is grounded; a second current source and a first capacitor, wherein the second current source and the first capacitor are connected in series between the first input terminal and ground, and a connection node therebetween is connected to the third voltage signal; a second NOT gate and a third NOT gate, wherein the input end of the second NOT gate is connected to the third voltage signal, the output end of the second NOT gate is connected to the third NOT gate, and the output end of the third NOT gate is used to provide the output voltage signal; A third transistor, wherein a first end of the third transistor is connected to the first input end, a second end of the third transistor is connected to the input end of the second NOT gate, and a control end of the third transistor is connected to the output end of the second NOT gate.

2. The undervoltage protection circuit according to claim 1, characterized in that: The high level of the indication signal is valid, and the low level is invalid.

3. The undervoltage protection circuit according to claim 2, characterized in that: The indication signal maintains its high level state in a stable state when the power-on of the power supply voltage is completed.

4. The undervoltage protection circuit according to claim 3, characterized in that: The reference voltage generating module includes: a driving transistor, wherein a first terminal of the driving transistor is connected to a power supply terminal and receives the power supply voltage, and a second terminal of the driving transistor provides the first reference voltage; a resistor string connected between the second terminal of the driving transistor and ground; an error amplifier, wherein a positive input terminal of the error amplifier is connected to the first reference voltage, a negative input terminal is connected to one of the connection nodes between the resistor strings, and an output terminal is connected to the control terminal of the driving transistor, Wherein, one of the connection nodes between the resistor strings is used to provide the second reference voltage.

5. The undervoltage protection circuit according to claim 4, characterized in that: Any one of the driving transistor, the first transistor, the second transistor, and the third transistor is a metal oxide semiconductor field effect transistor.

6. The undervoltage protection circuit according to claim 4, characterized in that: The driving transistor and the third transistor are P-channel metal oxide semiconductor field effect transistors, The first transistor and the second transistor are N-channel metal oxide semiconductor field effect transistors.

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