Semiconductor processing apparatus

Abstract

The present application provides a semiconductor processing device, which comprises: a first chamber part; a second chamber part movable relative to the first chamber part between an open position and a closed position, wherein a microchamber is formed between the first chamber part and the second chamber part when the second chamber part is located at the closed position relative to the first chamber part, a semiconductor wafer can be accommodated in the microchamber, and the semiconductor wafer can be taken out or put in when the second chamber part is located at the open position relative to the first chamber part; at least one of the first chamber part and the second chamber part comprises a main part and an embedded part, a fitting groove is formed on a surface of the main part facing the microchamber, and the embedded part is embedded in the fitting groove to form an integral whole with the main part. In this way, the deformation error of the embedded part caused by the difference between the processing temperature and the working temperature can be greatly reduced, thereby improving the accuracy of the semiconductor processing device.

Description

Technical field

[0001] The present invention relates to the field of semiconductor wafer processing, and in particular to a semiconductor processing device. [Background Technology]

[0002] Precision edge etching of semiconductor wafers is a challenging process. It requires precise micron-level etching of the wafer edge without damaging or contaminating the remaining thin film. In epitaxial wafer manufacturing and advanced integrated circuit manufacturing, wafer edge etching is a critical step in ensuring thin film quality and improving chip yield.

[0003] Please refer to Figures 1a to 1d ,in: Figure 1a 4 shows a schematic structural diagram of a semiconductor wafer 400. Figure 1b for Figure 1a EE cross-sectional view; Figure 1c A partial cross-sectional view of an outer edge of a semiconductor wafer before outer edge processing; Figure 1d This is a cross-sectional view of the outer edge of a semiconductor wafer after outer edge processing. Figures 1a to 1d As shown, semiconductor wafer 400 includes a base layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of base layer 401. After a selective etching process is performed on the first edge surface 404, the second wafer surface 406, and the outer bevel 408 of the outer edge portion of semiconductor wafer 400, the thin film layer 402 at the outer edge portion of semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of base layer 401 are exposed.

[0004] Existing wafer edge etching equipment can be categorized into two main types: dry and wet. Dry methods are primarily divided into plasma and polishing methods. Plasma edge etching is characterized by high equipment costs and complex methods, and is primarily used in integrated circuit chip manufacturing. Polishing involves rotating the wafer, utilizing physical friction and a combination of chemical vapors and liquids to remove the film that comes into contact. Polishing equipment is relatively inexpensive, but the retained film is susceptible to damage and contamination, and is primarily used in wafer manufacturing processes under 200 mm. Wet methods primarily include lamination and vacuum adsorption. The lamination method uses a pure, corrosion-resistant plastic film such as PTFE or PE to protect the portion of the film that needs to be retained. The entire film is then exposed to a chemically corrosive atmosphere or immersed in a chemically corrosive solution to etch away the exposed portion. The lamination method involves multiple steps and requires a variety of equipment, including lamination, wet etching, cleaning, and film removal equipment. The vacuum adsorption method uses a vacuum head to hold the wafer. The head holds the wafer, protecting the film to be retained within the head while exposing the film to be removed. The head and wafer are then immersed in a chemical etching solution to remove the film exposed outside. The vacuum adsorption method has simple steps and low equipment costs, but it is prone to damage and contamination of the retained film. It is primarily used in wafer manufacturing processes under 200mm.

[0005] Chinese patent application number 201821459515.8, titled "A Semiconductor Processing Device," discloses a semiconductor wafer edge processing solution. However, due to the difference in manufacturing and operating temperatures between the upper and lower chambers, there can be slight errors in the dimensions during manufacturing and in use, affecting the accuracy of wafer edge processing.

[0006] In view of this, there is a need to provide an improved semiconductor processing equipment to reduce the impact of thermal expansion and contraction. [Summary of the invention]

[0007] An object of the present invention is to provide a semiconductor processing device that can reduce the influence of thermal expansion and contraction.

[0008] To achieve the above-mentioned objectives, according to a first aspect of the present invention, there is provided a semiconductor processing device, comprising: a first chamber portion; a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the microchamber; when the second chamber portion is located at the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in; at least one of the first chamber portion and the second chamber portion comprises a main body portion and an embedding portion, an embedding groove is formed on a surface of the main body portion facing the microchamber, and the embedding portion is embedded in the embedding groove to form a whole with the main body portion.

[0009] Compared with the prior art, at least one of the first chamber portion and the second chamber portion in the present invention is composed of a main body portion and an embedded portion. A fitting groove is formed on the surface of the main body portion facing the microchamber, and the embedded portion is embedded in the fitting groove to form a whole with the main body portion. The thermal expansion coefficient of the main body portion at room temperature is smaller than the thermal expansion coefficient of the embedded portion at room temperature. The volume of the embedded portion is reduced, and the total expansion or contraction caused by temperature changes is also reduced. At the same time, the expansion range of the embedded portion can be controlled by selecting the size of the fitting groove of the main body portion and the size of the embedded portion, thereby controlling the impact of thermal expansion and contraction on the embedded portion.

Brief Description of the Drawings

[0010] The present invention will be more readily understood with reference to the accompanying drawings and the following detailed description, wherein like reference numerals correspond to like structural components, and wherein:

[0011] Figure 1a It is a structural schematic diagram of a semiconductor wafer;

[0012] Figure 1b for Figure 1a EE cross-sectional view;

[0013] Figure 1c A cross-sectional view of an outer edge portion of a semiconductor wafer before outer edge processing;

[0014] Figure 1d is a cross-sectional view of an outer edge portion of a semiconductor wafer after outer edge processing;

[0015] Figure 2a is a schematic cross-sectional view of a semiconductor processing device according to a first embodiment of the present invention;

[0016] Figure 2b for Figure 2a An enlarged schematic diagram of circle A in FIG;

[0017] Figure 3a for Figure 2a A bottom view of a first chamber portion of a semiconductor processing apparatus;

[0018] Figure 3b for Figure 2a A top view of a second chamber portion of a semiconductor processing apparatus;

[0019] Figure 4 is a schematic cross-sectional view of a second embodiment of a semiconductor processing device according to the present invention;

[0020] Figure 5 for Figure 4 An enlarged schematic diagram of circle B in FIG;

[0021] Figure 6a for Figure 4 A bottom view of a first chamber portion of a semiconductor processing apparatus;

[0022] Figure 6b for Figure 4 A top view of a second chamber portion of a semiconductor processing apparatus;

[0023] Figure 7a is a schematic cross-sectional view of a semiconductor processing device according to a third embodiment of the present invention;

[0024] Figure 7b for Figure 7a An enlarged schematic diagram of circle D in FIG;

[0025] Figure 8 for Figure 7a A three-dimensional exploded example diagram of the lower chamber part. [Specific implementation method]

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The term "one embodiment" or "embodiment" as used herein means that the specific features, structures, or characteristics associated with the embodiment may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily refer to the same embodiment, nor does it necessarily refer to separate or selected embodiments that are mutually exclusive with other embodiments. The terms "multiple" and "several" as used herein mean two or more. The term "and / or" as used herein means "and" or "or."

[0028] First embodiment:

[0029] Please refer to Figures 2a to 3b , which shows a schematic structural diagram of a semiconductor processing device 100 provided by a first embodiment of the present invention, wherein: Figure 2ais a schematic cross-sectional view of a semiconductor processing device according to a first embodiment of the present invention; Figure 2b for Figure 2a An enlarged schematic diagram of circle A in FIG; Figure 3a for Figure 2a A bottom view of a first chamber portion of a semiconductor processing apparatus; Figure 3b for Figure 2a A top view of a second chamber portion of a semiconductor processing apparatus in FIG.

[0030] Please refer to Figures 2a to 3b The semiconductor processing apparatus 100 includes a first chamber portion 110 and a second chamber portion 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from a periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending from a periphery of the second chamber plate 129.

[0031] The first chamber portion 110 is movable between an open position and a closed position relative to the second chamber portion 120. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 is relative. The first chamber portion 110 can be fixed while the second chamber portion 120 moves relative to it, or the second chamber portion 120 can be fixed while the first chamber portion 110 moves relative to it, or both the first chamber portion 110 and the second chamber portion 120 can move simultaneously, as long as the first chamber portion 110 and the second chamber portion 120 can move relative to each other. When the first chamber portion 110 is in the closed position relative to the second chamber portion 120, the flange 118 cooperates with the flange 128 to form a microchamber 140 between the first chamber plate 118 and the second chamber plate 128. The semiconductor wafer 400 to be processed can be accommodated in the microchamber 140, awaiting subsequent processing. When the first chamber portion 110 is in an open position relative to the second chamber portion 120 , the flange 118 is separated from the flange 128 , and the semiconductor wafer 400 to be processed can be taken out of or put into the microchamber 140 .

[0032] A first annular groove 116 is formed on the side of the first chamber portion 110 facing the microchamber 140, and a second groove 126 is formed on the side of the second chamber portion 120 facing the microchamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the microchamber, the first groove 116 and the second groove 126 jointly form an edge microprocessing space 130, and the outer edge of the semiconductor wafer 400 accommodated in the microchamber extends into the edge microprocessing space 130.

[0033] like Figures 2a to 3bAs shown, in this embodiment, the first groove 116 and the second groove 126 are annular grooves. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the microchamber, the wall surface 117 of the first chamber portion 110 located inside the first groove 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located inside the second groove 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed. The first groove 116 and the second groove 126 together enclose the closed, annular outer edge microprocessing space 130, and the outer edge portion of the semiconductor wafer 400 to be processed is accommodated in the edge microprocessing space 130.

[0034] Therefore, in this embodiment, the edge micro-processing space 130 can achieve selective processing of the entire outer edge portion of the semiconductor wafer 400 to be processed.

[0035] Of course, the first channel 116 and the second channel 126 can also be configured as arc-shaped channels with an arc angle less than 360 degrees. In this case, a closed, arc-shaped outer edge micro-processing space 130 with an arc angle less than 360 degrees is formed between the first channel 116 and the second channel 126. Accordingly, a portion of the outer edge of the semiconductor wafer 400 to be processed is accommodated within the edge micro-processing space 130. Therefore, in this case, the edge micro-processing space 130 only selectively processes the portion of the outer edge of the semiconductor wafer 400 to be processed.

[0036] The first chamber portion 110 has at least two edge processing through-holes 112 extending from the outside through the first chamber portion 110 to communicate with the edge micro-processing space 130. At least one edge processing through-hole serves as a fluid inlet, and at least one edge processing through-hole serves as a fluid outlet. In this embodiment, four edge processing through-holes are provided. Of course, the second chamber portion 120 may also be provided with edge processing through-holes communicating with the edge micro-processing space 130.

[0037] During application, a processing fluid can enter the edge micro-processing space 130 through an edge processing through-hole 112. The fluid entering the edge micro-processing space 130 can flow within the edge micro-processing space 130. At this time, the processing fluid can contact and process the outer edge portion of the semiconductor wafer 400 to be processed contained in the edge micro-processing space 130. The fluid that has processed the semiconductor wafer 400 to be processed can flow out through another edge processing through-hole 112, or through an edge processing through-hole provided on the second chamber portion 120 and connected to the edge micro-processing space 130. During the processing process, the processing fluid can be continuously or periodically introduced into the edge micro-processing space 130 through an edge processing through-hole 112. The fluid in the edge micro-processing space 130 can flow during the processing process, thereby speeding up the processing speed.

[0038] Of course, the treatment may be an etching treatment of the outer edge of the semiconductor wafer 400 to be processed to remove the thin film layer of the outer edge portion of the semiconductor wafer 400 to be processed, or it may be a selective cleaning of the outer edge of the semiconductor wafer 400 to be processed, etc.

[0039] Take the etching and removal of the thin film layer on the outer edge of the semiconductor wafer 400 to be processed as an example. Figures 1a to 1d and Figures 2a to 3b As shown, when it is necessary to corrode and remove the thin film layer on the first side and the second side of the outer edge of the semiconductor wafer 400 to be processed, it is only necessary to pass the corresponding processing fluid that has a corrosive effect on the thin film layer into the edge micro-processing space 130 through an edge processing through-hole 112. The processing fluid flows in the edge micro-processing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed, and chemically or physically reacts with the wafer surface of the wafer to be processed accommodated in the edge micro-processing space, so that the first edge surface, the second edge surface and the thin film layer 402 on the oblique edge of the outer edge of the semiconductor wafer 400 to be processed are continuously corroded and removed. As shown Figure 1d As shown, after processing is completed, the portion of the thin film layer 402 on the outer edge of the semiconductor wafer 400 that is contained within the edge micro-processing space 130 is etched away, exposing the first edge surface, second edge surface, and outer bevel edge of the substrate layer 401 on the outer edge of the semiconductor wafer 400. The fluid that has processed the semiconductor wafer 400 to be processed flows out through other edge processing through-holes.

[0040] As can be seen, based on the edge micro-processing space 130, the semiconductor processing apparatus 100 of this embodiment only consumes a small amount of processing fluid to achieve selective etching of the outer edge of a semiconductor wafer 400 to be processed, significantly reducing processing costs and the amount of waste liquid produced. Furthermore, compared to conventional dry-process apparatuses, the semiconductor processing apparatus 100 of this embodiment has significant advantages in terms of simple structure, ease of use, and low operator skill requirements.

[0041] It can be seen that the semiconductor processing device 100 provided in this embodiment can achieve selective processing of the outer edge of the semiconductor wafer 400 to be processed. In addition, by controlling the flow rate of the processing fluid in the semiconductor wafer 400 to be processed, the amount of processing fluid can be saved while ensuring the processing effect. Figure 2a to Figure 2b As shown, in this embodiment, the first chamber portion 110 further includes a first recessed portion 115 formed on the inner wall surface of the first chamber portion 110 facing the microchamber, and the first recessed portion is located inside the first groove 116. The second chamber portion 120 further includes a second recessed portion 125 formed on the inner wall surface of the second chamber portion 120 facing the microchamber, and the second recessed portion is located inside the second groove 126. The first recessed portion 115 and the second recessed portion 125 are also annular. When the second chamber portion 120 is located in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 to be processed is accommodated in the microchamber, a partial area of ​​the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner microspace, and a partial area of ​​the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner microspace. The first inner microspace and the second inner microspace are located inside the edge microprocessing space 130.

[0042] Correspondingly, the first chamber portion 110 has a first inner processing through-hole communicating with the first recessed portion 115, and the second chamber portion 120 has a second inner processing through-hole communicating with the second recessed portion 125. When the edge of the semiconductor wafer 400 is etched using the edge micro-processing space 130, liquid or gas, such as water or nitrogen, can be introduced into the first recessed portion 115 and the second recessed portion 125, i.e., into the first inner micro-space and the second inner micro-space, to prevent the liquid in the edge micro-processing space 130 from penetrating inward.

[0043] Likewise, the first recessed portion 115 and the second recessed portion 125 may also be arc-shaped.

[0044] Continue to refer to Figure 2a to Figure 2bAs shown, in this embodiment, when the second chamber portion 120 and the first chamber portion 110 are in the closed position, a micro chamber 140 is further formed in the middle thereof, the second chamber portion 120 has a middle processing through hole 123 communicating with the micro chamber 140, and the first chamber portion 110 has a middle processing through hole 113 communicating with the micro chamber 140.

[0045] References Figure 2b As shown, the first chamber portion 110 has a sealing joint 210 located outside the first groove 116, and the second chamber portion 120 has an engagement groove 122 corresponding to the sealing joint 210. The sealing joint 210 includes a guide surface 211 located at the end and an inner surface 212 located inside. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, the end of the sealing joint 210 extends into the engagement groove 122, and the end portion of the inner surface 212 thereof seals with the groove wall of the engagement groove 122. The upper end portion of the inner surface 212 forms the outer side surface of the outer edge micro-processing space 130. In addition, the sealing surface between the end portion of the inner surface 212 of the sealing joint 210 and the groove wall of the joint groove 122 is located below the outer edge micro-processing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. Such an arrangement can make the wall surface 117 of the first chamber portion 110 located on the inner side of the first groove 116 abut more tightly against the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located on the inner side of the second groove 126 abut more tightly against the second edge surface of the semiconductor wafer 400 to be processed, thereby preventing the corrosive liquid from penetrating inward.

[0046] exist Figure 2b In an embodiment, during the closing process of the second chamber portion 120 relative to the first chamber portion 110, the inner surface 212 of the sealing joint 210 can realize the center positioning of the semiconductor wafer 400, that is, if the center of the semiconductor wafer 400 deviates from the desired center when placed, then the inner edge surface 212 of the sealing joint 210 can also be pressed against the semiconductor wafer 140 so that its center is corrected to the desired center. In one example, when edge processing is performed, the center deviation of the semiconductor wafer 400 is required to be no more than 0.2 mm. By adopting the method of the present invention, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 can guide the sealing joint 210 into the joint groove 122 when the first chamber portion 110 and the second chamber portion 120 are closed. The sealing joint 210 can be stuck in the joint groove 122.

[0047] References Figure 2aAs shown, the first chamber portion 110 includes a positioning groove 114, and the second chamber portion 120 includes a positioning post 124, which can ensure that the first chamber portion 110 and the second chamber portion 120 are properly positioned when closed. During the closing process of the first chamber portion 110 and the second chamber portion 120, the positioning post 124 first engages with the positioning groove 114 to achieve initial positioning, and then the end of the sealing joint 210 extends into the joint groove 122.

[0048] In one embodiment, the semiconductor processing device 100 of the present invention is used to carry out a silicon oxide wafer edge etching process. Specifically, the method may include closing the cavity, HF acid etching, DIW rinsing, IPA rinsing, nitrogen drying, and opening the cavity. The specific processes of HF acid etching, DIW (deionized water) rinsing, and IPA (isopropyl alcohol) rinsing may be operated with reference to the above-described process. In particular, during the HF acid etching process, liquid or gas, such as water or nitrogen, may be introduced into the first recessed portion 115 and the second recessed portion 125 to prevent the liquid in the edge micro-processing space 130 from infiltrating inwardly.

[0049] Second embodiment

[0050] Please refer to Figures 4 to 6b , which shows a schematic structural diagram of a semiconductor processing device 200 provided by a second embodiment of the present invention, wherein: Figure 4 is a schematic cross-sectional view of a semiconductor processing device according to a first embodiment of the present invention; Figure 5 for Figure 4 An enlarged schematic diagram of circle B in FIG; Figure 6a for Figure 4 A bottom view of a first chamber portion of a semiconductor processing apparatus; Figure 6b for Figure 4 A top view of a second chamber portion of a semiconductor processing apparatus in FIG.

[0051] The semiconductor processing device 200 in the second embodiment has a structure that is largely identical to that of the semiconductor processing device 100 in the first embodiment, and therefore the identical parts thereof are labeled identically. The main difference between the two is that the sealing joint 310 of the semiconductor processing device 200 and the sealing joint 210 of the semiconductor processing device 100 have some differences in structure.

[0052] like Figure 5 As shown, the first chamber portion 110 has the sealing joint portion 310 located outside the first groove 116 , and the second chamber portion 120 has a joint groove 122 corresponding to the sealing joint portion 210 .

[0053] The sealing joint 310 includes a guide surface 311 at its distal end, an inner surface 312 at its inner upper end, and a protrusion 313 at its distal end. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, the distal end of the sealing joint 310 extends into the engagement groove 122, with the protrusion 313 sealingly engaging the groove wall of the engagement groove 122. The inner surface 312 forms the outer side of the outer micro-processing space 130. The inner surface 312 is spaced a distance from the outer edge of the semiconductor wafer 400.

[0054] The sealing surface formed by the protrusion 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge micro-processing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. Such an arrangement can make the wall surface 117 of the first chamber part 110 located on the inner side of the first groove 116 abut more tightly against the first side surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber part 120 located on the inner side of the second groove 126 abut more tightly against the second side surface of the semiconductor wafer 400 to be processed, thereby preventing the corrosive liquid from penetrating inward.

[0055] exist Figure 2b In the embodiment, during the closing process of the second chamber portion 120 relative to the first chamber portion 110, the protrusion 313 of the sealing joint 310 can realize the center positioning of the semiconductor wafer 140, that is, if the center of the semiconductor wafer 140 deviates from the desired center when it is placed, then the protrusion 313 of the sealing joint 310 can also be pressed against the semiconductor wafer 140 so that its center is corrected to the desired center.

[0056] Since there is still a distance between the inner surface 312 and the outer edge of the semiconductor wafer 400 , the semiconductor wafer 400 is not easily clamped by the sealing joint 310 when the second chamber portion 120 is separated from the first chamber portion 110 .

[0057] In another embodiment, the semiconductor wafer 400 may be centrally positioned without using the bumps 313 , that is, the bumps 313 may not contact the edge of the semiconductor wafer 400 . Instead, the center of the semiconductor wafer 400 may be centrally positioned using the edge of the wall of the first groove 116 .

[0058] Third embodiment

[0059] Figure 7a is a schematic cross-sectional view of a semiconductor processing device according to a third embodiment of the present invention; Figure 7b for Figure 7a An enlarged schematic diagram of circle D in FIG; Figure 8 Fig. 1 is a perspective view of a semiconductor processing device according to a first embodiment of the present application. Figure 7a Fig. 2 is a perspective view of a lower chamber portion of the semiconductor processing device according to the first embodiment of the present application.

[0060] Fig. 3 is a perspective view of a semiconductor processing device according to a second embodiment of the present application. Figure 7a Fig. 4 is a perspective view of a semiconductor processing device according to a third embodiment of the present application. 7b Fig. 5 is a perspective view of a semiconductor processing device according to a fourth embodiment of the present application. Fig. 6 is a perspective view of a semiconductor processing device according to a fifth embodiment of the present application.

[0061] Fig. 7 is a perspective view of a semiconductor processing device according to a sixth embodiment of the present application. Fig. 8 is a perspective view of a semiconductor processing device according to a seventh embodiment of the present application.

[0062] Fig. 9 is a perspective view of a semiconductor processing device according to an eighth embodiment of the present application. Figure 8 Fig. 10 is a perspective view of a semiconductor processing device according to a ninth embodiment of the present application. Fig. 11 is a perspective view of a semiconductor processing device according to a tenth embodiment of the present application.

[0063] Fig. 12 is a perspective view of a semiconductor processing device according to an eleventh embodiment of the present application. Figure 7a Fig. 13 is a perspective view of a semiconductor processing device according to a twelfth embodiment of the present application. Figure 8 Fig. 14 is a perspective view of a semiconductor processing device according to a thirteenth embodiment of the present application. Fig. 15 is a perspective view of a semiconductor processing device according to a fourteenth embodiment of the present application.

[0064] In one embodiment, the coefficient of thermal expansion of the main body portion at room temperature is less than the coefficient of thermal expansion of the embedded portion, such as the room temperature can be 10-30 degrees. More specifically, the embedded portion can be made of PTFE (polytetrafluoroethylene) material, and the main body portion can be made of PVC (polyvinyl chloride) material. During manufacturing, the low-temperature embedded portion is placed into the fitting groove of the main body portion, and when it reaches room temperature, the embedded portion expands to fill the fitting groove, thereby achieving the assembly of the embedded portion and the main body portion. Subsequently, the first chamber portion or the second chamber portion can be made of the material integrated by the embedded portion and the main body portion.

[0065] Because there can be a temperature difference between the temperature at which the first chamber portion and the second chamber portion are manufactured and the temperature at which the first chamber portion and the second chamber portion are used, such as a difference of 3-10 degrees. The coefficient of thermal expansion of PTFE material is relatively large at room temperature, so the size change of the first chamber portion and the second chamber portion made of PTFE material due to the temperature difference between manufacturing and use will be relatively large, which can cause the problem of excessive error. For example, when performing edge etching processing, the diameter of the etched edge line of the semiconductor wafer can have a certain error due to the thermal expansion and contraction of the first chamber portion and the second chamber portion, affecting the etching precision, which in some cases is not acceptable. In the present application, only the embedded portion is made of PTFE material, and the main body portion is made of PVC material, which has a smaller coefficient of thermal expansion than PTFE material at room temperature. Because the embedded portion is reduced in size and is clamped by the main body portion, the thermal expansion of the embedded portion is inhibited by the main body portion, thereby reducing the impact of the temperature difference between manufacturing and use on the first chamber portion and the second chamber portion. In addition, PVC material is cheaper than PTFE material, and the method of the present application can reduce the manufacturing cost.

[0066] The first chamber portion and / or the second chamber portion in the first embodiment and the second embodiment can also be combined by the embedded portion and the main body portion, at which time the first groove can be formed on the embedded portion of the first chamber portion, the second groove can be formed on the embedded portion of the second chamber portion, the sealing joint portion can be formed on the embedded portion of the first chamber portion, and the joint groove can be formed on the embedded portion of the second chamber portion.

[0067] In another embodiment, only one of the first chamber portion and the second chamber portion can be combined by the embedded portion and the main body portion.

[0068] In another alternative embodiment, the fitting groove can be circular, the embedded portion can be circular to match the fitting groove, and when the semiconductor wafer is contained in the microchamber, the middle portion and the edge portion of the semiconductor wafer correspond to the surface of the embedded portion.

[0069] In another alternative embodiment, a semiconductor processing device including a chamber portion formed by combining an embedded portion and a main body portion can be used not only to perform edge processing on semiconductor wafers, but also to perform other processing on semiconductor wafers, such as cleaning, drying, and etching of the entire surface.

[0070] The above description fully discloses the specific embodiments of the present invention. It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims. Accordingly, the scope of the claims of the present invention is not limited to the specific embodiments described above.

Claims

1. A semiconductor processing device, characterized in that: It includes: a first chamber portion; a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the microchamber; and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in; At least one of the first chamber portion and the second chamber portion includes a main body portion and an embedding portion, wherein a fitting groove is formed on a surface of the main body portion facing the micro chamber, and the embedding portion is embedded in the fitting groove to form a whole with the main body portion. The thermal expansion coefficient of the main body within the range of 10-30 degrees is smaller than the thermal expansion coefficient of the embedded part within the range of 10-30 degrees. The low-temperature embedded part is placed into the embedding groove of the main body. When it is at room temperature, the embedded part will expand and fill the embedding groove. When the semiconductor wafer is accommodated in the microchamber, the edge portion of the semiconductor wafer corresponds to the surface of the embedded portion, and the middle portion of the semiconductor wafer corresponds to the surface of the main portion. Alternatively, when the semiconductor wafer is accommodated in the microchamber, both the middle portion and the edge portion of the semiconductor wafer correspond to the surface of the embedded portion.

2. The semiconductor processing device according to claim 1, wherein The fitting groove is annular, and the embedded portion is annular to match the fitting groove; or, The fitting groove is circular, and the embedded portion is circular and matches the fitting groove.

3. The semiconductor processing device according to any one of claims 1 to 2, characterized in that: The first chamber portion has a first groove, and the second chamber portion has a second groove. When the second chamber portion is in the closed position relative to the first chamber portion and a semiconductor wafer is accommodated in the microchamber, the first groove and the second groove are communicated and form an edge microprocessing space together with the edge of the semiconductor wafer. The outer edge of the semiconductor wafer accommodated in the microchamber extends into the edge microprocessing space. The edge microprocessing space is communicated with the outside through an edge processing through-hole, and fluid enters or flows out of the edge microprocessing space through the edge processing through-hole. The first groove is formed on the embedded portion of the first cavity portion, and the second groove is formed on the embedded portion of the second cavity portion.

4. The semiconductor processing apparatus according to claim 3, wherein: The first chamber portion has a sealing joint portion located outside the first groove, and the second chamber portion has a joint groove corresponding to the sealing joint portion. The sealing joint portion is formed on the embedded portion of the first chamber portion, and the joint groove is formed on the embedded portion of the second chamber portion. The first edge surface, the second edge surface and the outer end bevel surface of the outer edge of the semiconductor wafer are exposed to the edge micro-processing space, one or more of the edge processing through holes serve as a fluid inlet, and one or more of the edge processing through holes serve as a fluid outlet. The edge micro-processing space is annular or arc-shaped, and the outer edge of the semiconductor wafer extends into the edge micro-processing space. The edge micro-processing space is a closed space and communicates with the outside through an edge processing through-hole; The top surface of the inner sidewall of the first groove abuts against the first edge surface of the semiconductor wafer near the first chamber portion, and the top surface of the inner sidewall of the second groove abuts against the second edge surface of the semiconductor wafer near the second chamber portion.

5. The semiconductor processing apparatus according to claim 4, wherein: The first chamber portion further includes a first recessed portion formed on the inner wall surface of the first chamber portion facing the microchamber, and the first recessed portion is located on the inner side of the first groove. The second chamber portion further includes a second recessed portion formed on the inner wall surface of the second chamber portion facing the microchamber, and the second recessed portion is located on the inner side of the second groove. When the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated in the microchamber, a partial area of ​​the second edge surface of the semiconductor wafer covers the top of the second recessed portion to form a second inner microspace, and a partial area of ​​the first edge surface of the semiconductor wafer covers the top of the first recessed portion to form a first inner microspace. The first inner microspace and the second inner microprocessing space are located on the inner side of the edge microprocessing space. The first chamber portion includes a first inner processing through-hole communicating with the first recessed portion, and the second chamber portion includes a second inner processing through-hole communicating with the second recessed portion.

6. The semiconductor processing apparatus according to claim 5, wherein: The first recessed portion and the second recessed portion are annular or arc-shaped. When the edge of the semiconductor wafer is corroded using the edge micro-processing space, liquid or gas is introduced into the first recessed portion and the second recessed portion to prevent the liquid in the edge micro-processing space from penetrating inward.

7. The semiconductor processing apparatus according to claim 4, wherein: The sealing joint portion includes an inner edge surface located on the inner side. When the second chamber portion is located in the closed position relative to the first chamber portion, the end of the sealing joint portion extends into the joint groove, and the end portion of its inner edge surface is sealed with the groove wall of the joint groove, and the upper end portion of its inner edge surface forms the outer side surface of the edge micro-processing space.

8. The semiconductor processing apparatus according to claim 7, wherein: A sealing surface between the end portion of the inner edge surface of the sealing joint and the groove wall of the joint groove is located below the edge micro-processing space, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer.

9. The semiconductor processing apparatus according to claim 7, wherein: During the closing process of the second chamber part relative to the first chamber part, the inner edge surface of the sealing joint realizes the center positioning of the semiconductor wafer. If the center of the semiconductor wafer deviates from the expected center when placed, the inner edge surface of the sealing joint presses against the semiconductor wafer so that its center is corrected to the expected center.

10. The semiconductor processing apparatus according to claim 4, wherein: The first chamber portion includes a positioning groove, and the second chamber portion includes a positioning column. The positioning column cooperates with the positioning groove so that the first chamber portion and the second chamber portion can be correctly positioned when closed.

11. The semiconductor processing apparatus according to claim 4, wherein: The sealing joint includes an inner edge surface located at the inner upper end and a protrusion located at the inner end. When the second chamber portion is located in the closed position relative to the first chamber portion, the end of the sealing joint extends into the joint groove, and its protrusion is sealed with the groove wall of the joint groove. Its inner edge surface forms the outer side surface of the edge micro-processing space, and the inner edge surface is still separated from the outer edge of the semiconductor wafer by a distance.

12. The semiconductor processing apparatus according to claim 11, wherein: A sealing surface formed by the protrusion of the sealing joint portion and the groove wall of the joint groove is located below the edge micro-processing space, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer.

13. The semiconductor processing apparatus according to claim 11, wherein: During the closing process of the second chamber part relative to the first chamber part, the protrusion of the sealing joint part realizes the center positioning of the semiconductor wafer. If the center of the semiconductor wafer deviates from the expected center when it is placed, the protrusion of the sealing joint part presses against the semiconductor wafer so that its center is corrected to the expected center.

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