Optical sensing system and digital sampled signal calculation method

Abstract

The embodiment of the specification provides an optical sensing system and a digital sampling signal calculation method. The system comprises a slope signal generator, a digital logic circuit and a plurality of column circuits; the slope signal generator is used to generate a slope signal and transmit the slope signal to the column circuits; the slope signal comprises a signal with gradually changing signal strength over time, and the signal strength change speed of the slope signal corresponds to the amplification multiple of a photosensitive electric signal; one of the plurality of column circuits is used to receive the photosensitive electric signal, and output a photosensitive gain signal to the digital logic circuit according to the slope signal and the photosensitive electric signal; the photosensitive gain signal comprises a digital signal corresponding to the photosensitive electric signal after signal strength amplification; and the digital logic circuit is used to calculate a digital sampling signal according to the photosensitive gain signal. The above system reduces the area overhead of the chip corresponding to the optical sensing system, and improves the application range of the corresponding optical sensing chip.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of optical sensing technology, and in particular to an optical sensing system and a method for calculating digital sampling signals. Background Technology

[0002] CMOS image sensors (CIS) are used to generate corresponding electrical signals based on light intensity, thereby achieving optical sensing. They are used in camera modules and photosensitive modules. Especially in recent years, with the improvement of devices such as smartphones, CMOS image sensors have also been increasingly widely used in the field of optical fingerprint recognition.

[0003] In current CMOS image sensors, photodiodes perform photoelectric conversion during the exposure stage to generate signal charges. These charges are picked up by MOSFET gates and converted into voltage signals. Then, a programmable gain amplifier (PGA) amplifies the voltage signal to obtain the photosensitive voltage and reset voltage. Subtracting these two voltages yields the corresponding analog signals, which are then converted to digital signals by an analog-to-digital converter (ADC) to ultimately produce the digital signals used for image processing.

[0004] However, the aforementioned structure requires separate PGAs to process the photosensitive signals of each pixel unit, increasing the complexity of the circuit structure and the chip's area overhead. This is especially problematic in portable devices such as smartphones and wearable devices, where the compact design means that an excessively large optical sensor chip not only increases design costs but also impacts processing speed. Therefore, adjusting the chip structure to reduce chip area while maintaining performance is a pressing issue that needs to be addressed. Summary of the Invention

[0005] The purpose of the embodiments in this specification is to provide an optical sensing system and a digital sampling signal calculation method to solve the technical problem of how to effectively reduce the area of ​​optical sensing chips.

[0006] To address the aforementioned technical problems, this specification provides an optical sensing system comprising a ramp signal generator, a digital logic circuit, and multiple column circuits. The ramp signal generator generates a ramp signal and transmits it to the column circuits. The ramp signal includes a signal whose intensity changes gradually over time, with the rate of change corresponding to the amplification factor of the photosensitive photoelectric signal. One of the multiple column circuits receives the photosensitive photoelectric signal and outputs a photosensitive gain signal to the digital logic circuit based on the ramp signal and the photosensitive photoelectric signal. The photosensitive gain signal includes a digital signal corresponding to the amplified photosensitive photoelectric signal. The digital logic circuit calculates a digital sampling signal based on the photosensitive gain signal.

[0007] This specification also proposes a method for calculating a digital sampling signal, comprising: a ramp signal generator generating a ramp signal; the ramp signal including a signal whose signal strength gradually changes over time, the rate of change of the ramp signal's signal strength corresponding to the amplification factor of the photosensitive photoelectric signal; the ramp signal generator transmitting the ramp signal to a column circuit; the column circuit generating a photosensitive gain signal based on the ramp signal and the photosensitive photoelectric signal; the photosensitive gain signal including a digital signal corresponding to the photosensitive photoelectric signal after signal strength amplification; the column circuit transmitting the photosensitive gain signal to a digital logic circuit; and the digital logic circuit calculating a digital sampling signal based on the photosensitive gain signal.

[0008] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification, through the aforementioned optical sensing system and digital sampling signal calculation method, control the amplification factor of the photoelectric signal based on the slope of the ramp signal generated by the ramp signal generator. This allows the array circuit to generate a photosensitive gain signal based on the ramp signal and the photoelectric signal, achieving signal strength amplification without the need for an additional PGA. Ultimately, the digital sampling signal can be calculated using the photosensitive gain signal to determine the corresponding optical signal intensity. The above system achieves signal amplification while eliminating the PGA, simplifying the structure of the optical sensing system, thereby reducing the area overhead of the corresponding chip, expanding the application range of the corresponding optical sensing chip, and ensuring the effectiveness of subsequent image processing. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a structural diagram of an optical sensing system according to an embodiment of this specification;

[0011] Figure 2 This is a structural diagram of a ramp signal amplifier according to an embodiment of this specification;

[0012] Figure 3A This is a structural diagram of a comparator module according to an embodiment of this specification;

[0013] Figure 3B This is a structural diagram of a comparator module according to an embodiment of this specification;

[0014] Figure 4 This is a schematic diagram illustrating a change in the negative terminal signal according to an embodiment of this specification;

[0015] Figure 5A This is a schematic diagram illustrating a change in the original signal according to an embodiment of this specification;

[0016] Figure 5B This is a schematic diagram illustrating an example of amplified signal variation in this specification.

[0017] Figure 5C This is a schematic diagram illustrating the signal change for adjusting the slope of a ramp signal according to an embodiment of this specification.

[0018] Figure 6A This is a schematic diagram illustrating a change in the original signal according to an embodiment of this specification;

[0019] Figure 6B This is a schematic diagram illustrating an example of amplified signal variation in this specification.

[0020] Figure 6C This is a schematic diagram illustrating the signal change for adjusting the slope of a ramp signal according to an embodiment of this specification.

[0021] Figure 7A This is a structural diagram of a comparator module according to an embodiment of this specification;

[0022] Figure 7B This is a structural diagram of a comparator module according to an embodiment of this specification;

[0023] Figure 8 This is a schematic diagram illustrating a signal change at a signal terminal according to an embodiment of this specification;

[0024] Figure 9 This is a flowchart illustrating a digital signal calculation method as an embodiment of this specification. Detailed Implementation

[0025] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0026] To address the aforementioned technical problems, this specification introduces an optical sensing system according to an embodiment. For example... Figure 1 As shown, the optical sensing system may include a ramp signal generator 120, a digital logic circuit 140, and multiple column circuits 131-133.

[0027] In some embodiments, the optical sensing system further includes a pixel array 110. Specifically, the pixel units can be arranged in multiple rows and columns to form the pixel array 110. The pixel units are used to sense light and generate corresponding electrical signals. Figure 1 As shown, an example of an optical sensing system including pixel unit 111, pixel unit 112, and pixel unit 113 is given. In practical applications, the number, arrangement, and other features of the pixel units in the pixel array 110 can be set as needed.

[0028] In the case where the pixel array 110 includes multiple rows and columns of pixel units, each column circuit in the optical sensing system can correspond to a column of pixel units in the pixel array 110. For example... Figure 1 As shown, pixel units 111, 112, and 113 respectively represent different columns in pixel array 110, and correspond to column circuits 131, 132, and 133 respectively. It should be noted that the use of columns to describe the correspondence between pixel units and column circuits is only for better illustration; in actual applications, the arrangement direction of pixel units corresponding to column circuits is not restricted.

[0029] When the pixel array 110 is exposed, the light received by each column of pixel units 111-113 in the pixel array 110 may vary depending on the scene corresponding to the array. Based on parameters such as the intensity and frequency of the light, the signals generated by different pixel units will also change accordingly. After processing the signals generated by each column of pixel units 111-113, image processing can be performed using the processed signals to achieve different functions such as photography, fingerprint recognition, and photosensing.

[0030] In the embodiments of this specification, pixel units 111-113 can generate corresponding photoelectric signals after receiving light signals. These photoelectric signals can then be used to reflect the corresponding parameters of the light. The photodiodes (PDs) in pixel units 111-113 generate signal charges based on photoelectric conversion. After exposure, the transfer gate (TG) is opened, allowing the signal charges to be transferred to the floating diffusion layer for accumulation. The charge is then picked up by the MOSFET gate (i.e., source follow, SF), which amplifies the signal, converting the charge signal into a voltage signal, thereby obtaining the photoelectric signal.

[0031] The specific methods and steps for generating photoelectric signals using pixel units 111-113 can be set and adjusted based on the actual application situation, and are not limited to the above description, so they will not be elaborated here.

[0032] In practical applications, to capture light, pixel units 111-113 can also be configured with corresponding lens modules based on a hierarchical structure. For example, in an optical sensing system, physical lenses and filters can be sequentially arranged based on their vertical relationship to achieve effects such as light focusing and filtering. Specific application methods can be configured according to the actual application requirements, and will not be elaborated further here.

[0033] It should be noted that in practical applications, the optical sensing system can integrate the pixel array 110, or it can exist as an independent signal processing module without the pixel array 110. The specific application method can be adjusted based on the needs of those skilled in the art.

[0034] The ramp signal generator 120 is used to generate a ramp signal, which can be a signal that changes gradually over time. In this embodiment, the rate of change of the ramp signal strength over time is used to adjust the amplification factor of the photosensitive signal. Preferably, to facilitate control of the amplification factor based on the rate of change of the ramp signal, the ramp signal strength can change with time at a fixed rate, i.e., the relationship between the ramp signal strength and time can be a linear function. Specifically, the ramp signal strength can either ramp up or ramp down over time; there is no limitation on this. In practical applications, for ease of calculation, the signal strength can be expressed as a voltage value.

[0035] In some implementations, the circuit (not shown) includes a configuration register corresponding to the ramp signal generator 120. This configuration register can pre-store corresponding parameter values. The magnitude of these parameter values ​​can control the switching circuit in the ramp signal generator 120 to adjust the rate of change of the signal strength of the generated ramp signal. When the ramp signal generator 120 uses appropriate processing logic to determine the output ramp signal based on the initial signal, the ramp signal is adjusted by changing the preset parameter values ​​in the configuration register. This allows the adjusted ramp signal to change its slope based on the magnitude of the parameter values.

[0036] In some implementations, the ramp signal generator 120 includes a capacitor whose capacitance value is used to adjust the rate of change of the ramp signal strength.

[0037] In some other embodiments, the ramp signal generator 120 is provided with a current source, and the signal strength change rate of the ramp signal can be adjusted by adjusting the magnitude of the current output from the current source to the ramp signal generator 120.

[0038] The structure of the ramp signal generator 120 will be further described using a specific example, such as... Figure 2 The diagram shows a schematic of a ramp signal generator 120. The ramp signal generator 120 includes multiple current sources 121, multiple capacitors 122, resistors 123, a comparator 124, and multiple switches 125 and 126. The ramp signal generator 120 can be an integrator, and its output voltage is expressed as follows: In the formula, V out Let be the voltage (analog quantity) of the output ramp signal, R be the resistance of resistor 123, C be the total capacitance of capacitor 122, and i(t) be the total current input to the ramp signal generator from several current sources 121, which is generally a constant value. With the current i constant, the integral over a constant becomes a linear function of time, causing the magnitude of the output ramp signal voltage to increase or decrease at a fixed rate with time.

[0039] In one embodiment of the present invention, the value of the configuration register in the digital circuit (not shown) can be used to control the switch 125 to adjust the number of connected capacitors 122, thereby adjusting the total capacitance value C, which can change the slope of the ramp signal. Alternatively, the value of the configuration register can be used to control the switch 126 to adjust the number of connected current sources 121 to control the current value i, which can also change the slope, thereby adjusting the rate of change of the signal strength of the ramp signal.

[0040] In practical applications, one of the capacitor value C and the current value i can be selected for adjustment, or both can be combined to adjust the rate of change of the ramp signal strength. There are no restrictions on this.

[0041] Based on the above description, in the optical sensing system, each column of pixel units 111-113 corresponds to a column circuit 131-133. After generating a photoelectric signal, the pixel unit can transmit the photoelectric signal to the column circuit 131-133. Correspondingly, after generating a ramp signal, the ramp signal generator 120 can also transmit the ramp signal to the column circuit 131-133.

[0042] After receiving the ramp signal and the photoelectric signal (analog signal), the column circuits 131-133 can output a photosensitive gain signal (digital signal). The photosensitive gain signal includes the digital signal corresponding to the photoelectric signal after signal intensity amplification. After acquiring the photoelectric signal, the column circuits 131-133 of this invention can amplify the photoelectric signal and perform analog-to-digital conversion to obtain the corresponding digital signal (i.e., the photosensitive gain signal). Traditional image sensors require amplification of the photoelectric signal (which is an analog signal) through a PGA circuit, calculation of the analog difference between the photoelectric signal and the reset signal, and finally analog-to-digital conversion of this difference. In another embodiment described later in this specification, the column circuits 131-133 can amplify and convert the photoelectric signal, and can also amplify and convert the reset signal. The subsequent digital logic circuit 140 then directly calculates the difference between the digital signals to obtain the corresponding digital sampling signal.

[0043] Since the embodiments in this specification achieve signal amplification based on the slope of the ramp signal, compared with traditional CMOS image sensors, there is no need to set up an additional PGA circuit in the column circuit to achieve signal gain, thus reducing area overhead.

[0044] In some implementations, each column circuit 131-133 includes a comparator module and a counter.

[0045] The comparator module can compare the analog voltage values ​​of the signals coupled to the two input terminals. The comparator module can also continuously output a specific signal. Correspondingly, the two input terminals of the comparator module receive the ramp signal and the photoelectric signal generated by the pixel unit (e.g., pixel unit 111) corresponding to the column circuit (e.g., column circuit 131). When the input ramp signal changes to the same voltage as the photoelectric signal, the signal output by the comparator module flips to indicate that the voltages of the two received signals are equal.

[0046] The structure and working principle of the comparator module are described below with reference to the accompanying drawings.

[0047] Figure 3A This is a schematic diagram of a comparator module during the reset phase. During the reset phase, the left electrode of the positive capacitor 221 of the comparator module 210 is not connected to the photoelectric signal V. sig Instead, it's the reset electrical signal V ph The left plate of the negative terminal capacitor 222 of comparator module 210 is connected to the ramp signal V. ramp During the reset phase, the ramp signal V ramp The voltage is maintained at its initial value, i.e., the reset phase voltage V. ramp_rst . Figure 3B This is a schematic diagram of a comparator module in the comparison phase, wherein, in the comparison phase, the signal connected to the positive terminal of the comparator module 210 is switched to a photoelectric signal V. sig The ramp signal V at the negative end ramp Voltage from voltage value V ramp_rst The comparison module 210 also includes self-bias switches 231 and 232. During the reset phase, self-bias switches 231 and 232 are closed to eliminate self-offset; during the comparison phase, self-bias switches 231 and 232 are open.

[0048] like Figure 3A As shown, during the reset phase of comparator module 210, the voltage across the left plate of capacitor 221 at the positive input terminal of comparator module 210 is V. ph The left plate of capacitor 222 at the negative input terminal is the voltage V during the reset phase. ramp_rst The right plates of capacitors 221 and 222 at the positive and negative terminals can be reset to a preset voltage value due to the closure of self-bias switches 231 and 232. Assuming the reset voltage value of the right plates of capacitors 221 and 222 at both terminals is the bias voltage V... sf That is, the positive and negative terminals of the comparator module are both biased by voltage V during the reset phase. sf In practical applications, the reset voltage values ​​for the positive and negative terminals can be different, and there is no restriction on this. At the end of the reset phase, self-bias switches 231 and 232 are open. Since there are no other charge discharge paths, the voltage on the right plate of the positive terminal capacitor 221 and the negative terminal capacitor 222 will remain at the bias voltage V. sf .

[0049] When the comparison phase begins, at the instant that self-bias switches 231 and 232 are opened, the right plates of both positive and negative capacitors 221 and 222 are at their bias voltage V. sf The voltage value corresponding to the left plate of the positive terminal capacitor 221 of comparator module 210 is determined by V. ph The voltage value V of the photoelectric signal jumps to the sensor.sig Since self-bias switches 231 and 232 are open at this time, neither the right plate of the positive capacitor 221 nor the negative capacitor 222 has a charge discharge path. Therefore, their voltage changes will follow the voltage change of their respective left plates. In other words, the voltage change of the right plate of the capacitor will be the same as the voltage change of the left plate. The voltage change of the left plate of the positive capacitor 221 is V. sig -V ph Therefore, at the initial moment of the comparison phase, the voltage value of the right plate of the positive terminal capacitor 221 of the comparator module 210 jumps to V. sf +(V sig -V ph Similarly, at this time, the voltage value of the left plate of the negative capacitor 222 is changed from V. ramp_rst Jump to V ramp_start Then the voltage change of the right plate of the negative capacitor 222 is V. sf +(V ramp_start -V ramp_rst ).

[0050] Due to the ramp signal V ramp It is a signal that changes gradually over time. Afterwards, the voltage on the right plate of the negative capacitor 222 (i.e., the voltage value at the negative input terminal of comparator module 210) is based on the ramp signal V. ramp Changes ( Figure 4 The voltage value of the ramp signal Vramp shown is from V ramp_start Scroll down (rampdown) to see the changes. For example... Figure 4 The diagram shows the change of the voltage value of the right plate of a negative capacitor 222 (i.e., the voltage value at the negative input terminal of comparator module 210) over time. The dashed line represents the voltage value of the right plate of the positive capacitor 221 (i.e., the voltage value at the positive input terminal of comparator module 210), and the solid line represents the voltage value of the right plate of the negative capacitor (i.e., the voltage value at the negative input terminal of comparator module 210). The ramp signal V is connected to the left plate of the negative capacitor 222. ramp As time decreases to a certain time t1 (i.e. Figure 4 At the intersection of the dashed and solid lines, the voltage on the right plate of capacitor 222 at the negative terminal simultaneously drops to V. sf +(V sig -V ph When the voltage values ​​of the input signals at the positive and negative terminals of the comparator module 210 are the same, the output signal of the comparator module 210 will undergo a level flip.

[0051] The following section describes the principle of signal amplification using the rate of change of signal strength of a ramp signal, based on the specific structure of comparator module 210. One input terminal of comparator module 210 receives a photoelectric signal V. sigThe other input terminal receives a ramp signal V. ramp To make it easier to understand, a bias voltage V can be set. sf It is 0.

[0052] As attached Figure 5A In order to detect the photoelectric signal V sig When processing is performed, the comparator module 210 corresponds to the ramp signal V. ramp A schematic diagram of the voltage change of the input signal at the input terminal. For ease of description, the ramp signal V is used in this section. ramp The rate of change over time is expressed as a slope. For example... Figure 5A As shown, the ramp signal V ramp The slope of the change is a. Before time t0 is the reset phase. At time t0, the comparison phase begins. After entering the comparison phase, after time T, the signal voltages at the two input terminals of comparator module 210 are equal, and the output signal of comparator module 210 flips.

[0053] Figure 5B To amplify the voltage value of the photoelectric signal by two times to 2V using a PGA circuit, following the traditional method... sig Then, comparator module 210 corresponds to the ramp signal V ramp A schematic diagram showing the voltage change of the input signal at the input terminal. It can be seen that after 0.5T, the signal voltages at the two input terminals of comparator module 210 are equal. The counter of column circuit 131 starts from the ramp signal V. ramp The counting begins at the initial time t0 and stops at the time t1 when the output signal of the comparator module 210 flips, thus obtaining a count value. Based on this count value, a photosensitive gain signal is output. The time length T between time t0 and time t1 corresponds one-to-one with the digital signal (i.e., photosensitive gain signal) output by the analog-to-digital converter 131. That is to say, there is a correspondence between time T and the magnitude of the digital value of the photosensitive gain signal.

[0054] Figure 5C In this embodiment of the invention, the slope of the ramp signal is adjusted to 2a to maintain the photoelectric signal V. sig With the analog voltage value remaining constant, the diagram showing the voltage change of the input signal at the input terminal of the comparator module 210 corresponding to the ramp signal shows that, also after a time of 0.5T, Figure 5C When the dashed and solid lines intersect, the signal voltages at the two input terminals of comparator module 210 are equal, causing the output of comparator module 210 to flip, controlling the counter to stop counting and generate a count value. Therefore, Figure 5C The ramp signal V ramp Increasing the slope to change the timing of the flip of the comparator module 210 output signal is equivalent to Figure 5BDirect amplification of photoelectric signal V sig The effect of voltage amplitude.

[0055] Figure 6A , Figure 6B , Figure 6C This is a schematic diagram illustrating the ramp-up of the voltage value of the ramp signal over time. Similarly, Figure 6A The original photoelectric signal V is targeted in the middle. sig After time T, the signal voltages at the two input terminals of comparator module 210 are equal; Figure 6B The 2V sensor signal after being amplified by two times sig After a time of 2T, the signal voltages at the two input terminals of comparator module 210 are equal; Figure 6C For a ramp signal with a slope of 0.5a, the signal voltages at the two input terminals of the comparator module are equal after a time of 2T, which is equivalent to... Figure 6B Directly transmit the photoelectric signal V sig The effect is magnified twice.

[0056] In practical applications, the ramp signal can be selected to increase or decrease over time as needed, and there are no restrictions on this.

[0057] Based on the above signals, it can be seen that the comparator module, through the sensing of photoelectric signal V... sig and ramp signal V ramp A voltage comparison is performed, and when the two values ​​are equal, the output signal flips (at the intersection of the dashed and solid lines) to control the count value of the subsequent counter. In other words, the circuit uses both a comparator module and a counter to simultaneously control the measured photoelectric signal V. sig The signal amplitude is amplified and the analog-to-digital conversion is performed to obtain the corresponding photosensitive gain signal.

[0058] The following discussion covers the signal input method of comparator module 210. Figures 3A-4 In some embodiments, comparator module 210 may include a first input terminal and a second input terminal. The first and second input terminals are coupled to a bias voltage V during the reset phase. sf The first input terminal is coupled to the photoelectric signal V during the comparison phase. sig The second input terminal is coupled to the ramp signal V during the comparison phase. ramp After the comparison phase begins, comparator module 210 compares the signal voltages at the two input terminals and measures the photoelectric signal V. sig and ramp signal V ramp The switching occurs when the voltage values ​​are the same. Figures 4-6C The intersection of the dashed and solid lines is flipped. It is worth noting that, in the aforementioned... Figure 3A and 3B In one embodiment, during the comparison phase, the photoelectric signal Vsig and ramp signal V ramp The problem with this connection method is that the positive and negative input terminals of the comparator module 210 are connected respectively. This is because the sampled photoelectric signal V... sig The voltage values ​​are different, therefore Figure 4 ΔV = V in the middle jump sig -V ph It is not a fixed quantity, so the flip point of the comparator module (the intersection of the dashed and solid lines) is not fixed. This requires the input common-mode range of the comparator module to cover all cases, which increases the design difficulty of the comparator module.

[0059] To address the aforementioned issues, some other implementations of the comparator module include a first input and a second input; the first input is coupled to a reference voltage V. ref (This reference voltage has a fixed level). The second input terminal is coupled to the photoelectric signal V during the reset phase. sig And in the comparison phase, the ramp signal V is coupled. ramp The output signal of the comparator module flips when the voltage at the second input terminal changes to be the same as that at the first input terminal.

[0060] This implementation method is described in detail below, utilizing... Figure 7A The structure of the comparator module in the above embodiment will be further described. The first input terminal and the second input terminal of the comparator module 610 correspond to the positive terminal and the negative terminal, respectively. The first input terminal is always coupled to the reference voltage V. ref (Grounded or fixed level). The second input terminal is coupled to the photoelectric signal during the reset phase and to the ramp signal during the comparison phase. That is, during the reset phase, switch 621 is closed, switch 622 is open, and the photoelectric signal V... sig Coupled to the second input terminal; during the comparison phase, switch 621 is open, switch 622 is closed, and the ramp signal V... ramp It is coupled to the second input terminal. The comparator module 610 also includes a self-bias switch 623 and a self-bias switch 624. During the reset phase, the self-bias switches 623 and 624 are closed to eliminate their own offset; during the comparison phase, the self-bias switches 623 and 624 are open. Figure 7A The image shows the state of comparator module 610 during the reset phase. Figure 7B The diagram shows the state of comparator module 610 during the comparison phase. The positive and negative terminals of comparator module 610 are also connected to a positive capacitor 631 and a negative capacitor 632, respectively.

[0061] Figure 7A , Figure 7B In this example, the positive terminal of the comparator module 610 is used as the first input terminal and the negative terminal as the second input terminal. However, this is not a restriction in actual applications.

[0062] During the reset phase of comparator module 610, the voltage across the left plate of the positive capacitor 631 of comparator module 610 is the reference voltage value V. ref The voltage across the left plate of the negative capacitor 632 is the voltage value V of the photoelectric signal. sig The right plates of both positive capacitor 631 and negative capacitor 632 are reset to their pre-designed voltage values. Assume the reset voltage of the right plate of negative capacitor 632 is the bias voltage V. sf The voltage at which the right plate of the positive capacitor 631 is reset is also the bias voltage V. sf At the end of the reset phase, self-bias switches 623 and 624 are open. Since there are no other charge discharge paths, the voltage across the right plates of the positive capacitor 631 and the negative capacitor 632 will remain at the bias voltage V. sf .

[0063] Once the comparison phase begins, the signal coupled to the negative terminal of comparator module 610 is switched to the ramp signal V via switches 621 and 622. ramp The voltage value corresponding to the left plate of the negative capacitor 632 of the comparator module is V. sig Jump to ramp signal V ramp The initial voltage value V ramp_start Since both self-biasing switches 623 and 624 are open at this time, the right plate of the negative capacitor 632 has no charge discharge path, and therefore will change in accordance with the voltage change of the left plate. Because the voltage change of the left plate of the negative capacitor 632 is V... ramp_start -V sig Therefore, at the initial moment of the comparison phase, the voltage value of the right plate of the negative terminal capacitor 632 of the comparator module 610 jumps to V. sf +(V ramp_start -V sig The voltage value of the left plate of the positive capacitor 631 does not change after entering the comparison phase; it remains the fixed reference voltage V. ref Therefore, the voltage on the right plate of the positive capacitor 631 will not change and will remain at the bias voltage V. sf .

[0064] Due to the ramp signal V ramp It is a signal that changes gradually over time. Afterwards, the voltage value of the right plate of the negative capacitor 632 is based on the ramp signal V. ramp The scrolling (upward ramp-up or downward ramp-down) changes the format. For example... Figure 8The diagram shows the variation of the voltage value at the right electrode of a negative capacitor 632 (i.e., the voltage value at the negative input terminal of comparator module 610) over time. The solid line represents the voltage value at the right electrode of the negative capacitor 632 (i.e., the voltage value at the negative input terminal of comparator module 610) under the ramp signal V. ramp When the voltage value decreases over time to a certain moment t1, the voltage value of the right electrode of the negative capacitor 632 (i.e., the voltage value of the negative input terminal of the comparator module 610) drops to the bias voltage V. sf Because the voltage value of the right electrode of the positive capacitor 631 (i.e., the voltage value of the positive input terminal of the comparator module 610) is fixed at Vsf, the voltage values ​​at the positive and negative terminals of the comparator module 610 are the same at this time, i.e., Vsf. sf +(V ramp -V sig Since ) = Vsf, the flip must occur at V. ramp =V sig At that moment, the output signal of comparator module 610 flips.

[0065] In this photoelectric signal V sig and ramp signal V ramp In the implementation where the comparator module 610 is connected to the same input terminal in stages, since the comparator module 610 is always based on the same voltage value V sf Complete the level flipping of the output signal (i.e.) Figure 8 (The dotted line in the diagram remains stationary), which greatly reduces the common-mode input range of the comparator module and reduces the design difficulty.

[0066] The following describes the counter coupled to the comparator module.

[0067] In one embodiment, the counter is a local counter, meaning that each column circuit 131 has its own internal counter (e.g., ...). Figure 1 As shown in the figure, the counter counts according to the clock signal.

[0068] The counter can start counting from the initial moment (t0) of the comparison phase of the comparator module, outputting a corresponding clock signal. Counting ends when the comparator module's output signal flips (t1) to obtain the corresponding count value. This count value reflects the time length T between the start of the comparison phase (t0) and the moment (t1) when the voltages of the photosensitive photoelectric signal and the ramp signal are equal. The count value can be stored in the register corresponding to the counter. Based on the preset logic and the count value, a photosensitive gain signal can be generated, thereby controlling the photosensitive photoelectric signal V. sigSimultaneous amplification and analog-to-digital conversion are performed. For example, the count value can be converted into a corresponding digital signal based on appropriate processing logic, thereby generating the photosensitive gain signal. Since the generated photosensitive gain signal is a digital signal, it will not affect the subsequent processing based on the photosensitive gain signal if the amplified signal and the slope adjustment of the ramp signal have the same effect.

[0069] In some implementations, to further reduce chip area overhead, the counter can be a global counter, meaning only one global counter is set in the optical sensing system. To accommodate the count values ​​corresponding to different column circuits 131-133, each column circuit 131-133 can have its own memory cell to store its respective count value. The global counter starts from the ramp signal V. ramp The counting begins at the initial time (i.e., the initial time t0 of the comparison phase), and when the comparator modules of the multiple column circuits 131-133 flip (at time t1), the count value corresponding to each comparator module is stored in its respective memory cell. Accordingly, each column circuit 131-133 can generate its corresponding photosensitive gain signal based on the count value in its respective memory cell. Since the clock signal generated by the global counter does not affect the processing logic of different column circuits, the chip area can be effectively reduced while ensuring system performance.

[0070] Now return to the reference Figure 1 The ramp signal generator 120 is a global ramp generator, meaning that only one global ramp generator 120 is needed in the optical sensing system. The global ramp generator 120 is used to generate the ramp signal V. ramp And the ramp signal V ramp The data is transmitted to each column circuit 131-133 respectively. The design of the global ramp generator 120 can also effectively reduce the chip area.

[0071] After receiving the photosensitive gain signal, which is the result of analog-to-digital conversion performed by the column circuits 131 to 133, the digital logic circuit 140 can use the photosensitive gain signal to calculate the digital sampling signal, which can then be used to reflect the light signal intensity of the corresponding light.

[0072] Since the photosensitive gain signal alone may not be able to reflect the comparison results before and after illumination, i.e., it is impossible to directly determine the light signal intensity corresponding to the photosensitive gain signal, one embodiment of the present invention also performs Correlated Double Sampling (CDS): the output signal of each pixel unit contains both the photosensitive photoelectric signal and the reset electrical signal. At the start and end of integration, the output signal is sampled (two sampling pulses are generated within one signal output cycle, sampling the two levels of the output signal respectively, i.e., one sampling of the reset electrical signal and the other sampling of the photosensitive photoelectric signal), and the time interval between the two samplings is carefully controlled so that the noise voltages of the two samplings are almost the same. Subtracting the two sampled values ​​(photosensitive gain signal and reset gain signal) basically eliminates the interference of reset noise and obtains the actual effective amplitude of the signal level. That is to say, the Correlated Double Sampling (CDS) of one embodiment of the present invention is performed in the digital domain: the difference between the photosensitive gain signal and the reset gain signal is calculated as the digital sampling signal.

[0073] The reset gain signal can be a digital signal obtained by sampling the reset electrical signal using the array circuit. The reset electrical signal can be the signal output at the initial moment of photoelectric conversion in the pixel unit. By comparing this signal with the photosensitive gain signal, the aforementioned correlated double sampling can be achieved. The specific process of sampling the reset electrical signal (including gain amplification and analog-to-digital conversion) can be referred to the steps above for the photosensitive photoelectric signal V. sig The process of magnification will not be described in detail here.

[0074] The digital logic circuit 140 calculates the difference between the photosensitive gain signal and the reset gain signal, and uses the difference as a digital sampling signal to determine the light signal intensity of the light received by the pixel unit this time.

[0075] Correspondingly, after obtaining the digital sampling signal, the corresponding processing module in the optical sensing system can also integrate the digital sampling signals corresponding to each pixel unit to perform corresponding image processing and generation, thereby achieving effects such as image capture and fingerprint recognition.

[0076] Optical sensing systems can be applied to fingerprint detection devices, such as smartphones and access control systems, to achieve user authentication and protect user information security. In practical applications, optical sensing systems can also be used in other devices for image sensing, and are not limited to the examples mentioned above.

[0077] As can be seen from the above embodiments, the optical sensing system controls the amplification factor of the photoelectric signal based on the slope of the ramp signal generated by the ramp signal generator. This allows the array circuit to generate a photosensitive gain signal based on the ramp signal and the photoelectric signal, achieving signal strength amplification without the need for an additional PGA. Ultimately, the photosensitive gain signal can be used to calculate the digital sampled signal to determine the corresponding optical signal intensity. This system achieves signal amplification while eliminating the PGA, simplifying the structure of the optical sensing system, reducing the area overhead of the corresponding chip, expanding the application range of the optical sensing chip, and ensuring the effectiveness of subsequent image processing.

[0078] Based on the aforementioned optical sensing system, this specification also proposes a method for calculating digital sampling signals. This method is implemented based on the aforementioned optical sensing system. For example... Figure 9 As shown, the digital sampling signal calculation method may include the following specific implementation steps.

[0079] S910: A ramp signal generator generates a ramp signal; the ramp signal includes a signal whose signal strength changes gradually over time, and the rate of change of the ramp signal's signal strength corresponds to the amplification factor of the photoelectric signal.

[0080] S920: The ramp signal generator transmits the ramp signal to the column circuit.

[0081] S930: The column circuit generates a photosensitive gain signal based on the ramp signal and the photosensitive photoelectric signal; the photosensitive gain signal includes the digital signal corresponding to the photosensitive photoelectric signal after signal intensity amplification.

[0082] S940: The column circuit transmits the photosensitive gain signal to the digital logic circuit.

[0083] S950: The digital logic circuit calculates the digital sampling signal based on the photosensitive gain signal.

[0084] After receiving the photosensitive gain signal, the digital logic circuit can use the photosensitive gain signal to calculate the digital sampling signal, which can then be used to reflect the light signal intensity of the corresponding light.

[0085] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations, which may be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).

[0086] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations, which may be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).

[0087] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0089] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0091] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0092] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0093] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of computer program products implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] The embodiments described in this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0095] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0096] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An optical sensing system, characterized by The ramp signal generator, the digital logic circuit and the plurality of column circuits are included. The ramp signal generator is configured to generate a ramp signal and transmit the ramp signal to the column circuits; the ramp signal includes a signal with a gradually changing signal strength over time, and a signal strength change rate of the ramp signal corresponds to an amplification multiple of a photosensitive electrical signal; One of the plurality of column circuits is configured to receive the photosensitive electrical signal and output a photosensitive gain signal to the digital logic circuit according to the ramp signal and the photosensitive electrical signal; the column circuit includes a comparator module and a counter, or the column circuit includes the comparator module and the optical sensing system includes a global counter; the counter is configured to count a time length from an initial time of the ramp signal to a time when an output signal of the comparator module is inverted; the photosensitive gain signal is obtained by converting the time length, and the photosensitive gain signal includes a digital signal corresponding to an amplified photosensitive electrical signal; The digital logic circuit is configured to calculate a digital sampling signal according to the photosensitive gain signal.

2. The system of claim 1, wherein, The optical sensing system further includes a pixel array. The pixel array includes a plurality of rows and a plurality of columns of pixel units, and each of the column circuits corresponds to a column of pixel units of the pixel array. Each of the pixel units is configured to generate a corresponding photosensitive electrical signal according to a received light signal and transmit the photosensitive electrical signal to the column circuit.

3. The system of claim 1, wherein, The ramp signal generator is configured to have different signal strength change rates according to different values of a configuration register.

4. The system of claim 1, wherein, The ramp signal generator is provided with a capacitor; a capacitance value of the capacitor is used to adjust the signal strength change rate of the ramp signal.

5. The system of claim 1, wherein, The ramp signal generator is provided with a current source; a current output to the ramp signal generator is used to adjust the signal strength change rate of the ramp signal.

6. The system of claim 1, wherein, The output signal of the comparator module is inverted when a voltage difference between the ramp signal and the photosensitive electrical signal is zero.

7. The system of claim 6, wherein, The comparator module includes a first input terminal and a second input terminal; the first input terminal is coupled to a reference voltage; the second input terminal is coupled to the photosensitive electrical signal in a reset stage and coupled to the ramp signal in a comparison stage; the output signal of the comparator module is inverted when a signal voltage coupled to the second input terminal changes to be the same as the first input terminal.

8. The system of claim 1, wherein, The output signal of the comparator module is inverted when the ramp signal is equal to the photosensitive electrical signal.

9. The system of claim 8, wherein, The comparator module includes a first input terminal and a second input terminal; the first input terminal and the second input terminal are coupled to a bias voltage in a reset stage, the first input terminal is coupled to the photosensitive electrical signal in a comparison stage, and the second input terminal is coupled to the ramp signal in the comparison stage; the output signal of the comparator module is inverted when a signal voltage coupled to the second input terminal changes to be the same as the first input terminal.

10. The system of claim 6 or 8, wherein, The counter starts counting from an initial time of the ramp signal until the output signal of the comparator module is inverted to obtain a count value, and outputs the photosensitive gain signal according to the count value.

11. The system of claim 6 or 8, wherein, The optical sensing system further comprises a plurality of storage units, each of which corresponds to a column circuit; the global counter starts counting from the initial time when the ramp signal is generated, and stores the count value corresponding to each comparator module in the corresponding storage unit when the comparator module in each column circuit flips, and outputs the corresponding light sensing gain signal according to the corresponding count value.

12. The system of claim 1, wherein, The ramp signal generator comprises a global ramp generator; the global ramp generator is configured to generate the ramp signal and transmit the ramp signal to each column circuit.

13. The system of claim 2, wherein, The calculation of the digital sampling signal according to the light sensing gain signal comprises: The column circuit receives a reset electrical signal and outputs a reset gain signal to the digital logic circuit according to the ramp signal and the reset electrical signal; the reset electrical signal is a signal output at the initial time of photoelectric conversion of the pixel unit; the reset gain signal comprises a digital signal corresponding to the reset electrical signal after signal intensity amplification; The digital logic circuit calculates the difference between the light sensing gain signal and the reset gain signal as the digital sampling signal.

14. A method for calculating a digital sampled signal applied to an optical sensing system, characterized by, The method comprises: The ramp signal generator generates a ramp signal; the ramp signal comprises a signal whose signal intensity gradually changes over time, and the signal intensity change rate of the ramp signal corresponds to the amplification multiple of the light sensing electrical signal; The ramp signal generator transmits the ramp signal to the column circuit; The column circuit generates a light sensing gain signal according to the ramp signal and the light sensing electrical signal; the column circuit comprises a comparator module and a counter, or the column circuit comprises a comparator module and the optical sensing system comprises a global counter; the counter is configured to count the time length from the initial time when the ramp signal is generated to the time when the output signal of the comparator module flips; the light sensing gain signal is obtained by converting the time length, and the light sensing gain signal comprises a digital signal corresponding to the light sensing electrical signal after amplitude amplification; The column circuit transmits the light sensing gain signal to the digital logic circuit; The digital logic circuit calculates a digital sampling signal according to the light sensing gain signal.

Images