Phase deviation measurement circuit, detection circuit, chip system and application method thereof

Abstract

The application discloses a phase deviation measurement circuit, a detection circuit, a chip system and an application method thereof, wherein the phase deviation measurement circuit comprises a coarse-grained delay chain, a signal source selector, a fine-grained delay chain and a sampling unit. The phase deviation measurement circuit of the application utilizes the coupling relationship between the phase deviation of the interconnection bus signal between chips and the parameters such as the parasitic capacitance, resistance and inductance of the signal line, detects the phase deviation between different signals based on the method combining the coarse-grained delay chain and the fine-grained delay chain, has universal applicability, can be widely used in the interconnection bus transmission protection of various chips, can prevent the key information from being detected and analyzed in the interconnection bus transmission process, expands the chip data security protection range from the chip interior to the chip exterior, has the advantages of good security, high sensitivity and wide adaptability, can improve the security of the data transmission between chips, and avoids the leakage of sensitive data through the bus detection approach.

Description

Technical Field

[0001] This invention relates to security hardening circuit technology in the field of integrated circuit design, specifically to a phase deviation measurement circuit, a detection circuit, a chip system, and its application method. Background Technology

[0002] In electronic information systems, multiple different processing chips, such as data processing chips and data storage chips, are often present. When data is transmitted between different chips via a data bus, there is a risk of information leakage if malicious attackers use probes to probe and recover the transmitted data. Data buses include, but are not limited to, SPI, QSPI, UART, USART, and I2C. Conventional oscilloscopes or logic analyzers have the capability to probe signal lines. Generally, existing chips do not have leakage protection measures for data transmission on the data bus; they are often only responsible for implementing the corresponding data transmission function. This makes the data bus between chips a potential channel for sensitive information leakage. Malicious attackers can intercept the transmitted content simply by probing the data signal lines. If the data transmitted on the data bus between chips is in plaintext format, malicious attackers can easily reconstruct the content of the transmitted data. Therefore, how to avoid the risk of information leakage during data bus transmission has become a critical technical problem that urgently needs to be solved. Summary of the Invention

[0003] The technical problem this invention aims to solve is as follows: Addressing the aforementioned problems in the prior art, this invention provides a phase deviation measurement circuit designed to detect chip phase deviation, enabling phase deviation detection via chip bus sensing. This invention also provides a detection circuit and a chip system for integrating the aforementioned phase deviation measurement circuit to achieve chip phase deviation detection. Furthermore, this invention provides an application method for the chip system, which integrates data bus sensing within the chip to detect potential probing behavior in real time, and actively blocks data transmission upon detection to prevent information leakage, thus preventing malicious attackers from using signal detection tools to collect transmitted content and recover original data, thereby preventing the leakage of sensitive information.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A phase deviation measurement circuit includes a coarse-grained delay chain, a signal source selector, a fine-grained delay chain, and a sampling unit. The coarse-grained delay chain includes N series-connected delay units C-DLY, used to sequentially pass an input first detection signal S through the N delay units C-DLY to obtain N delayed signals S1 to SN. The signal source selector, under the control of a gating signal CSEL, selects one detection signal SC from the first detection signal S and the N delayed signals S1 to SN as the input to the fine-grained delay chain. The fine-grained delay chain contains M series-connected fine-grained delay units. The fine-grained delay unit F-DLY is used to sequentially process the input detection signal SC through M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM; the sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T.

[0006] Furthermore, the present invention also provides a phase deviation measurement circuit, including a fine-grained delay chain and a sampling unit. The fine-grained delay chain includes M series-connected fine-grained delay units F-DLY, used to sequentially pass the input first detection signal S through the M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM. The sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T.

[0007] Furthermore, the present invention also provides an interconnect bus signal phase deviation remote detection circuit, including n remote phase deviation measurement circuits RTDC1 to RTDCn, wherein the remote phase deviation measurement circuits RTDC1 to RTDCn are the phase deviation measurement circuits as described in claim 1, and any i-th remote phase deviation measurement circuit RDCi is used to detect the phase deviation Ri between the first detection signal RSi and the second detection signal RTi from the remote chip under the control of the corresponding gating signal CSELi.

[0008] Furthermore, the present invention also provides an interconnect bus signal phase deviation local detection circuit, including m local phase deviation measurement circuits LTDC1 to LTDCm. The local phase deviation measurement circuits LTDC1 to LTDCm are the phase deviation measurement circuits as described in claim 1. Any i-th local phase deviation measurement circuit LTDCi is used to detect the phase deviation Li between the first detection signal LSi and the second detection signal LTi from the local chip under the control of the corresponding strobe signal CSELi. The first detection signal and the second detection signal of the local chip are connected to the input signals of the bidirectional IO pads of the local chip.

[0009] In addition, the present invention also provides a chip, including a chip body, wherein the chip body is provided with the aforementioned interconnect bus signal phase deviation remote detection circuit or the aforementioned interconnect bus signal phase deviation local detection circuit.

[0010] In addition, the present invention also provides a multi-chip circuit system, including a remote chip and a local chip interconnected by an interconnect bus, wherein at least one of the remote chip or the local chip has the aforementioned interconnect bus signal phase deviation remote detection circuit or the aforementioned interconnect bus signal phase deviation local detection circuit in its chip body.

[0011] Furthermore, the present invention also provides an application method for the aforementioned multi-chip circuit system, comprising:

[0012] S101 enables signal phase deviation detection on the interconnect bus;

[0013] S102, clear the timer to 0;

[0014] S103, timer counting;

[0015] S104: Determine if the timing threshold has been reached. If not, proceed to step S103; otherwise, continue to step S105.

[0016] S105, determine whether remote detection is enabled. If enabled, continue to step S106; otherwise, proceed to step S110.

[0017] S106, initiate remote phase deviation detection;

[0018] S107, samples the far-end detection circuit for the phase deviation of the interconnect bus signal;

[0019] S108, compare with pre-configured remote detection feature values;

[0020] S109, If the difference between the current sampled value and the feature value exceeds the threshold, a remote detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102.

[0021] S110, determine whether local detection is enabled. If enabled, continue to execute step S111; otherwise, end the current interconnect bus signal line detection behavior perception operation.

[0022] S111, Initiate local phase deviation detection;

[0023] S112, sampling the local end detection circuit of the interconnect bus signal phase deviation;

[0024] S113, compare with the pre-configured local detection feature value;

[0025] S114, if the difference between the current sampled value and the feature value exceeds the threshold, a local detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102.

[0026] Optionally, before step S101, a detection parameter register is further included to configure at least one of the following: the strobe signal CSEL of each phase deviation measurement circuit, the detection reference value, the difference judgment threshold between the phase deviation and the feature value, and the timing threshold for triggering phase deviation detection.

[0027] Optionally, before step S108, the method further includes generating pre-configured remote detection feature values:

[0028] S201, remote chip starts training;

[0029] S202, the remote chip sends a start training command to the local chip via the interconnect bus; after receiving the start training command, the local chip performs phase deviation sampling and training feature value initialization.

[0030] S203, the remote chip continuously sends training mode sequence 1 to training mode sequence t to the local chip via the interconnect bus. Here, the training mode sequence is a data sequence with an agreed encoding format between the two chips, and t is an integer greater than or equal to 1. When the local chip receives each training mode sequence, it triggers remote phase deviation sampling and updates the remote detection feature value.

[0031] S204 After the remote chip completes the transmission of the training mode sequence, it ends the training process and obtains the remote detection feature values ​​stored in the local chip.

[0032] Optionally, before step S113, the method further includes generating pre-configured local detection feature values:

[0033] S301, the local chip starts training and performs phase deviation sampling and training feature value initialization actions;

[0034] S302, the local chip outputs the training sequence via the interconnect bus;

[0035] S303, the local chip uses the interconnect bus signal phase deviation local detection circuit to sample the signal phase deviation;

[0036] S304, the local chip updates the local detection feature value;

[0037] S305, the local chip determines whether the training sampling number has been reached. If it has, the training ends, and the remote detection feature value of the local chip is obtained and saved, and the process ends; otherwise, the process proceeds to step S302.

[0038] Optionally, updating the remote detection feature value in step S203 means calculating and updating the remote detection feature value using the cumulative average; updating the local detection feature value in step S304 means calculating and updating the local detection feature value using the cumulative average.

[0039] Compared with existing technologies, the present invention has the following main advantages: The phase deviation measurement circuit of the present invention utilizes the coupling relationship between the phase deviation of the interconnect bus signal and parameters such as parasitic capacitance, resistance, and inductance of the signal line. Based on a method combining coarse-grained and fine-grained delay chains, it can sensitively detect the phase deviation between different signals, thereby detecting possible signal probe behavior. It has universal applicability and can be widely used for interconnect bus transmission protection of various high-security chips, preventing critical information from being probed and analyzed during interconnect bus transmission, thus providing extremely high security. The present invention extends the scope of chip data security protection from internal chip storage and processing to the perception of probe behavior on the external interconnect bus. By equivalently converting the minute parasitic capacitance, resistance, and inductance parameters introduced by signal line probe behavior, it detects the phase deviation between different signals, offering advantages of high sensitivity and wide applicability. It can improve the security of data transmission between different chips via the interconnect bus in electronic information systems, avoiding the leakage of sensitive data through bus probe paths. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the phase deviation measurement circuit in Embodiment 1 of the present invention.

[0041] Figure 2 This is a schematic diagram of the principle of the far-end detection circuit for the phase deviation of the interconnect bus signal in Embodiment 1 of the present invention.

[0042] Figure 3 This is a schematic diagram of the local end detection circuit for the interconnect bus signal phase deviation in Embodiment 1 of the present invention.

[0043] Figure 4 This is a schematic diagram of the real-time sensing process of signal line detection behavior in Embodiment 1 of the present invention.

[0044] Figure 5 This is a flowchart of the signal phase deviation far-end detection feature value training method in Embodiment 1 of the present invention.

[0045] Figure 6 This is a flowchart of the signal phase deviation local end detection feature value training method in Embodiment 1 of the present invention. Detailed Implementation

[0046] Example 1:

[0047] like Figure 1 As shown, this embodiment provides a phase deviation measurement circuit, including a coarse-grained delay chain, a signal source selector, a fine-grained delay chain, and a sampling unit. The coarse-grained delay chain includes N series-connected delay units C-DLY, used to sequentially pass the input first detection signal S through the N delay units C-DLY to obtain N delayed signals S1 to SN. The signal source selector, under the control of the gating signal CSEL, selects one detection signal SC from the first detection signal S and the N delayed signals S1 to SN as the input of the fine-grained delay chain. The fine-grained delay chain contains M series-connected fine-grained delay units. The granular delay unit F-DLY is used to sequentially pass the input detection signal SC through M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM. The sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of each D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T. This phase deviation measurement circuit, through the combination of coarse-grained and fine-grained delay chains, can detect the relative delay of the phase transition between two signals (the first detection signal S and the second detection signal T). See also Figure 1 The phase deviation measurement circuit includes four input signals: S, T, CSEL, and EN. S is the first detection signal; T is the second detection signal; and CSEL is an X-bit gating signal used for selecting a coarse-grained delay signal source, where X is an integer greater than or equal to 1. CSEL can be used to select 2... XThere are three different delay signal sources; EN is the enable signal. The output of this phase deviation measurement circuit is denoted as T1, T2, ..., TM, which is an M-bit delay count value, where M is an integer greater than or equal to 1. The input of the coarse-grained delay chain is the first detection signal S, which contains N cascaded delay units C-DLY. Here, the delay units can generally be selected from the standard cell library with a larger delay for the corresponding process technology, where N is an integer greater than or equal to 1. The outputs of each delay unit are denoted as S1, S2, ..., SN. As needed, 2^X signal sources are selected from S, S1, ..., SN and input to the signal source selector (multiplexer C-MUX). According to the configuration of CSEL, the delayed detection signal SC is selected and used as the input of the fine-grained delay chain. The fine-grained delay chain comprises M cascaded fine-grained delay units F-DLY. These units are typically selected from standard cell libraries with shorter delay times for the corresponding process technology, resulting in higher accuracy in delay detection. The outputs of each delay unit are denoted as F1, F2, ..., FM. A D flip-flop unit corresponds to each fine-grained delay unit. These D flip-flops can also be selected from standard cell libraries for the corresponding process technology. The data input D of the D flip-flop unit is connected to the output of the fine-grained delay unit, the reset signal RSTN is connected to the enable signal EN, and the clock signal CK is connected to the second detection signal T. The outputs Q are denoted as T1, T2, ..., TM, representing the overall circuit output. When the second detection signal T rises and the enable signal EN is active, the circuit completes one sampling and generates an output. T1, T2, ..., TM can reflect the number of delay unit stages that the first detection signal S passes through the coarse-grained delay and fine-grained delay chains when the second detection signal T has a rising edge transition, which is the phase deviation between the first detection signal S and the second detection signal T.

[0048] Using the aforementioned phase deviation measurement circuit combining coarse and fine granularity as a basic building block, a remote phase deviation detection circuit for interconnect bus signals can be constructed. From the perspective of the chip with the built-in detection circuit, the remote end is the peer chip connected via the interconnect bus; here, remote detection refers to detecting the phase deviation of the signal driven by the remote chip. Figure 2As shown, this embodiment provides a remote detection circuit for interconnect bus signal phase deviation, including n remote phase deviation measurement circuits RTDC1 to RTDCn. These circuits are the phase deviation measurement circuits described above. The i-th remote phase deviation measurement circuit, RDCi, is used to detect the phase deviation Ri between the first detection signal RSi and the second detection signal RTi from the remote chip under the control of the corresponding gating signal CSEL, where n is an integer greater than or equal to 1. The enable signal for the remote phase deviation measurement circuits RTDC1 to RTDCn is denoted as EN. The inputs of RTDC1 are denoted as RS1, RT1, and RSEL1, and the output is denoted as R1, where RS1 and RT1 are the first and second detection signals, respectively, RSEL1 is an X-bit gating signal, and R1 is an M-bit output signal; similarly, the inputs of RTDC2 are denoted as RS2, RT2, and RSEL2, and the output is R2; the inputs of RTDCn are denoted as RSn, RTn, and RSELn, and the output is Rn. Generally, the first and second detection signals of each circuit module can be the same, or different signals can be selected as needed. For example, if you want to perform remote detection of signal phase deviation on the QSPI bus, you can configure four time-to-digital converter circuit modules that combine coarse and fine granularity. The first detection signal of each circuit module can be the QSPI clock signal, and the second detection signal of each circuit module can be one of the four data signals. This is equivalent to detecting the phase deviation of each data signal relative to the clock signal.

[0049] Using the aforementioned phase deviation measurement circuit combining coarse and fine granularity as a basic building block, a local-end phase deviation detection circuit for interconnect bus signals can be constructed. From the perspective of a chip with a built-in detection circuit, the local end refers to the chip itself; here, local-end detection means detecting the phase deviation of the signal driven by the chip itself. Figure 3As shown, this embodiment also provides an interconnect bus signal phase deviation local detection circuit, including m local phase deviation measurement circuits LTDC1 to LTDCm. The local phase deviation measurement circuits LTDC1 to LTDCm are the phase deviation measurement circuits described in claim 1. Any i-th remote phase deviation measurement circuit LTDCi is used to detect the phase deviation Li between the first detection signal LSi and the second detection signal LTi from the local chip under the control of the corresponding strobe signal CSEL. The first detection signal and the second detection signal of the local chip are connected to the input signals of the bidirectional IO pads of the local chip. Wherein, m is an integer greater than or equal to 1, and the enable signal of the m local phase deviation measurement circuits LTDC1 to LTDCm is denoted as EN. The inputs of LTDC1 are denoted as LS1, LT1, LSEL1, and the output is denoted as L1. LS1 and LT1 are the first and second detection signals, respectively, LSEL1 is an X-bit strobe signal, and L1 is an M-bit output signal. Similarly, the inputs of LTDC2 are denoted as LS2, LT2, LSEL2, and the output is L2; ​​the inputs of LTDCm are denoted as LSm, LTm, LSELm, and the output is Lm. Generally, the first and second detection signals of each circuit module can be the same, or different signals can be selected as needed. Unlike remote detection, local detection requires the chip itself to drive the detection signal, which can be achieved through bidirectional I / O pads (PADs). These bidirectional I / O pads have both output and input paths. When the output path is enabled, the output state of the bidirectional I / O pad is controlled by the chip itself. After a certain signal delay, the output value will return to the chip through the input path. Thus, the detection circuit can use the input signal of the bidirectional I / O pad as the detection signal. For example, if you want to perform local phase deviation detection on the QSPI bus, you can configure two time-to-digital converter circuit modules that combine coarse and fine granularity. Each circuit module uses two data signals as the first detection signal and the second detection signal, which is equivalent to detecting the phase deviation between each data signal.

[0050] Furthermore, this embodiment also provides a chip, including a chip body, in which the aforementioned interconnect bus signal phase deviation remote detection circuit or interconnect bus signal phase deviation local detection circuit is provided. When the chip integrates the aforementioned interconnect bus signal phase deviation remote detection circuit or local detection circuit, the detection circuit can be used to detect the phase deviation of the interconnect bus signal. The phase change between signals is affected by the parasitic capacitance, resistance, and inductance on each transmission signal line. When a malicious attacker uses equipment such as an oscilloscope or logic analyzer to probe the signal, it inevitably causes changes in the parasitic capacitance, resistance, and inductance on the corresponding signal line, resulting in a change in the phase deviation between the signals. Therefore, it is possible to infer whether a probe has occurred. To detect the aforementioned changes in signal phase deviation, it is necessary to perform phase deviation detection under safe and reliable conditions where there is no signal probe activity, extract feature values, and use these as a reference value for subsequent probe detection.

[0051] Furthermore, this embodiment also provides a multi-chip circuit system, including a remote chip and a local chip interconnected via an interconnect bus. At least one of the remote chip or the local chip has a remote detection circuit or a local detection circuit for interconnect bus signal phase deviation described above in its chip body. When the multi-chip circuit system integrates the aforementioned remote detection circuit and local detection circuit for interconnect bus signal phase deviation, the detection circuit can be used to detect the phase deviation of the interconnect bus signal. Phase changes between signals are affected by parasitic capacitance, resistance, and inductance on each transmission signal line. When a malicious attacker uses equipment such as an oscilloscope or logic analyzer to probe the signal, it inevitably causes changes in the parasitic capacitance, resistance, and inductance on the corresponding signal lines, resulting in changes in the phase deviation between signals. Therefore, it is possible to infer whether a probe has occurred. To detect the aforementioned changes in signal phase deviation, it is necessary to perform phase deviation detection under safe and reliable conditions where there is no signal probe activity, extract feature values, and use these as a reference value for subsequent probe detection.

[0052] like Figure 4 and Figure 5 As shown, this embodiment also provides an application method for the aforementioned multi-chip circuit system, including:

[0053] S101 enables signal phase deviation detection on the interconnect bus;

[0054] S102, clear the timer to 0;

[0055] S103, timer counting;

[0056] S104: Determine if the timing threshold has been reached. If not, proceed to step S103; otherwise, continue to step S105.

[0057] S105, determine whether remote detection is enabled. If enabled, continue to step S106; otherwise, proceed to step S110.

[0058] S106, initiate remote phase deviation detection;

[0059] S107, samples the far-end detection circuit for the phase deviation of the interconnect bus signal;

[0060] S108, compare with pre-configured remote detection feature values;

[0061] S109, If the difference between the current sampled value and the feature value exceeds the threshold, a remote detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102.

[0062] S110, determine whether local detection is enabled. If enabled, continue to execute step S111; otherwise, end the current interconnect bus signal line detection behavior perception operation.

[0063] S111, Initiate local phase deviation detection;

[0064] S112, sampling the local end detection circuit of the interconnect bus signal phase deviation;

[0065] S113, compare with the pre-configured local detection feature value;

[0066] S114, if the difference between the current sampled value and the feature value exceeds the threshold, a local detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102.

[0067] As an optional implementation, this embodiment further includes configuring a detection parameter register before step S101, which is used to configure at least one of the following: the strobe signal CSEL of each phase deviation measurement circuit, the detection reference value, the difference judgment threshold between phase deviation and feature value, and the timing threshold for triggering phase deviation detection.

[0068] See Figure 5 and Figure 6 Before step S108, the process also includes generating pre-configured remote detection feature values:

[0069] S201, remote chip starts training;

[0070] S202, the remote chip sends a start training command to the local chip via the interconnect bus; after receiving the start training command, the local chip performs phase deviation sampling and training feature value initialization.

[0071] S203, the remote chip continuously sends training mode sequence 1 to training mode sequence t to the local chip via the interconnect bus. Here, the training mode sequence is a data sequence with an agreed encoding format between the two chips, and t is an integer greater than or equal to 1. When the local chip receives each training mode sequence, it triggers remote phase deviation sampling and updates the remote detection feature value.

[0072] S204 After the remote chip completes the transmission of the training mode sequence, it ends the training process and obtains the remote detection feature values ​​stored in the local chip.

[0073] See Figure 5 and Figure 6 Before step S113, the method also includes generating pre-configured local detection feature values:

[0074] S301, the local chip starts training and performs phase deviation sampling and training feature value initialization actions;

[0075] S302, the local chip outputs the training sequence via the interconnect bus;

[0076] S303, the local chip uses the interconnect bus signal phase deviation local detection circuit to sample the signal phase deviation;

[0077] S304, the local chip updates the local detection feature value;

[0078] S305, the local chip determines whether the training sampling number has been reached. If it has, the training ends, and the remote detection feature value of the local chip is obtained and saved, and the process ends; otherwise, the process proceeds to step S302.

[0079] It should be noted that updating the remote detection feature value / updating the local detection feature value can be done using the required statistical data update method as needed. For example, without loss of generality, as an optional implementation, updating the remote detection feature value in step S203 means calculating and updating the remote detection feature value using the cumulative average; updating the local detection feature value in step S304 means calculating and updating the local detection feature value using the cumulative average.

[0080] When the chip integrates the aforementioned interconnect bus signal phase deviation remote detection circuit or local detection circuit, after training using the aforementioned feature value training method, real-time sensing of interconnect bus signal line detection behavior can be achieved in the actual working state of the chip.

[0081] In summary, this embodiment utilizes the coupling relationship between the phase deviation of inter-chip interconnect bus signals and parameters such as parasitic capacitance, resistance, and inductance of signal lines. Based on a phase deviation measurement circuit combining coarse and fine granularity, it sensitively detects the phase deviation between different signals, thereby detecting possible signal probing behavior. It has universal applicability and can be widely used for interconnect bus transmission protection of various high-security chips, preventing critical information from being probed and analyzed during interconnect bus transmission, thus providing extremely high security. This embodiment extends the scope of chip data security protection from internal chip storage and processing to the perception of probe behavior on the external interconnect bus. By equivalently converting the minute parasitic capacitance, resistance, and inductance parameters introduced by signal line probe behavior to detect the phase deviation between different signals, it has the advantages of high sensitivity and wide applicability. It can further improve the security of data transmission between different chips via interconnect buses in electronic information systems, avoiding the leakage of sensitive data through bus probes.

[0082] Example 2:

[0083] This embodiment is a simplification of Embodiment 1. Without loss of generality, if N is 0 in Embodiment 1, it is equivalent to not using the coarse-grained delay chain, but directly using the detection signal S as the input of the fine-grained delay chain. That is, the phase deviation measurement circuit of this embodiment includes a fine-grained delay chain and a sampling unit. The fine-grained delay chain contains M series-connected fine-grained delay units F-DLY, used to sequentially pass the input first detection signal S through the M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM; the sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T.

[0084] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A remote detection circuit for phase deviation of interconnect bus signals, characterized in that, The system includes n remote phase deviation measurement circuits RTDC1 to RTDCn, each of which is either a first phase deviation measurement circuit or a second phase deviation measurement circuit. The i-th remote phase deviation measurement circuit RDCi is used, under the control of the corresponding gating signal CSEL, to detect the phase deviation Ri between the first detection signal RSi and the second detection signal RTi from the remote chip. The first phase deviation measurement circuit includes a coarse-grained delay chain, a signal source selector, a fine-grained delay chain, and a sampling unit. The coarse-grained delay chain comprises N cascaded delay units C-DLY, used to sequentially pass the input first detection signal S through the N delay units C-DLY to obtain N delayed signals S1 to SN; the signal source selector, under the control of the gating signal CSEL, selects one detection signal SC from the first detection signal S and the N delayed signals S1 to SN as the input of the fine-grained delay chain; the fine-grained delay chain comprises M cascaded fine-grained delay units F-DLY, used to sequentially pass the input detection signal SC through the M fine-grained delay units F-DLY to obtain The sampling unit includes M-channel delay signals F1 to FM; each sampling unit includes a D flip-flop unit corresponding to a fine-grained delay unit F-DLY. The reset signal terminal RSTN of each D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T. The second phase deviation measurement circuit includes a fine-grained delay chain and a sampling unit. The fine-grained delay chain contains M series-connected fine-grained delay units. The delay unit F-DLY is used to sequentially process the input first detection signal S through M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM; the sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T.

2. A local-end detection circuit for phase deviation of interconnect bus signals, characterized in that, This includes m local phase deviation measurement circuits LTDC1 to LTDCm, where each circuit is either a first or second phase deviation measurement circuit. The i-th far-end phase deviation measurement circuit LTDCi is used, under the control of the corresponding gating signal CSEL, to detect the phase deviation Li between the first detection signal LSi and the second detection signal LTi from the local chip. The first and second detection signals from the local chip are connected to the bidirectional I / O pins of the local chip. The input signal of the pad; the first phase deviation measurement circuit includes a coarse-grained delay chain, a signal source selector, a fine-grained delay chain, and a sampling unit. The coarse-grained delay chain includes N series-connected delay units C-DLY, used to sequentially pass the input first detection signal S through the N delay units C-DLY to obtain N delayed signals S1 to SN. The signal source selector is used to select one detection signal SC from the first detection signal S and the N delayed signals S1 to SN as the input of the fine-grained delay chain under the control of the gating signal CSEL. The fine-grained delay chain includes M series-connected fine-grained delay units F-DLY, used to sequentially pass the input detection signal SC through the M fine-grained delay units F-DLY to obtain M delayed signals F1 to FM. The sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY, and the reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal E. The circuit includes a clock terminal CK connected to the second detection signal T, a data input terminal D connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and an output terminal used to output the phase deviation detection signal between the first detection signal S and the second detection signal T. The second phase deviation measurement circuit includes a fine-grained delay chain and a sampling unit. The fine-grained delay chain contains M series-connected fine-grained delay units F-DLY, used to sequentially pass the input first detection signal S through the M fine-grained delay units F-DLY to obtain M delay signals F1 to FM. The sampling unit includes D flip-flop units corresponding one-to-one with the fine-grained delay units F-DLY. The reset signal terminal RSTN of the D flip-flop unit is connected to the enable signal EN, the clock terminal CK is connected to the second detection signal T, the data input terminal D is connected to the output terminal of the corresponding fine-grained delay unit F-DLY, and the output terminal is used to output the phase deviation detection signal between the first detection signal S and the second detection signal T.

3. A chip, comprising a chip body, wherein the chip body is provided with the far-end detection circuit for interconnect bus signal phase deviation as described in claim 1 or the local-end detection circuit for interconnect bus signal phase deviation as described in claim 2.

4. A multi-chip circuit system, comprising a remote chip and a local chip interconnected by an interconnect bus, wherein at least one of the remote chip or the local chip has an interconnect bus signal phase deviation remote detection circuit as described in claim 1 or an interconnect bus signal phase deviation local detection circuit as described in claim 2 in its chip body.

5. A method for applying the multi-chip circuit system as described in claim 4, characterized in that, include: S101 enables signal phase deviation detection on the interconnect bus; S102, clear the timer to 0; S103, timer counting; S104: Determine if the timing threshold has been reached. If not, proceed to step S103; otherwise, continue to step S105. S105, determine whether remote detection is enabled. If enabled, continue to step S106; otherwise, proceed to step S110. S106, initiate remote phase deviation detection; S107, samples the far-end detection circuit for the phase deviation of the interconnect bus signal; S108, compare with pre-configured remote detection feature values; S109, If the difference between the current sampled value and the feature value exceeds the threshold, a remote detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102. S110, determine whether local detection is enabled. If enabled, continue to execute step S111; otherwise, end the current interconnect bus signal line detection behavior perception operation. S111, Initiate local phase deviation detection; S112, sampling the local end detection circuit of the interconnect bus signal phase deviation; S113, compare with the pre-configured local detection feature value; S114, if the difference between the current sampled value and the feature value exceeds the threshold, a local detection anomaly warning is triggered, and the current interconnect bus signal line detection behavior perception operation is terminated; otherwise, proceed to step S102.

6. The application method of the multi-chip circuit system according to claim 5, characterized in that, Before step S101, a detection parameter register is configured to configure at least one of the following: the strobe signal CSEL of each phase deviation measurement circuit, the detection reference value, the difference judgment threshold between the phase deviation and the feature value, and the timing threshold for triggering phase deviation detection.

7. The application method of the multi-chip circuit system according to claim 5, characterized in that, Step S108 includes generating pre-configured remote detection feature values: S201, remote chip starts training; S202, the remote chip sends a start training command to the local chip via the interconnect bus; after receiving the start training command, the local chip performs phase deviation sampling and training feature value initialization. S203, the remote chip continuously sends training mode sequence 1 to training mode sequence t to the local chip via the interconnect bus. Here, the training mode sequence is a data sequence with an agreed encoding format between the two chips, and t is an integer greater than or equal to 1. When the local chip receives each training mode sequence, it triggers remote phase deviation sampling and updates the remote detection feature value. S204 After the remote chip completes the transmission of the training mode sequence, it ends the training process and obtains the remote detection feature values ​​stored in the local chip.

8. The application method of the multi-chip circuit system according to claim 7, characterized in that, Before step S113, the process also includes generating pre-configured local detection feature values: S301, the local chip starts training and performs phase deviation sampling and training feature value initialization actions; S302, the local chip outputs the training sequence via the interconnect bus; S303, the local chip uses the interconnect bus signal phase deviation local detection circuit to sample the signal phase deviation; S304, the local chip updates the local detection feature value; S305, the local chip determines whether the training sampling number has been reached. If it has, the training ends, and the remote detection feature value of the local chip is obtained and saved, and the process ends; otherwise, the process proceeds to step S302.

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