Analysis Method, Device, Electronic Device, and Storage Medium of Digital Circuit

Abstract

A method, apparatus, electronic device, and storage medium for analyzing a digital circuit. The method for analyzing the digital circuit includes: determining at least one critical path in the digital circuit; performing critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path; in response to N being greater than 1, performing voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine a voltage drop analysis result corresponding to the digital circuit; wherein the critical clock cycle detection includes: determining a plurality of analysis nodes included in the critical path; obtaining a plurality of simulation waveforms respectively corresponding to the plurality of analysis nodes; and based on the plurality of simulation waveforms, extracting p critical clock cycles corresponding to the critical path. The method for analyzing the digital circuit realizes more accurate voltage drop analysis, captures accurate working voltage changes, reduces over-design in irrelevant worst cases, and significantly improves the design margin.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for analyzing a digital circuit, an apparatus for analyzing a digital circuit, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Voltage drop (also known as IR Drop) refers to a phenomenon of voltage drop and rise on the network between power supply and ground in an integrated circuit. With the continuous evolution of semiconductor processes, the width of metal interconnects becomes narrower and narrower, resulting in an increasing resistance value (and a decreasing supply voltage). If a device is far from the power supply point, its equivalent resistance value will inevitably be relatively large. Since the power supply network is a global network with a relatively long average length, the effect of IR Drop will become more and more obvious with the continuous evolution of semiconductor processes. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for analyzing a digital circuit, including: determining at least one critical path in the digital circuit; performing critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number; in response to N being greater than 1, performing voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine a voltage drop analysis result corresponding to the digital circuit; where the critical clock cycle detection includes: determining a plurality of analysis nodes included in the critical path; obtaining a plurality of simulation waveforms respectively corresponding to the plurality of analysis nodes; based on the plurality of simulation waveforms, extracting p critical clock cycles corresponding to the critical path, where in each critical clock cycle, the plurality of analysis nodes do not satisfy the timing constraint conditions or the plurality of analysis nodes all have maximum delays, where p is a natural number.

[0004] For example, in a method for analyzing a digital circuit provided by at least one embodiment of the present disclosure, determining at least one critical path in the digital circuit includes: performing static timing analysis on the digital circuit to determine the at least one critical path, where the at least one critical path is a timing path in the digital circuit with a timing margin value less than a margin threshold or a circuit delay value greater than a delay threshold.

[0005] For example, in a method for analyzing a digital circuit provided by at least one embodiment of the present disclosure, determining a plurality of analysis nodes included in the critical path includes: determining a plurality of second devices included in the critical path and a first device located at the starting point of the timing path; using the output terminals of the first device and the plurality of second devices as the plurality of analysis nodes.

[0006] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, each simulation waveform is a simulation waveform with timing information.

[0007] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, based on the multiple simulation waveforms, p key clock cycles corresponding to the critical path are extracted, including: obtaining multiple transition edges respectively corresponding to the multiple analysis nodes; based on the multiple simulation waveforms and the multiple transition edges, determining the p key clock cycles corresponding to the critical path, wherein, in each key clock cycle, signal transitions corresponding to the corresponding transition edges are sequentially generated by the multiple simulation waveforms.

[0008] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, obtaining the multiple transition edges respectively corresponding to the multiple analysis nodes includes: performing static timing analysis on the digital circuit; based on the static timing analysis result, determining the multiple transition edges respectively corresponding to the multiple analysis nodes; wherein each transition edge indicates that when a signal transition corresponding to the transition edge occurs at the corresponding analysis node, the corresponding analysis node does not meet the timing constraint or has the maximum delay, and the transition edge includes a rising edge and / or a falling edge.

[0009] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, each simulation waveform includes multiple clock cycles. Based on the multiple simulation waveforms and the multiple transition edges, determining the p key clock cycles corresponding to the critical path includes: determining a detection order, wherein the detection order is obtained by sorting the multiple analysis nodes in the direction from the path start point to the path end point of the critical path; traversing the multiple simulation waveforms, and based on the detection order, performing a key clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a key clock cycle, wherein i is a positive integer and sequentially takes values from 1 to M, and M is the minimum value among the total number of clock cycles included in the multiple simulation waveforms.

[0010] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, based on the detection order, a critical clock cycle determination is performed on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle, including: determining the i-th clock cycle in the plurality of simulation waveforms as a plurality of waveform segments to be analyzed; determining whether corresponding signal transitions occur in sequence for the plurality of waveform segments according to the detection order, where the corresponding signal transition for each waveform segment is determined by the transition edge corresponding to the analysis node corresponding to each waveform segment; in response to the corresponding signal transitions occurring in sequence for the plurality of waveform segments according to the detection order, determining that the i-th clock cycle is a critical clock cycle, and in response to the corresponding signal transitions not occurring in sequence for the plurality of waveform segments according to the detection order, determining that the i-th clock cycle is not a critical clock cycle.

[0011] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, determining whether corresponding signal transitions occur in sequence for the plurality of waveform segments according to the detection order includes: traversing the plurality of waveform segments according to the detection order, and for the j-th waveform segment in the plurality of waveform segments: determining whether a corresponding signal transition occurs in the j-th waveform segment; in response to a corresponding signal transition occurring in the j-th waveform segment, determining whether the (j + 1)-th waveform segment meets the detection conditions, where the detection conditions include that a corresponding signal transition occurs in the (j + 1)-th waveform segment and the occurrence time of the corresponding signal transition in the (j + 1)-th waveform segment is later than the occurrence time of the corresponding signal transition in the j-th waveform segment; in response to the (j + 1)-th waveform segment meeting the detection conditions, continuing to determine whether the (j + 2)-th waveform segment meets the detection conditions until the traversal of the plurality of waveform segments is completed, and in response to the (j + 1)-th waveform segment not meeting the detection conditions, determining that the corresponding signal transitions do not occur in sequence for the plurality of waveform segments according to the detection order; where j is a positive integer and less than or equal to the total number of the plurality of waveform segments.

[0012] For example, in an analysis method of a digital circuit provided by at least one embodiment of the present disclosure, performing voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit includes: performing voltage drop analysis on the N alternative analysis scenarios respectively to obtain N analysis results corresponding to the N alternative analysis scenarios respectively; based on the N analysis results, taking the alternative analysis scenario with the largest voltage drop or the highest current change rate among the N alternative analysis scenarios as the voltage drop analysis scenario, and taking the analysis result corresponding to the voltage drop analysis scenario as the voltage drop analysis result corresponding to the digital circuit.

[0013] For example, at least one embodiment of the present disclosure provides an analysis method for a digital circuit, further including: determining, according to the voltage drop analysis result, a plurality of voltage drop voltages corresponding to the plurality of analysis nodes one by one; adjusting the operating voltages of the plurality of analysis nodes to the corresponding voltage drop voltages; performing static timing analysis on the digital circuit after voltage adjustment to determine the convergence situation of the timing of the critical path in the voltage drop analysis scenario.

[0014] For example, at least one embodiment of the present disclosure provides an analysis method for a digital circuit, further including: performing static timing analysis on the digital circuit after voltage adjustment, calculating the timing margin of the digital circuit in the voltage drop analysis scenario; and determining the timing sign-off standard of the digital circuit based on the timing margin.

[0015] For example, at least one embodiment of the present disclosure provides an analysis method for a digital circuit, further including: in response to N being equal to 0, determining that the switching coverage rate in the gate-level simulation of the digital circuit is not satisfied.

[0016] At least one embodiment of the present disclosure further provides an analysis device for a digital circuit, including: a determination unit configured to determine at least one critical path in the digital circuit; a detection unit configured to perform critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number; and an analysis unit configured to, in response to N being greater than 1, perform voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit; wherein the critical clock cycle detection includes: determining a plurality of analysis nodes included in the critical path, obtaining a plurality of simulation waveforms respectively corresponding to the plurality of analysis nodes, and extracting p critical clock cycles corresponding to the critical path based on the plurality of simulation waveforms, where in each critical clock cycle, the plurality of analysis nodes do not satisfy the timing constraint conditions or the plurality of analysis nodes all have the maximum delay, and p is a natural number.

[0017] At least one embodiment of the present disclosure further provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; and a processor configured to run the computer-executable instructions, wherein when the computer-executable instructions are run by the processor, the analysis method for a digital circuit according to any embodiment of the present disclosure is implemented.

[0018] At least one embodiment of the present disclosure further provides a non-transient computer-readable storage medium, wherein the non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the analysis method for a digital circuit according to any embodiment of the present disclosure is implemented. Description of the Drawings

[0019] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0020] Figure 1 It is a schematic flowchart of an analysis method for a digital circuit provided by at least one embodiment of the present disclosure;

[0021] Figure 2 It is a schematic flowchart of a critical clock cycle detection provided by at least one embodiment of the present disclosure;

[0022] Figure 3A It is a schematic diagram of a critical path provided by an embodiment of the present disclosure;

[0023] Figure 3B It is a schematic diagram of multiple simulation waveforms provided by an embodiment of the present disclosure;

[0024] Figure 4A It is a schematic diagram of a critical path provided by another embodiment of the present disclosure;

[0025] Figure 4B It is a schematic diagram of multiple simulation waveforms provided by another embodiment of the present disclosure;

[0026] Figure 5A It is a schematic block diagram of an analysis device for a digital circuit provided by at least one embodiment of the present disclosure;

[0027] Figure 5B It is a schematic block diagram of a detection unit provided by at least one embodiment of the present disclosure;

[0028] Figure 6 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0029] Figure 7 It is a schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed Embodiments

[0030] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the field to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0032] To keep the following description of the embodiments of this disclosure clear and concise, some detailed descriptions of known functions and known components are omitted in this disclosure.

[0033] The voltage drop phenomenon includes static voltage drop and dynamic voltage drop. The main reason for the static voltage drop phenomenon is the voltage division of the metal wires in the power network, which is mainly caused by the voltage division of the resistance of the metal wires themselves. When the current passes through the internal power wires, a power voltage drop occurs. The dynamic voltage drop is the voltage drop caused by the current fluctuation when the power supply switches in the circuit. This phenomenon occurs at the triggering edge of the clock. The clock edge transition not only brings the opening and closing of a large number of transistors in the circuit, but also brings the transition of the combinational logic circuit, often causing a large current to be generated on the entire chip in a short time. This instantaneous large current causes the voltage drop phenomenon. The more transistors that switch at the same time, the easier it is to trigger the dynamic voltage drop phenomenon.

[0034] In integrated circuit design, especially in the chip design of high-performance CPUs (Central Processing Units) and GPUs (Graphics Processing Units), the operating voltages of each device will directly affect the chip performance. Currently, the Dynamic IR Drop Margin is one of the key criteria for chip sign-off. However, the current measurement of the dynamic voltage drop margin does not ensure that the margin is related to the critical path and the voltage drop of the critical path.

[0035] Currently, the functional simulation scenario with the highest power consumption or the fastest current change rate is usually regarded as the dynamic scenario of transient voltage drop caused by a huge increase in current demand, and the voltage drop analysis based on this dynamic scenario is used as a reference for chip issuance. However, this analysis method combines multiple unrelated worst-case scenarios, and these superimposed unrelated events will lead to overdesign and omission of real problems.

[0036] At least one embodiment of the present disclosure provides an analysis method for a digital circuit, an analysis device for a digital circuit, an electronic device, and a non-transitory computer-readable storage medium. The analysis method for the digital circuit includes: determining at least one critical path in the digital circuit; performing critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number; in response to N being greater than 1, performing voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit; where the critical clock cycle detection includes: determining multiple analysis nodes included in the critical path; obtaining multiple simulation waveforms respectively corresponding to the multiple analysis nodes; based on the multiple simulation waveforms, extracting p critical clock cycles corresponding to the critical path, where in each critical clock cycle, the multiple analysis nodes do not satisfy the timing constraint conditions or the multiple analysis nodes all have the maximum delay, and p is a natural number.

[0037] At least one embodiment of the present disclosure provides an analysis method for a digital circuit that analyzes the critical path, associates the critical path with the simulation waveform, finds the exact time points with the worst timing according to the dynamic waveform changes in the simulation waveform that match the critical path, performs voltage drop analysis on these time points, realizes more accurate voltage drop analysis, captures the accurate working voltage change, reduces overdesign in unrelated worst cases, and significantly improves the design margin.

[0038] It should be noted that in the embodiments of the present disclosure, the logic devices include combinational logic devices and sequential logic devices. Here, the sequential logic devices refer to devices such as flip-flops, registers, and latches in digital circuit design. The sequential logic devices have the function of storing and memorizing input signals. When receiving the valid edge or valid level of the clock signal, the sequential logic devices can trigger the storage of the input signal and the change of the output signal state. The combinational logic devices refer to devices such as AND gates and OR gates in digital circuit design that implement logical operations, such as data selectors and numerical comparators. The combinational logic devices do not have the function of storing and memorizing input signals. At any moment, the state of the output signal of the combinational logic device depends on the state of the input signal at the current moment.

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0040] Figure 1 Schematic flowchart of an analysis method for a digital circuit provided by at least one embodiment of the present disclosure.

[0041] For example, as Figure 1 shown, the analysis method for the digital circuit provided by the embodiments of the present disclosure includes steps S10 to S30.

[0042] For example, the digital circuit in the present disclosure may refer to a partial design or a partial module in a large circuit design (such as an integrated circuit). That is, the digital circuit in the present disclosure may be either the entire digital circuit itself or a partial circuit in the entire circuit, and the present disclosure does not limit this.

[0043] In step S10, determine at least one critical path in the digital circuit.

[0044] For example, step S10 may include: performing static timing analysis on the digital circuit to determine at least one critical path, where at least one critical path is a timing path in the digital circuit with a timing margin value less than the margin threshold or a circuit delay value greater than the delay threshold.

[0045] For example, a critical path is also called a critical timing path, which refers to the timing path with the worst timing in the digital circuit.

[0046] For example, in some embodiments, a slack value may be used to characterize whether the timing meets the design requirements when performing static timing analysis on the digital circuit. For example, a positive timing margin value indicates that the timing constraint is met, a negative timing margin value indicates that the timing constraint is not met, and the smaller the timing margin value, the worse the timing.

[0047] Since in this way, the smaller the timing margin value, the worse the timing, and it is more necessary to modify it to meet the timing requirements, at least one circuit path corresponding to the minimum timing margin value can be selected as the critical path. For example, in some examples, the minimum timing margin value corresponds to one timing path, and this one timing path is used as the critical path; for example, in other examples, multiple timing paths may correspond to the minimum timing margin value, and these multiple timing paths are all used as the critical paths.

[0048] For example, in some other embodiments, circuit delay can be used as the selection basis. For example, here the circuit delay can refer to the time required for reference data to be transmitted from one sequential logic device to another sequential logic device via a certain timing path. Here, the reference data is the data collected based on the transition of a clock edge in the sequential logic device. Generally, the larger the circuit delay, the relatively worse the timing of the corresponding circuit path.

[0049] Since in this way, the larger the circuit delay value, the relatively worse its timing, and it is more necessary to modify it to meet the timing requirements. Therefore, at least one timing path corresponding to the maximum circuit delay value can be selected as the critical path.

[0050] For example, at least one timing path with a timing margin value less than the margin threshold can also be used as the critical path; for example, at least one circuit path with a circuit delay value greater than the delay threshold can also be used as the critical path; for example, the circuit delay value and the timing margin value can also be combined as the criterion for judging the critical path, or other methods can also be used to determine the critical path with relatively poor timing. The embodiments of the present disclosure do not limit this.

[0051] For example, the "at least one critical path" here can refer to all the timing paths in the digital circuit with a timing margin value less than the margin threshold or a circuit delay value greater than the delay threshold, or it can also refer to some of the timing paths in the digital circuit with a timing margin value less than the margin threshold or a circuit delay value greater than the delay threshold. For example, in some embodiments, A critical paths are obtained based on the results of static timing analysis, and the timings of the A critical paths do not meet the constraint conditions. Some of the critical paths that are preferentially considered are selected from the A critical paths as the "at least one critical path" here for subsequent critical clock cycle detection. Here, A is a positive integer greater than 1.

[0052] By introducing relevant parameters of static timing analysis to perform a preliminary analysis on the circuit, the critical path is selected from it for subsequent voltage drop analysis, which improves the efficiency and reduces the iteration cycle.

[0053] In step S20, critical clock cycle detection is performed on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path. Here, N is a natural number.

[0054] For example, after obtaining the at least one critical path, critical clock cycle detection is performed on each critical path sequentially or in parallel to obtain the critical clock cycles corresponding to each critical path. For example, the N critical clock cycles include all the critical clock cycles corresponding to all the critical paths.

[0055] For example, if there is no corresponding critical clock cycle for each critical path, then N is equal to 0 here.

[0056] For example, if two critical paths are obtained in step S10, and after performing critical clock cycle detection on the first critical path in step S20, two critical clock cycles are obtained, denoted as critical clock cycle 1 and critical clock cycle 2 respectively, and after performing critical clock cycle detection on the second critical path, one critical clock cycle is obtained, denoted as critical clock cycle 3, then at this time N = 3, and the N critical clock cycles include critical clock cycle 1, critical clock cycle 2, and critical clock cycle 3.

[0057] Figure 2 A schematic flowchart of critical clock cycle detection provided by at least one embodiment of the present disclosure.

[0058] For example, as Figure 2 shown, the critical clock cycle detection provided by the embodiments of the present disclosure includes steps S201 to S203.

[0059] In step S201, determine multiple analysis nodes included in the critical path.

[0060] In step S202, obtain multiple simulation waveforms respectively corresponding to the multiple analysis nodes.

[0061] For example, the simulation waveform is a simulation waveform with timing information. For example, the simulation waveform can be a simulation waveform obtained by simulating the circuit after placement and routing. For example, the simulation waveform is a simulation waveform obtained by simulating a netlist file with delay information added.

[0062] In step S203, based on the multiple simulation waveforms, extract p critical clock cycles corresponding to the critical path.

[0063] For example, in each critical clock cycle, multiple analysis nodes do not satisfy the timing constraint conditions or multiple analysis nodes all have the maximum delay, where p is a natural number.

[0064] For example, step S201 may include: determining multiple second devices included in the critical path and a first device located at the start point of the timing path; using the output terminals of the first device and the multiple second devices as multiple analysis nodes.

[0065] For example, the first device includes a sequential logic device, and the second device includes a combinational logic device. For example, the critical path includes a sequential logic device located at the start point (Start Point) of the timing path, a sequential logic device located at the end point (End Point) of the timing path, and multiple combinational logic devices located on the critical path.

[0066] For example, the first device may further include an input port, that is, the start point of the timing path of the critical path is the input port at this time.

[0067] For example, step S203 may include: obtaining multiple edges corresponding to multiple analysis nodes respectively; determining p critical clock cycles corresponding to the critical path based on the multiple simulation waveforms and the multiple edges, wherein in each critical clock cycle, the multiple simulation waveforms sequentially generate signal transitions corresponding to the corresponding edges.

[0068] For example, obtaining multiple edges corresponding to multiple analysis nodes respectively may include: performing static timing analysis on the digital circuit; determining multiple edges corresponding to multiple analysis nodes respectively based on the static timing analysis result; wherein each edge indicates that when the signal of the corresponding analysis node undergoes a signal transition corresponding to the edge, the corresponding analysis node does not meet the timing constraint or has the maximum delay, and the edge includes a rising edge and / or a falling edge.

[0069] For example, when performing static timing analysis (STA) on the digital circuit, the static timing analysis traverses and analyzes all timing paths in the digital circuit, and performs setup time check, hold time check, etc. on all timing paths according to the topological structure of the circuit netlist to obtain a timing analysis report. The timing analysis report indicates that one or more critical paths with relatively worst timing in the digital circuit need to be optimized, and the timing analysis report will indicate the edges corresponding to each device (such as a standard cell) on the critical path. For example, the edge includes a rising edge and a falling edge. When there is a delay when the clock signal or data signal of the device undergoes a signal transition corresponding to the edge, the delay of these devices makes this timing path a critical path. For example, when the edge is a rising edge, it means that when the clock signal or data signal undergoes a transition from logic 0 (such as a low voltage value) to logic 1 (such as a high voltage value), the timing of the device is the worst or the propagation delay between the input and the output is the largest; for example, when the edge is a falling edge, it means that when the clock signal or data signal undergoes a transition from logic 1 to logic 0, the timing of the device is the worst or the propagation delay between the input and the output is the largest.

[0070] For example, the signal transition corresponding to the rising edge includes the clock signal or data signal undergoing a transition from logic 0 (such as a low voltage value) to logic 1 (such as a high voltage value), and the signal transition corresponding to the falling edge includes the clock signal or data signal undergoing a transition from logic 1 to logic 0.

[0071] For example, each simulation waveform includes multiple clock cycles. Based on multiple simulation waveforms and multiple transition edges, determining p critical clock cycles corresponding to a critical path may include: determining a detection order, where the detection order is obtained by sorting multiple analysis nodes in the direction from the path start point to the path end point of the critical path; traversing multiple simulation waveforms, and based on the detection order, performing a critical clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle, where i is a positive integer and sequentially takes values from 1 to M, and M is the minimum value among the total number of clock cycles included in the multiple simulation waveforms.

[0072] For example, based on the detection order, performing a critical clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle may include: determining the i-th clock cycle in the multiple simulation waveforms as multiple waveform segments to be analyzed; determining whether corresponding signal transitions occur in sequence for the multiple waveform segments according to the detection order, where the corresponding signal transition for each waveform segment is determined by the transition edge corresponding to the analysis node corresponding to each waveform segment; in response to the corresponding signal transitions occurring in sequence for the multiple waveform segments according to the detection order, determining that the i-th clock cycle is a critical clock cycle, and in response to the corresponding signal transitions not occurring in sequence for the multiple waveform segments according to the detection order, determining that the i-th clock cycle is not a critical clock cycle.

[0073] For example, determining whether corresponding signal transitions occur in sequence for the multiple waveform segments according to the detection order may include: traversing the multiple waveform segments according to the detection order, and for the j-th waveform segment among the multiple waveform segments: determining whether a corresponding signal transition occurs in the j-th waveform segment; in response to a corresponding signal transition occurring in the j-th waveform segment, determining whether the (j + 1)-th waveform segment meets the detection conditions, where the detection conditions include that a corresponding signal transition occurs in the (j + 1)-th waveform segment and the occurrence time of the corresponding signal transition in the (j + 1)-th waveform segment is later than the occurrence time of the corresponding signal transition in the j-th waveform segment; in response to the (j + 1)-th waveform segment meeting the detection conditions, continuing to determine whether the (j + 2)-th waveform segment meets the detection conditions until all the multiple waveform segments are traversed, and in response to the (j + 1)-th waveform segment not meeting the detection conditions, determining that the corresponding signal transitions do not occur in sequence for the multiple waveform segments according to the detection order; where j is a positive integer and less than or equal to the total number of the multiple waveform segments.

[0074] That is to say, critical clock cycle detection associates the simulation waveform with the critical path to find one or more precise time points (i.e., critical clock cycles). At these time points, the respective devices on the critical path sequentially experience corresponding signal transitions. At this time, the circuit timing is relatively the worst, with the maximum number of transistors in the circuit being turned on and off simultaneously, as well as transitions in the combinational logic circuit. Consequently, the instantaneous large current generated at these precise time points is relatively the largest, and the voltage drop phenomenon is the most obvious. Therefore, these time points can be used for the voltage drop analysis scenario, and the resulting voltage drop analysis results are also more accurate, approaching the actual worst-case scenario of the circuit operation.

[0075] The following specifically describes the execution process of critical clock cycle detection provided by at least one embodiment of the present disclosure in conjunction with the accompanying drawings.

[0076] Figure 3A It is a schematic diagram of a critical path provided by an embodiment of the present disclosure.

[0077] For example, according to the critical path 1 determined in step S10, as Figure 3A shown, the critical path 1 includes the timing logic device 201 located at the starting point of the timing path, the timing logic device 206 located at the ending point of the timing path, and the combinational logic devices 202, 203, 204, and 205.

[0078] For example, 301 represents the output terminal of the timing logic device 201, 302 represents the output terminal of the combinational logic device 202, 303 represents the output terminal of the combinational logic device 203, 304 represents the output terminal of the combinational logic device 204, and 305 represents the output terminal of the combinational logic device 205.

[0079] For example, when performing critical clock cycle detection on the critical path 1, first in step S201, the output terminal 301 of the timing logic device 201, the output terminal 302 of the combinational logic device 202, the output terminal 303 of the combinational logic device 203, the output terminal 304 of the combinational logic device 204, and the output terminal 305 of the combinational logic device 205 are used as analysis nodes, thereby obtaining the analysis nodes 301, 302, 303, 304, and 305.

[0080] After that, in step S202, multiple simulation waveforms corresponding to the multiple analysis nodes are obtained.

[0081] For example, Figure 3B It is a schematic diagram of multiple simulation waveforms provided by an embodiment of the present disclosure.

[0082] As Figure 3BAs shown, the first line represents the change of the clock signal of the simulation waveform; the second line represents the clock cycle number, which increases starting from 0; the third to seventh lines represent the change of the simulation waveforms of analysis nodes 301 to 305.

[0083] After that, in step S203, based on Figure 3B the multiple simulation waveforms shown, p critical clock cycles corresponding to the critical path are extracted.

[0084] For example, first in step S203, multiple transition edges corresponding to multiple analysis nodes are obtained.

[0085] For example, the transition edges corresponding to each device in the critical path are obtained through the static timing analysis report of the digital circuit, and thus the output end of the device, that is, the transition edge corresponding to the analysis node, is obtained.

[0086] Table 1 shows the transition edges of analysis nodes 301 to 305.

[0087] Table 1 Transition Edges of Analysis Nodes

[0088] Analysis Node Edge Transition Analysis Node 301 Rising Edge (R) Analysis Node 302 Rising Edge (R) Analysis Node 303 Falling Edge (F) Analysis Node 304 Rising Edge (R) Analysis Node 305 Rising Edge (R)

[0089] After that, in step S203, based on Figure 3B the multiple simulation waveforms shown and the multiple transition edges shown in Table 1, p critical clock cycles corresponding to critical path 1 are determined.

[0090] For example, first the detection order is determined. According to the direction from the path start point to the path end point of critical path 1, the detection order is determined as: analysis node 301 -> analysis node 302 -> analysis node 303 -> analysis node 304 -> analysis node 305.

[0091] After that, the waveforms with clock cycle number 0 in the 5 simulation waveforms are used as 5 waveform segments to be analyzed, and it is judged whether the 5 waveform segments sequentially have corresponding signal conversions according to the detection order. For example, as Figure 3B shown, when the clock cycle number is 0, the waveform segments of the 5 analysis nodes do not have signal conversions, so it is determined that the 5 waveform segments do not have corresponding signal conversions, and the clock cycle with clock cycle number 0 is not a critical clock cycle.

[0092] After that, the waveforms with clock cycle number 1 in the 5 simulation waveforms are used as 5 waveform segments to be analyzed, and it is judged whether the 5 waveform segments sequentially have corresponding signal conversions according to the detection order. For example, as Figure 3B shown, when the clock cycle number is 1, the waveform segments of the 5 analysis nodes do not have signal conversions, so it is determined that the 5 waveform segments do not have corresponding signal conversions, and the clock cycle with clock cycle number 1 is not a critical clock cycle.

[0093] After that, take the waveform with the clock cycle number 2 among the 5 simulation waveforms as the 5 waveform segments to be analyzed, and determine whether the 5 waveform segments show corresponding signal transitions in sequence according to the detection order. For example, as Figure 3B shown, the analysis node 301 first shows a signal transition from logic 0 to logic 1, as Figure 3B shown by the jump 1 in it, and this signal transition corresponds to the jump edge (i.e., the rising edge) corresponding to the analysis node 301; after that, the analysis node 302 shows a signal transition from logic 0 to logic 1, as Figure 3B shown by the jump 2 in it, and this signal transition corresponds to the jump edge (i.e., the rising edge) corresponding to the analysis node 302, and the occurrence time of the signal transition of the analysis node 302 is later than the occurrence time of the signal transition of the analysis node 301; after that, the analysis node 303 shows a signal transition from logic 1 to logic 0, as Figure 3B shown by the jump 3 in it, and this signal transition corresponds to the jump edge (i.e., the falling edge) corresponding to the analysis node 301, and the occurrence time of the signal transition of the analysis node 303 is later than the occurrence time of the signal transition of the analysis node 302; after that, the analysis node 304 shows a signal transition from logic 0 to logic 1, as Figure 3B shown by the jump 4 in it, and this signal transition corresponds to the jump edge (i.e., the rising edge) corresponding to the analysis node 304, and the occurrence time of the signal transition of the analysis node 304 is later than the occurrence time of the signal transition of the analysis node 303; finally, the analysis node 305 shows a signal transition from logic 0 to logic 1, as Figure 3B shown by the jump 5 in it, and this signal transition corresponds to the jump edge (i.e., the rising edge) corresponding to the analysis node 305, and the occurrence time of the signal transition of the analysis node 305 is later than the occurrence time of the signal transition of the analysis node 304.

[0094] Thus, it is determined that the 5 waveform segments show corresponding signal transitions in sequence according to the detection order, and the clock cycle with the clock cycle number 2 is determined as the critical clock cycle, which can be used as an alternative analysis scenario for subsequent voltage drop analysis.

[0095] After that, perform the above-mentioned critical clock cycle detection on clock cycles such as the clock cycle number 3 in sequence until multiple clock cycles are traversed, which will not be elaborated here.

[0096] Figure 4A It is a schematic diagram of the critical path provided by another embodiment of the present disclosure.

[0097] For example, according to the critical path 2 determined in step S10, as Figure 4AAs shown, the critical path 2 includes a timing logic device 401 at the start of the timing path, a timing logic device 406 at the end of the timing path, combinational logic devices 402, 403, 404, and 405.

[0098] For example, 501 represents the output terminal of the timing logic device 401, 502 represents the output terminal of the combinational logic device 402, 503 represents the output terminal of the combinational logic device 403, 504 represents the output terminal of the combinational logic device 404, and 505 represents the output terminal of the combinational logic device 405.

[0099] For example, when performing critical clock cycle detection on the critical path 2, first in step S201, the output terminal 501 of the timing logic device 401, the output terminal 502 of the combinational logic device 402, the output terminal 503 of the combinational logic device 403, the output terminal 504 of the combinational logic device 404, and the output terminal 505 of the combinational logic device 405 are used as analysis nodes, thereby obtaining analysis nodes 501, 502, 503, 504, and 505.

[0100] After that, in step S202, multiple simulation waveforms corresponding to the multiple analysis nodes are obtained.

[0101] For example, Figure 4B is a schematic diagram of multiple simulation waveforms provided by another embodiment of the present disclosure.

[0102] As Figure 4B shown, the first row represents the change of the clock signal of the simulation waveform; the second row represents the clock cycle number, for example Figure 4B fully shows the waveform change of 5 simulation waveforms when the clock cycle number is i; the third row to the seventh row represent the simulation waveform changes of the analysis nodes 501 to 505.

[0103] After that, in step S203, based on Figure 4B the multiple simulation waveforms shown, p critical clock cycles corresponding to the critical path are extracted.

[0104] For example, first in step S203, multiple transition edges corresponding to the multiple analysis nodes are obtained.

[0105] Table 2 shows the transition edges of the analysis nodes 501 to 505.

[0106] Table 2 Transition Edges of Analysis Nodes

[0107] Analysis Node Edge Transition Analysis Node 501 Rising Edge (R) Analysis Node 502 Rising Edge (R) Analysis Node 503 Rising Edge (R) Analysis Node 504 Rising Edge (R) Analysis Node 505 Rising Edge (R)

[0108] After that, based on Figure 4BDetermine p critical clock cycles of the critical path 2 based on the multiple simulation waveforms shown and the multiple transition edges shown in Table 2.

[0109] For example, first determine the detection order. According to the direction of the critical path 2 from the path start point to the path end point, the detection order is determined as: analyze node 501 -> analyze node 502 -> analyze node 503 -> analyze node 504 -> analyze node 505.

[0110] For example, take the clock cycle number i as an example for illustration.

[0111] For example, take the waveforms with the clock cycle number i in the 5 simulation waveforms as the 5 waveform segments to be analyzed. As Figure 4B shown, among the 5 waveform segments, first, a signal transition from logic 0 to logic 1 occurs at node 501, as Figure 4B shown by transition 1' in; then, a signal transition from logic 0 to logic 1 occurs at node 502, as Figure 4B shown by transition 2' in; then, a signal transition from logic 0 to logic 1 occurs at node 503, as Figure 4B shown by transition 3' in; then, a signal transition from logic 0 to logic 1 occurs at node 504, as Figure 4B shown by transition 4' in; finally, a signal transition from logic 0 to logic 1 occurs at node 505, as Figure 4B shown by transition 5' in. That is to say, the 5 waveform segments sequentially undergo signal transitions corresponding to the transition edges corresponding to each analysis node according to the detection order, thereby determining the clock cycle with the clock cycle number i as the critical clock cycle.

[0112] The analysis method of the digital circuit provided by at least one embodiment of the present disclosure associates the critical path with the simulation waveforms, ensuring that the simulation waveforms cover the most critical timing paths that can be used for voltage drop (IR Drop) analysis, that is, finding the exact time points when the circuit is in the worst case according to the simulation waveforms to capture a more real and accurate voltage drop analysis scenario.

[0113] In step S30, in response to N being greater than 1, perform voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit.

[0114] For example, step S30 may include: performing voltage drop analysis on the N alternative analysis scenarios respectively to obtain N analysis results corresponding to the N alternative analysis scenarios respectively; based on the N analysis results, use the alternative analysis scenario with the largest voltage drop or the highest current change rate among the N alternative analysis scenarios as the voltage drop analysis scenario, and use the analysis result corresponding to the voltage drop analysis scenario as the voltage drop analysis result corresponding to the digital circuit.

[0115] That is to say, after obtaining the critical clock cycles, since the time points where these critical clock cycles are located indicate that the circuit may be in the worst timing state, and at the same moment, there are the most transistor turn - ons and turn - offs in the circuit, as well as the transitions of the combinational logic circuit, the instantaneous large current generated at these time points is relatively the largest, and the voltage drop phenomenon is the most obvious. Conducting voltage drop analysis at these time points can obtain more accurate voltage drop analysis results. Moreover, select one scenario with the most obvious voltage drop phenomenon from these time points. For example, select a time point with the largest voltage drop or the highest current change rate among these time points as the voltage drop analysis scenario, and use the analysis result obtained from the voltage drop analysis scenario as the voltage drop analysis result corresponding to the digital circuit, accurately mark the operating voltages of each analysis node on the critical path, thereby obtaining a voltage drop analysis result closely related to the critical path, avoiding over - design in irrelevant worst - case scenarios, improving the design margin, and enhancing the design performance of the digital circuit.

[0116] For example, the digital circuit analysis method provided by at least one embodiment of the present disclosure may further include: according to the voltage drop analysis result, determining a plurality of voltage drop voltages corresponding to a plurality of analysis nodes one by one; adjusting the operating voltages of the plurality of analysis nodes to the corresponding voltage drop voltages; performing static timing analysis on the digital circuit after voltage adjustment to determine the convergence situation of the timing of the critical path in the voltage drop analysis scenario.

[0117] For example, according to the voltage drop analysis result, back - annotate the operating voltages of each analysis node to the circuit, and perform static timing analysis on the circuit to determine whether the timing can still converge in the worst case of IR Drop.

[0118] For example, the digital circuit analysis method provided by at least one embodiment of the present disclosure may further include: performing static timing analysis on the digital circuit after voltage adjustment, calculating the timing margin of the digital circuit in the voltage drop analysis scenario; based on the timing margin, determining the timing sign - off standard of the digital circuit.

[0119] According to the voltage drop analysis result obtained in step S30, determine the operating voltages of each analysis node and back - annotate them to the circuit. Perform static timing analysis on the circuit with the operating voltages marked, and obtain a more accurate timing sign - off margin based on the static timing analysis result, thereby improving the design margin, avoiding over - design, and providing a more generous timing design space for other associated circuit modules.

[0120] For example, the digital circuit analysis method provided by at least one embodiment of the present disclosure may further include: in response to N being equal to 0, determining that the switching coverage rate in the gate - level simulation of the digital circuit is not satisfied.

[0121] The digital circuit backend design process includes gate level simulation. Gate level simulation means that after the integrated circuit layout and routing, according to the timing file, such as the SDF (Standard Delay Format) file, the timing information is back-annotated to the post-layout netlist, and the netlist with timing information is simulated. Gate level simulation is used to check the consistency (logic Equivalence check) between the simulation of the register transfer level file and the post-layout netlist after physical implementation.

[0122] The measurement method of gate level simulation is usually fault simulation, for example, creating a set of tests to verify in the physically implemented circuit. The design method of the digital circuit provided by at least one embodiment of the present disclosure can measure whether the test group of the fault simulation of the gate level simulation is complete by the number of critical clock cycles, that is, whether the toggle coverage is appropriate.

[0123] For example, if N is equal to 0, that is, there is no critical clock cycle with the worst timing in the simulation waveform of the digital circuit, it means that the fault simulation of the gate level simulation of the circuit is not sufficient and does not cover the worst scenario that needs to be tested, and corresponding test cases need to be added.

[0124] Corresponding to the above analysis method of the digital circuit, at least one embodiment of the present disclosure also provides an analysis device for a digital circuit. Figure 5A It is a schematic block diagram of an analysis device for a digital circuit provided by at least one embodiment of the present disclosure.

[0125] For example, as Figure 5A shown, the analysis device 600 of the digital circuit includes: a determination unit 501, a detection unit 502, and an analysis unit 503.

[0126] The determination unit 501 is configured to determine at least one critical path in the digital circuit.

[0127] The detection unit 502 is configured to perform critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number.

[0128] The analysis unit 503 is configured to, in response to N being greater than 1, perform voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit.

[0129] For example, when the determination unit 501 determines at least one critical path in a digital circuit, the following steps are included: performing static timing analysis on the digital circuit to determine at least one critical path, where the at least one critical path is a timing path in the digital circuit with a timing margin value less than a margin threshold or a circuit delay value greater than a delay threshold.

[0130] For example, when the analysis unit 503 performs voltage drop analysis on N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit, the following steps are included: performing voltage drop analysis on the N alternative analysis scenarios respectively to obtain N analysis results corresponding to the N alternative analysis scenarios respectively; based on the N analysis results, taking the alternative analysis scenario with the largest voltage drop or the highest current change rate among the N alternative analysis scenarios as the voltage drop analysis scenario, and taking the analysis result corresponding to the voltage drop analysis scenario as the voltage drop analysis result corresponding to the digital circuit.

[0131] Figure 5B A schematic block diagram of a detection unit provided by at least one embodiment of the present disclosure.

[0132] For example, as Figure 5B shown, the detection unit includes: an analysis node determination subunit 5021, an acquisition subunit 5022, and an extraction subunit 5023.

[0133] The analysis node determination subunit 5021 is configured to determine multiple analysis nodes included in the critical path.

[0134] The acquisition subunit 5022 is configured to acquire multiple simulation waveforms respectively corresponding to the multiple analysis nodes.

[0135] The extraction subunit 5023 is configured to extract p critical clock cycles corresponding to the critical path based on the multiple simulation waveforms, where in each critical clock cycle, the multiple analysis nodes do not satisfy the timing constraint conditions or the multiple analysis nodes all have the maximum delay, and p is a natural number.

[0136] For example, when the analysis node determination subunit 5021 determines multiple analysis nodes included in the critical path, the following steps are included: determining multiple second devices included in the critical path and a first device located at the start point of the timing path; taking the output terminals of the first device and the multiple second devices as the multiple analysis nodes.

[0137] For example, the extraction subunit 5023 includes a transition edge acquisition subunit 5024 and a critical clock cycle detection subunit 5025.

[0138] The transition edge acquisition subunit 5024 is configured to acquire multiple transition edges respectively corresponding to the multiple analysis nodes.

[0139] The critical clock cycle detection subunit 5025 is configured to determine p critical clock cycles corresponding to the critical path based on a plurality of simulation waveforms and a plurality of transition edges. Among them, in each critical clock cycle, the plurality of simulation waveforms sequentially generate signal transitions corresponding to the corresponding transition edges.

[0140] For example, when the transition edge acquisition subunit 5024 executes to acquire a plurality of transition edges respectively corresponding to a plurality of analysis nodes, it includes performing the following steps: performing static timing analysis on the digital circuit; determining a plurality of transition edges respectively corresponding to the plurality of analysis nodes based on the static timing analysis result; among them, each transition edge indicates that when the signal of the corresponding analysis node undergoes a signal transition corresponding to the transition edge, the corresponding analysis node does not meet the timing constraint or has the maximum delay, and the transition edge includes a rising edge and / or a falling edge.

[0141] For example, when the critical clock cycle detection subunit 5025 executes to determine p critical clock cycles corresponding to the critical path based on a plurality of simulation waveforms and a plurality of transition edges, it includes performing the following steps: determining the detection order, where the detection order is obtained by sorting the plurality of analysis nodes in the direction from the path start point of the critical path to the path end point of the critical path; traversing the plurality of simulation waveforms, and based on the detection order, performing a critical clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle, where i is a positive integer and sequentially takes values from 1 to M, and M is the minimum value among the total number of clock cycles included in the plurality of simulation waveforms.

[0142] For example, when the critical clock cycle detection subunit 5025 executes to perform a critical clock cycle determination on the i-th clock cycle based on the detection order to determine whether the i-th clock cycle is a critical clock cycle, it includes performing the following steps: determining the i-th clock cycle in the plurality of simulation waveforms as a plurality of waveform segments to be analyzed; determining whether the plurality of waveform segments sequentially undergo corresponding signal transitions according to the detection order, where each signal transition corresponding to each waveform segment is determined by the transition edge corresponding to the analysis node corresponding to each waveform segment; in response to the plurality of waveform segments sequentially undergoing corresponding signal transitions according to the detection order, determining that the i-th clock cycle is a critical clock cycle, and in response to the plurality of waveform segments not sequentially undergoing corresponding signal transitions according to the detection order, determining that the i-th clock cycle is not a critical clock cycle.

[0143] For example, when the critical clock cycle detection subunit 5025 determines whether corresponding signal transitions occur in sequence for multiple waveform segments according to the detection order, the following steps are included: traversing the multiple waveform segments according to the detection order, and for the j-th waveform segment among the multiple waveform segments: determining whether a corresponding signal transition occurs in the j-th waveform segment; in response to a corresponding signal transition occurring in the j-th waveform segment, determining whether the (j + 1)-th waveform segment meets the detection conditions, where the detection conditions include that a corresponding signal transition occurs in the (j + 1)-th waveform segment, and the occurrence time of the corresponding signal transition in the (j + 1)-th waveform segment is later than the occurrence time of the corresponding signal transition in the j-th waveform segment; in response to the (j + 1)-th waveform segment meeting the detection conditions, continuing to determine whether the (j + 2)-th waveform segment meets the detection conditions until all the multiple waveform segments are traversed, and in response to the (j + 1)-th waveform segment not meeting the detection conditions, determining that the corresponding signal transitions do not occur in sequence for the multiple waveform segments according to the detection order; where j is a positive integer and less than or equal to the total number of the multiple waveform segments.

[0144] For example, in some embodiments, the analysis device 600 of the digital circuit may further include a timing convergence analysis unit.

[0145] For example, the timing convergence analysis unit is configured to determine the voltage drops corresponding to a plurality of analysis nodes according to the voltage drop analysis result; adjust the operating voltages of the plurality of analysis nodes to the corresponding voltage drop voltages; perform static timing analysis on the digital circuit after voltage adjustment to determine the convergence condition of the timing of the critical path in the voltage drop analysis scenario.

[0146] For example, in some embodiments, the analysis device 600 of the digital circuit may further include a margin determination unit.

[0147] For example, the margin determination unit is configured to perform static timing analysis on the digital circuit after voltage adjustment, calculate the timing margin of the digital circuit in the voltage drop analysis scenario; and determine the timing sign-off standard of the digital circuit based on the timing margin.

[0148] For example, the determination unit 501, the detection unit 502, and the analysis unit 503 include code and programs stored in a memory; a processor can execute the code and programs to implement some or all of the functions of the determination unit 501, the detection unit 502, and the analysis unit 503 as described above. For example, the determination unit 501, the detection unit 502, and the analysis unit 503 can be dedicated hardware devices for implementing some or all of the functions of the determination unit 501, the detection unit 502, and the analysis unit 503 as described above. For example, the determination unit 501, the detection unit 502, and the analysis unit 503 can be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiments of the present application, the circuit board or the combination of multiple circuit boards can include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memory and executable by the processors.

[0149] It should be noted that the determination unit 501 is used to implement Figure 1 step S10 shown, the detection unit 502 is used to implement Figure 1 step S20 shown, and the analysis unit 503 is used to implement Figure 1 step S30 shown. Therefore, the specific description of the determination unit 501 can refer to the relevant description of step S10 in the embodiments of the above-mentioned analysis method of digital circuits Figure 1 shown, the specific description of the detection unit 502 can refer to the relevant description of step S20 in the embodiments of the above-mentioned analysis method of digital circuits Figure 1 shown, and the specific description of the analysis unit 503 can refer to the relevant description of step S30 in the embodiments of the above-mentioned analysis method of digital circuits Figure 1 shown.

[0150] It should be noted that the analysis node determination subunit 5021 is used to implement Figure 2 step S201 shown, the acquisition subunit 5022 is used to implement Figure 2 step S202 shown, and the extraction subunit 5023 is used to implement Figure 2 step S203 shown. Therefore, the specific description of the analysis node determination subunit 5021 can refer to the relevant description of step S201 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown, the specific description of the acquisition subunit 5022 can refer to the relevant description of step S202 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown, and the specific description of the extraction subunit 5023 can refer to the relevant description of step S203 in the embodiments of the above-mentioned analysis method of digital circuits Figure 2 shown.

[0151] In addition, the analysis device of the digital circuit can achieve technical effects similar to those of the aforementioned digital circuit analysis method, which will not be elaborated here.

[0152] At least one embodiment of the present disclosure further provides an electronic device. Figure 6 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0153] For example, as Figure 6 shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004. Components such as the processor 1001, the communication interface 1002, and the memory 1003 can also communicate through a network connection. The present disclosure does not limit the type and function of the network here.

[0154] For example, the memory 1003 is used to non-transiently store computer-executable instructions. When the processor 1001 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 1001, implement the digital circuit analysis method according to any of the above embodiments. For the specific implementation of each step of the digital circuit analysis method and the related explanatory content, reference can be made to the embodiments of the digital circuit analysis method above, which will not be elaborated here.

[0155] For example, the implementation manner in which the processor 1001 executes the program stored on the memory 1003 to implement the digital circuit analysis method is the same as the implementation manner mentioned in the embodiment part of the aforementioned digital circuit analysis method, and will not be elaborated here either.

[0156] For example, the communication bus 1004 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0157] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0158] For example, the processor 1001 can control other components in the electronic device to perform desired functions. The processor 1001 can be a Central Processing Unit (CPU), a Network Processor (NP), etc., and can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The Central Processing Unit (CPU) can be of the X86 or ARM architecture, etc.

[0159] For example, the memory 1003 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage media, and the processor 1001 may run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data, etc. may also be stored in the storage media.

[0160] For example, for a detailed description of the process of the electronic device performing the analysis of the digital circuit, reference may be made to the relevant description in the embodiments of the method for analyzing the digital circuit, and repeated parts will not be elaborated.

[0161] Figure 7 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 7 shown, one or more computer-executable instructions 1101 may be non-temporarily stored on the storage medium 1100. For example, when the computer-executable instructions 1101 are executed by the processor, one or more steps in the method for analyzing the digital circuit described above may be executed.

[0162] For example, the storage medium 1100 may be applied to the above-mentioned electronic device and / or the digital circuit analysis device 1400. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

[0163] For example, for the description of the storage medium 1100, reference may be made to the description of the memory in the embodiments of the electronic device, and repeated parts will not be elaborated.

[0164] For the present disclosure, the following points need to be noted:

[0165] (1) The drawings in the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0166] (2) For clarity, in the drawings used to describe the embodiments of the present invention, the thickness and dimensions of layers or structures are enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" on or under the other element, or there may be intermediate elements.

[0167] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0168] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for analyzing a digital circuit, comprising: Determining at least one critical path in the digital circuit, where the at least one critical path is a timing path in the digital circuit with a timing margin value less than a margin threshold or a circuit delay value greater than a delay threshold; Performing critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number; In response to N being greater than 1, performing voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit; Wherein, the critical clock cycle detection includes: Determining a plurality of analysis nodes included in the critical path; Obtaining a plurality of simulation waveforms respectively corresponding to the plurality of analysis nodes; Based on the plurality of simulation waveforms, extracting p critical clock cycles corresponding to the critical path, where in each critical clock cycle, the plurality of analysis nodes do not satisfy the timing constraint conditions or the plurality of analysis nodes all have a maximum delay, where p is a natural number.

2. The analysis method according to claim 1, wherein Determining at least one critical path in the digital circuit includes: Performing static timing analysis on the digital circuit to determine the at least one critical path.

3. The analysis method according to claim 1, wherein, Determining a plurality of analysis nodes included in the critical path includes: Determining a plurality of second devices included in the critical path and a first device located at the start point of the timing path; Taking the output terminals of the first device and the plurality of second devices as the plurality of analysis nodes.

4. The analysis method according to claim 1, wherein Each simulation waveform is a simulation waveform with timing information.

5. The analysis method according to claim 1, wherein, Based on the plurality of simulation waveforms, extracting p critical clock cycles corresponding to the critical path includes: Obtaining a plurality of transition edges respectively corresponding to the plurality of analysis nodes; Based on the plurality of simulation waveforms and the plurality of transition edges, determining p critical clock cycles corresponding to the critical path, where in each critical clock cycle, the plurality of simulation waveforms sequentially generate signal transitions corresponding to the corresponding transition edges.

6. The analysis method according to claim 5, wherein Obtaining a plurality of transition edges respectively corresponding to the plurality of analysis nodes includes: Performing static timing analysis on the digital circuit; Based on the static timing analysis result, determining a plurality of transition edges respectively corresponding to the plurality of analysis nodes; Wherein, each transition edge indicates that when the signal of the corresponding analysis node undergoes a signal transition corresponding to the transition edge, the corresponding analysis node does not satisfy the timing constraint or has a maximum delay, and the transition edge includes a rising edge and / or a falling edge.

7. The analysis method according to claim 5, wherein Each simulation waveform includes a plurality of clock cycles, Based on the plurality of simulation waveforms and the plurality of transition edges, determining p critical clock cycles corresponding to the critical path includes: Determining a detection order, where the detection order is obtained by sorting the plurality of analysis nodes in the direction from the start point of the critical path to the end point of the critical path; Traversing the plurality of simulation waveforms, and based on the detection order, performing critical clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle, Wherein, i is a positive integer and takes values from 1 to M in sequence, and M is the minimum value among the total number of clock cycles included in the multiple simulation waveforms.

8. The analysis method according to claim 7, wherein Based on the detection order, perform critical clock cycle determination on the i-th clock cycle to determine whether the i-th clock cycle is a critical clock cycle, including: Determine the i-th clock cycle in the multiple simulation waveforms as multiple waveform segments to be analyzed; Judge whether corresponding signal transitions occur in sequence for the multiple waveform segments according to the detection order, wherein the corresponding signal transition for each waveform segment is determined by the transition edge corresponding to the analysis node corresponding to each waveform segment; In response to the corresponding signal transitions occurring in sequence for the multiple waveform segments according to the detection order, determine that the i-th clock cycle is a critical clock cycle; In response to the corresponding signal transitions not occurring in sequence for the multiple waveform segments according to the detection order, determine that the i-th clock cycle is not a critical clock cycle.

9. The analysis method according to claim 8, wherein Judging whether corresponding signal transitions occur in sequence for the multiple waveform segments according to the detection order includes: Traverse the multiple waveform segments according to the detection order. For the j-th waveform segment among the multiple waveform segments: Judge whether a corresponding signal transition occurs in the j-th waveform segment; In response to a corresponding signal transition occurring in the j-th waveform segment, judge whether the (j + 1)-th waveform segment meets the detection conditions, wherein the detection conditions include that a corresponding signal transition occurs in the (j + 1)-th waveform segment, and the occurrence time of the corresponding signal transition in the (j + 1)-th waveform segment is later than the occurrence time of the corresponding signal transition in the j-th waveform segment; In response to the (j + 1)-th waveform segment meeting the detection conditions, continue to judge whether the (j + 2)-th waveform segment meets the detection conditions until the traversal of the multiple waveform segments is completed; In response to the (j + 1)-th waveform segment not meeting the detection conditions, determine that the corresponding signal transitions do not occur in sequence for the multiple waveform segments according to the detection order; Wherein, j is a positive integer and less than or equal to the total number of waveform segments.

10. The analysis method according to claim 1, wherein, Perform voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit, including: Perform voltage drop analysis on the N alternative analysis scenarios respectively to obtain N analysis results corresponding to the N alternative analysis scenarios respectively; Based on the N analysis results, use the alternative analysis scenario with the largest voltage drop or the highest current change rate among the N alternative analysis scenarios as the voltage drop analysis scenario, and use the analysis result corresponding to the voltage drop analysis scenario as the voltage drop analysis result corresponding to the digital circuit.

11. The analysis method according to claim 10 further includes: Determine multiple voltage drop voltages corresponding to the multiple analysis nodes one by one according to the voltage drop analysis result; Adjust the operating voltages of the multiple analysis nodes to the corresponding voltage drop voltages; Perform static timing analysis on the digital circuit after voltage adjustment to determine the convergence situation of the timing of the critical path in the voltage drop analysis scenario.

12. The analysis method according to claim 11 further includes: Performing static timing analysis on the digital circuit after the voltage regulation, and calculating the timing margin of the digital circuit in the voltage drop analysis scenario; Determining the timing sign-off standard of the digital circuit based on the timing margin.

13. The analysis method according to any one of claims 1-12 further includes: In response to N being equal to 0, determining that the switching coverage rate in the gate-level simulation of the digital circuit is not satisfied.

14. An analysis device for a digital circuit includes: A determination unit configured to determine at least one critical path in the digital circuit, where the at least one critical path is a timing path in the digital circuit with a timing margin value less than a margin threshold or a circuit delay value greater than a delay threshold; A detection unit configured to perform critical clock cycle detection on each of the at least one critical path to obtain N critical clock cycles corresponding to the at least one critical path, where N is a natural number; An analysis unit configured to, in response to N being greater than 1, perform voltage drop analysis on the N critical clock cycles as N alternative analysis scenarios respectively to determine the voltage drop analysis result corresponding to the digital circuit; Wherein, the critical clock cycle detection includes: Determining a plurality of analysis nodes included in the critical path, Obtaining a plurality of simulation waveforms respectively corresponding to the plurality of analysis nodes, Based on the plurality of simulation waveforms, extracting p critical clock cycles corresponding to the critical path, where in each critical clock cycle, the plurality of analysis nodes do not satisfy the timing constraint conditions or the plurality of analysis nodes all have the maximum delay, where p is a natural number.

15. An electronic device includes: A memory that stores computer-executable instructions non-transiently; A processor configured to run the computer-executable instructions, Wherein, when the computer-executable instructions are run by the processor, the analysis method of the digital circuit according to any one of claims 1-13 is implemented.

16. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the analysis method of the digital circuit according to any one of claims 1-13 is implemented.

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