Digital analog converter, chip and electronic device

Abstract

Embodiments of the present disclosure provide a digital-to-analog converter, a chip and an electronic device. The digital-to-analog converter comprises: a PWM integration circuit and a resistance network type circuit; wherein any one of the PWM integration circuit and the resistance network type circuit is used to realize a high-bit part of digital-to-analog conversion, and the other circuit is used to realize a low-bit part of digital-to-analog conversion; an input end of a first circuit used to realize high-bit digital-to-analog conversion is connected with a reference voltage; an output end of the first circuit is connected with an input end of a second circuit used to realize low-bit digital-to-analog conversion; and an output end of the second circuit outputs an output voltage of the digital-to-analog converter. Embodiments of the present disclosure provide a digital-to-analog converter, a chip and an electronic device, which can combine the advantages of high precision of the PWM integration circuit and high conversion speed of the resistance network type circuit, and can realize a high-precision digital-to-analog converter which takes into account speed and precision.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to digital-to-analog converters, chips, and electronic devices. Background Technology

[0002] Digital-to-analog converters (DACs) are widely used in various integrated circuits. Existing DACs can be implemented using resistor network circuit structures, but this approach has limited achievable accuracy. DACs can also be implemented using PWM integrator circuits, but this approach results in lower conversion speeds. In short, existing DACs cannot simultaneously achieve both high conversion speeds and high accuracy. Summary of the Invention

[0003] The embodiments described herein provide a digital-to-analog converter, a chip, and an electronic device.

[0004] According to a first aspect of this disclosure, a digital-to-analog converter is provided. The digital-to-analog converter includes: a PWM integrator circuit and a resistor network type circuit;

[0005] Wherein, either the PWM integrator circuit or the resistor network circuit is used to implement the high-order part of the digital-to-analog conversion, and the other circuit is used to implement the low-order part of the digital-to-analog conversion;

[0006] The input terminal of the first circuit used to implement the high-order part of the digital-to-analog conversion is connected to the reference voltage;

[0007] The output terminal of the first circuit is connected to the input terminal of the second circuit used to implement the low-order part of the digital-to-analog conversion;

[0008] The output terminal of the second circuit outputs the output voltage of the digital-to-analog converter.

[0009] In some embodiments of this disclosure, the PWM integrator circuit is used to implement the high-order portion of the digital-to-analog conversion;

[0010] The resistor network circuit is used to implement the low-order part of the digital-to-analog conversion;

[0011] The input terminal of the PWM integrator circuit is connected to the reference voltage;

[0012] The output terminal of the PWM integrator circuit is connected to the input terminal of the resistor network circuit;

[0013] The output terminal of the resistor network circuit outputs the output voltage of the digital-to-analog converter.

[0014] In some embodiments of this disclosure, the resistor network circuit is used to implement the high-order portion of the digital-to-analog conversion;

[0015] The PWM integrator circuit is used to implement the low-order part of the digital-to-analog conversion;

[0016] The input terminal of the resistor network circuit is connected to the reference voltage;

[0017] The output terminal of the resistor network circuit is connected to the input terminal of the PWM integrator circuit;

[0018] The output terminal of the PWM integrator circuit outputs the output voltage of the digital-to-analog converter.

[0019] In some embodiments of this disclosure, the resistor network type circuit includes any one of the following: a thermometer code resistor string structure, an R-2R resistor string structure, and a multi-stage cascaded resistor string voltage divider structure.

[0020] In some embodiments of this disclosure, the R-2R resistor string structure includes: N first resistors, N+1 second resistors, and N+1 single-pole double-throw switches;

[0021] In this circuit, the N first resistors are connected in series, and the first end of one of the N first resistors serves as the first input terminal of the resistor network circuit. The first ends of the remaining first resistors are coupled to the second end of the previous first resistor.

[0022] Each of the N+1 second resistors and a corresponding single-pole double-throw switch among the N+1 single-pole double-throw switches form a second resistor-switch group. The first end of each second resistor-switch group is coupled to the second end of the corresponding first resistor. The second end of each second resistor-switch group is connected to the second input end of the resistor network circuit. The third end of each second resistor-switch group is connected to the output end of the R-2R resistor string structure.

[0023] Where N is an integer greater than 1; the resistance value of the second resistor is twice the resistance value of the first resistor.

[0024] In some embodiments of this disclosure, the resistor network circuit includes a first input terminal and a second input terminal;

[0025] The PWM integrator circuit includes: two sub-PWM integrator circuits;

[0026] In this circuit, the output terminal of one of the sub-PWM integrator circuits is connected to the first input terminal of the resistor network circuit, and the output terminal of the other sub-PWM integrator circuit is connected to the second input terminal of the resistor network circuit.

[0027] The sub-PWM integrator circuit includes: a single-pole double-throw switch, a third resistor, a capacitor, and an operational amplifier;

[0028] Wherein, the first terminal of the single-pole double-throw switch is connected to the first terminal of the third resistor, the second terminal of the single-pole double-throw switch is connected to the reference voltage, and the third terminal of the single-pole double-throw switch is grounded;

[0029] The second terminal of the third resistor is connected to the non-inverting input terminal of the operational amplifier;

[0030] The first terminal of the capacitor is connected to the non-inverting input terminal of the operational amplifier, and the second terminal of the capacitor is grounded.

[0031] The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier;

[0032] The output terminal of the operational amplifier is the output terminal of the sub-PWM integrator circuit;

[0033] The conduction state of the single-pole double-throw switches in the two sub-PWM integrator circuits is controlled by different PWM control signals.

[0034] In some embodiments of this disclosure, the PWM integrator circuit is configured as follows:

[0035] The conduction state of the single-pole double-throw switch in the first sub-PWM integrator circuit of the two sub-PWM integrator circuits is controlled by PWM control signal 1;

[0036] The conduction state of the single-pole double-throw switch in the second sub-PWM integrator circuit of the two sub-PWM integrator circuits is controlled by PWM control signal 2.

[0037] The first sub-PWM integrator circuit satisfies the following first equation:

[0038]

[0039] Wherein, Vo1 is the output voltage of the first sub-PWM integrator circuit; M is the number of integration cycles of the PWM control signal 1; the accuracy of the high-order bit-to-analog conversion is αbit; and Vref is the reference voltage.

[0040] The second sub-PWM integrator circuit satisfies the following second equation:

[0041]

[0042] Where Vo1′ is the output voltage of the second sub-PWM integrator circuit; M-1 is the number of integration cycles of the PWM control signal 2.

[0043] In some embodiments of this disclosure, the R-2R resistor string structure is configured as follows:

[0044] The R-2R resistor string structure satisfies the following third equation:

[0045]

[0046] Wherein, R is the resistance value of the first resistor, A is the resistance mismatch of the R-2R resistor string structure, and the digital-to-analog conversion accuracy of the R-2R resistor string structure is βbit.

[0047] According to a second aspect of this disclosure, a chip is provided. The chip includes a digital-to-analog converter as described in a first aspect of this disclosure.

[0048] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in the second aspect of this disclosure.

[0049] The embodiments described herein provide a digital-to-analog converter, chip, and electronic device that have at least the following advantages:

[0050] 1. In the embodiments of this disclosure, a segmented processing method is used to implement the digital-to-analog converter. The required accuracy of the entire digital-to-analog converter is divided into two parts—a high-order part and a low-order part. Different circuit structures are used for the high-order part and the low-order part respectively. The high accuracy of the PWM integrator circuit and the resistor network circuit are combined to realize the overall digital-to-analog converter. This disclosure combines the advantages of the high accuracy of the PWM integrator circuit and the fast conversion speed of the resistor network circuit, which can balance speed and accuracy to achieve a high-precision digital-to-analog converter.

[0051] 2. In the embodiments of this disclosure, the resistor network circuit realizes the low-order digital-to-analog conversion, and the PWM integral circuit realizes the high-order digital-to-analog conversion. This scheme can greatly reduce the static power consumption of the digital-to-analog converter, ensure the working life of the chip, and reduce the power consumption of the digital-to-analog converter system. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0053] Figure 1 This is a schematic diagram of the timing structure of a PWM integrator circuit.

[0054] Figure 2 This is a schematic diagram of a digital-to-analog converter;

[0055] Figure 3 This is a schematic diagram of another type of digital-to-analog converter;

[0056] Figure 4 This is an exemplary circuit diagram of an R-2R resistor string structure;

[0057] Figure 5 This is an exemplary circuit diagram of a sub-PWM integrator circuit;

[0058] Figure 6 This is an exemplary circuit diagram of a digital-to-analog converter;

[0059] Figure 7 This is a schematic diagram of the timing structure of the first sub-PWM integrator circuit and the second sub-PWM integrator circuit.

[0060] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0063] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0064] Existing digital-to-analog converters (DACs) can be implemented using resistor network circuit structures or PWM integrator circuits. However, the highest accuracy achievable with resistor network circuit structures is limited, often falling short of the required precision. Generally, a resistor network-based DAC can only achieve a maximum accuracy of 12 bits. Therefore, a simple resistor network structure is insufficient for implementing DACs exceeding 12 bits. Furthermore, resistor network structures are prone to significant errors due to resistor mismatch. For example, in an R-2R resistor string structure, a mismatch exceeding 0.5‰ will result in an output error exceeding 1 LSB at 12-bit accuracy. Avoiding errors caused by resistor mismatch requires using high-value resistors, leading to a significant increase in chip area.

[0065] In addition, such as Figure 1 The schematic diagram of the timing structure of the PWM integrator circuit shown illustrates how, in implementing a digital-to-analog converter using a PWM integrator circuit, to achieve N-bit output accuracy, it uses 2... N If we take one clock cycle as a whole cycle T, and integrate the RC network over M clock cycles, the duty cycle of the integration over the whole cycle T is D = M / 2. N When the integration period is 1T, the integration is non-linear. In the diagram, Vout1 is the initial value of integration, and Vout1' is the new output value after integration. A single-cycle integration cannot precisely control the accuracy of the output voltage. Therefore, P overall cycles are needed as the total integration period. If the reference voltage is Vref, the final output voltage of the PWM integrator circuit is Vout1 = D·Vref. The overall integration time is P·T. If there is a minimum clock period, then when the achieved accuracy N is large, the overall clock period T is very high, therefore P·T is large, and the circuit switching speed is slow.

[0066] It is evident that existing digital-to-analog converters cannot simultaneously achieve both fast conversion speeds and high accuracy.

[0067] To enable a digital-to-analog converter to simultaneously achieve fast conversion speed and high accuracy, according to a first aspect of this disclosure, a digital-to-analog converter is provided. This digital-to-analog converter includes: a PWM integrator circuit and a resistor network type circuit;

[0068] Wherein, either the PWM integrator circuit or the resistor network circuit is used to implement the high-order part of the digital-to-analog conversion, and the other circuit is used to implement the low-order part of the digital-to-analog conversion;

[0069] The input terminal of the first circuit used to implement the high-order part of the digital-to-analog conversion is connected to the reference voltage;

[0070] The output terminal of the first circuit is connected to the input terminal of the second circuit used to implement the low-order part of the digital-to-analog conversion;

[0071] The output terminal of the second circuit outputs the output voltage of the digital-to-analog converter.

[0072] In the embodiments of this disclosure, a segmented processing approach is used to implement the digital-to-analog converter (D / A converter). The required accuracy of the entire D / A converter is divided into two parts—high-order bits and low-order bits. Different circuit structures are used for the high-order bits and low-order bits respectively. The high accuracy of the PWM integrator circuit and the resistor network circuit are combined to realize the overall D / A converter. This disclosure combines the advantages of high accuracy of the PWM integrator circuit and fast conversion speed of the resistor network circuit, thus achieving a balance between speed and accuracy, and realizing a high-precision D / A converter.

[0073] In the embodiments of this disclosure, the resistor network circuit is a structure that performs voltage and current division with a certain precision through a network formed by connecting several resistors in series and parallel.

[0074] like Figure 2 The diagram shows a digital-to-analog converter. In some embodiments of this disclosure, the PWM integrator circuit 201 is used to implement the high-order part of the digital-to-analog conversion.

[0075] The resistor network circuit 202 is used to implement the low-order part of the digital-to-analog conversion;

[0076] The input terminal of the PWM integrator circuit 201 is connected to the reference voltage Vref;

[0077] The output terminal of the PWM integrator circuit 201 is connected to the input terminal of the resistor network circuit 202;

[0078] The output terminal of the resistor network circuit 202 outputs the output voltage Vout of the digital-to-analog converter.

[0079] like Figure 3 The diagram shows a digital-to-analog converter. In some embodiments of this disclosure, the resistor network circuit 301 is used to implement the high-order part of the digital-to-analog conversion.

[0080] The PWM integrator circuit 302 is used to implement the low-order part of the digital-to-analog conversion;

[0081] The input terminal of the resistor network circuit 301 is connected to the reference voltage;

[0082] The output terminal of the resistor network circuit 301 is connected to the input terminal of the PWM integrator circuit 302;

[0083] The output terminal of the PWM integrator circuit 302 outputs the output voltage of the digital-to-analog converter.

[0084] In the embodiments of this disclosure, a resistor network circuit is used to implement high-bit-to-analog conversion, and a PWM integrator circuit is used to implement low-bit-to-analog conversion, compared to Figure 2 The PWM integrator circuit shown is used to implement high-bit-to-digital conversion, and the resistor network circuit is used to implement low-bit-to-digital conversion. Figure 3 The embodiment consumes more power.

[0085] Taking a resistor network circuit as an example of a thermometer-coded resistor string structure, if a high-β-bit digital-to-analog converter accuracy is achieved using a thermometer-coded resistor string structure, then a 2 β For the resistor, assuming a unit resistance of R, the static power consumption of the circuit is:

[0086]

[0087] If a PWM integrator circuit is used to achieve high α-bit accuracy, and a thermometer-coded resistor string structure is used to achieve low β-bit accuracy in a digital-to-analog converter, then the circuit's static power consumption is:

[0088]

[0089] Where n is the duration of the PWM high level in the total integral period, and m is the total period duration, i.e., the PWM control signal duty cycle D = n / m (D ≤ 1). When the output voltage is low, D is small, and the static power consumption is significantly reduced compared to resistor network circuits implementing high-order digital-to-analog converters. This approach balances ensuring chip lifespan with reducing the power consumption of the digital-to-analog converter system. Figure 2 The proposed solution has significant advantages.

[0090] In some embodiments of this disclosure, the resistor network type circuit includes any one of the following: a thermometer code resistor string structure, an R-2R resistor string structure, and a multi-stage cascaded resistor string voltage divider structure.

[0091] In the embodiments of this disclosure, the resistor network type circuit achieves voltage division through a resistor network and digital-to-analog conversion of high or low bits through a resistor array. Besides the aforementioned thermometer code resistor string structure, R-2R resistor string structure, and multi-stage cascaded resistor string voltage divider structure, the resistor network type circuit can also be other circuits that meet the requirements.

[0092] In some embodiments of this disclosure, the R-2R resistor string structure includes: N first resistors, N+1 second resistors, and N+1 single-pole double-throw switches;

[0093] In this circuit, the N first resistors are connected in series, and the first end of one of the N first resistors serves as the first input terminal of the resistor network circuit. The first ends of the remaining first resistors are coupled to the second end of the previous first resistor.

[0094] Each of the N+1 second resistors and a corresponding single-pole double-throw switch among the N+1 single-pole double-throw switches form a second resistor-switch group. The first end of each second resistor-switch group is coupled to the second end of the corresponding first resistor. The second end of each second resistor-switch group is connected to the second input end of the resistor network circuit. The third end of each second resistor-switch group is connected to the output end of the R-2R resistor string structure.

[0095] Where N is an integer greater than 1; the resistance value of the second resistor is twice the resistance value of the first resistor.

[0096] Figure 4 An exemplary circuit diagram of an R-2R resistor string structure is shown. The R-2R resistor string structure includes: N first resistors R1_1, ..., R1_N; N+1 second resistors R2_1, ..., R2_N-1, R2_N, R2_N+1; and N+1 single-pole double-throw switches S_1, ..., S_N-1, S_N, S_N+1. Each single-pole double-throw switch S_1, ..., S_N-1, S_N, S_N+1 includes two contacts and one control terminal.

[0097] N first resistors R1_1, ..., R1_N are connected in series. The first terminal of one of the N first resistors R1_1, ..., R1_N, R1_1, serves as the first input terminal Vin1 of the resistor network circuit. The first terminals of the remaining first resistors R1_N are coupled to the second terminal of the preceding first resistor. Each of the N+1 second resistors R2_1, ..., R2_N-1, R2_N, R2_N+1, together with a corresponding single-pole double-throw switch S_1, ..., S_N-1, S_N, S_N+1, forms a second resistor-switch group. For example, the first second resistor R2_1 and the first single-pole double-throw switch S_1 form the first second resistor-switch group. The Nth second resistor R2_N and the Nth single-pole double-throw switch S_N form the Nth second resistor-switch group. The first terminal of each second resistor-switch group is coupled to the second terminal of the corresponding first resistor. For example, the first terminal of the first second resistor-switch group (i.e., the first terminal (upper end) of the first second resistor R2_1) is coupled to the second terminal (right end) of the first first resistor R1_1. The first terminal of the Nth second resistor-switch group (i.e., the first terminal (upper end) of the second resistor R2_N) is coupled to the second terminal (right end) of the Nth first resistor R1_N. In particular, the first terminal of the (N+1)th second resistor-switch group is coupled to the second terminal (right end) of the Nth first resistor R1_N. The second terminal of each second resistor-switch group (one of the two contacts of a single-pole double-throw switch) is connected to the second input terminal Vin2 of the R-2R resistor string structure. The third terminal of each second resistor-switch group (the other of the two contacts of a single-pole double-throw switch) is connected to the output terminal of the R-2R resistor string structure.

[0098] In some embodiments of this disclosure, the resistance values ​​of the second resistors R2_1, ..., R2_N-1, R2_N, R2_N+1 are twice the resistance values ​​of the first resistors R1_1, ..., R1_N.

[0099] In some embodiments of this disclosure, the resistor network circuit includes a first input terminal and a second input terminal;

[0100] The PWM integrator circuit includes: two sub-PWM integrator circuits;

[0101] In this circuit, the output terminal of one of the sub-PWM integrator circuits is connected to the first input terminal of the resistor network circuit, and the output terminal of the other sub-PWM integrator circuit is connected to the second input terminal of the resistor network circuit.

[0102] like Figure 5The sub-PWM integrator circuit shown in some embodiments of this disclosure includes: a single-pole double-throw switch S, a third resistor R, a capacitor C, and an operational amplifier Amp.

[0103] Wherein, the first terminal of the single-pole double-throw switch S is connected to the first terminal of the third resistor R3, the second terminal of the single-pole double-throw switch S is connected to the reference voltage Vref, and the third terminal of the single-pole double-throw switch S is grounded;

[0104] The second terminal of the third resistor R3 is connected to the non-inverting input terminal of the operational amplifier Amp;

[0105] The first terminal of the capacitor C is connected to the non-inverting input terminal of the operational amplifier Amp, and the second terminal of the capacitor C is grounded.

[0106] The inverting input terminal of the operational amplifier Amp is connected to the output terminal of the operational amplifier Amp;

[0107] The output terminal of the operational amplifier Amp is the output terminal of the sub-PWM integrator circuit;

[0108] The conduction state of the single-pole double-throw switches in the two sub-PWM integrator circuits is controlled by different PWM control signals.

[0109] like Figure 6 The digital-to-analog converter shown in some embodiments of this disclosure includes... Figure 4 The R-2R resistor string structure shown, and two Figure 5 The diagram shows two sub-PWM integrator circuits, namely a first sub-PWM integrator circuit and a second sub-PWM integrator circuit. The first sub-PWM integrator circuit includes a single-pole double-throw switch S1, a third resistor R3, a capacitor C1, and an operational amplifier Amp1. The second sub-PWM integrator circuit includes a single-pole double-throw switch S2, a third resistor R4, a capacitor C2, and an operational amplifier Amp2. The output of the operational amplifier Amp1 in the first sub-PWM integrator circuit is connected to the first input of the R-2R resistor string structure. The output of the operational amplifier Amp2 in the second sub-PWM integrator circuit is connected to the second input of the R-2R resistor string structure. The output of the R-2R resistor string structure is connected to the inverting input of an operational amplifier Amp3 and the first terminal of a resistor R5. The second terminal of resistor R5 is connected to the output of operational amplifier Amp3, and the non-inverting input of operational amplifier Amp3 is connected to the output of operational amplifier Amp2 in the second sub-PWM integrator circuit. The resistance value of resistor R5 can be the same as that of the first resistor.

[0110] In this circuit, the conduction state of the single-pole double-throw switch of the first sub-PWM integrator circuit is controlled by PWM control signal 1, and the conduction state of the single-pole double-throw switch of the second sub-PWM integrator circuit is controlled by PWM control signal 2. Figure 7 A schematic diagram of the timing structure of the first sub-PWM integrator circuit and the second sub-PWM integrator circuit is shown.

[0111] In the embodiments of this disclosure, taking a digital-to-analog converter achieving (α+β)-bit precision as an example, a PWM integrator circuit is used for the high-order bits, and an R-2R resistor string structure is used for the low-order bits. These two circuits are cascaded to achieve the (α+β)-bit precision requirement. The duty cycle D of the PWM control signal 1 of the first sub-PWM integrator circuit is 2π / M for M integration clock cycles. α The duty cycle D' of the PWM control signal 2 of the second sub-PWM integrator circuit is obtained by the ratio of M-1 integration clock cycles. α The ratio of the total clock cycles is obtained. The capacitor charges when the PWM control signal voltage is high and discharges when the PWM control signal voltage is low. Therefore, the output voltage Vo1 of the first sub-PWM integrator circuit and the output voltage Vo1' of the second sub-PWM integrator circuit can be adjusted by controlling M. For the lower bits, it is in ΔV o1 =V o1 -V o1 Based on the existing structure, an R-2R resistor string structure is embedded. Based on the R-2R resistor string structure, the output current at the k-th R-2R node is... The total output current is:

[0112]

[0113] When k = α, its least significant bit precision is . It achieves the (α+β)-bit digital-to-analog converter accuracy design requirement. This hybrid digital-to-analog converter circuit structure, while achieving high accuracy, avoids the problem of slow PWM integrator circuits; for example, the 16 clock cycles used are significantly faster than 2... N In the case of (N>10) clock cycles, the equivalent speed is 2... N-4 At the same time, since the overall period T contains fewer clock cycles, its ripple is smaller than that of the large period integral, and can be filtered out by the bandwidth of the buffer itself, ensuring output stability.

[0114] In some embodiments of this disclosure, the PWM integrator circuit is configured as follows:

[0115] The conduction state of the single-pole double-throw switch in the first sub-PWM integrator circuit of the two sub-PWM integrator circuits is controlled by PWM control signal 1;

[0116] The conduction state of the single-pole double-throw switch in the second sub-PWM integrator circuit of the two sub-PWM integrator circuits is controlled by PWM control signal 2.

[0117] The first sub-PWM integrator circuit satisfies the following first equation:

[0118]

[0119] Wherein, Vo1 is the output voltage of the first sub-PWM integrator circuit; M is the number of integration cycles of the PWM control signal 1; the accuracy of the high-order bit-to-analog conversion is αbit; and Vref is the reference voltage.

[0120] The second sub-PWM integrator circuit satisfies the following second equation:

[0121]

[0122] Where Vo1′ is the output voltage of the second sub-PWM integrator circuit; M-1 is the number of integration cycles of the PWM control signal 2.

[0123] In the embodiments of this disclosure, based on the first formula, the desired output voltage Vo1 can be obtained by adjusting the integration period M of the PWM control signal. Given the desired accuracy αbit and output voltages Vo1 and Vo1′, based on the first formula, the desired accuracy αbit and the desired output voltages Vo1 and Vo1′ can be achieved by adjusting M.

[0124] In some embodiments of this disclosure, the R-2R resistor string structure is configured as follows:

[0125] The R-2R resistor string structure satisfies the following third equation:

[0126]

[0127] Wherein, R is the resistance value of the first resistor, A is the resistance mismatch of the R-2R resistor string structure, and the digital-to-analog conversion accuracy of the R-2R resistor string structure is βbit.

[0128] In the embodiments of this disclosure, given the resistance mismatch A of the R-2R resistor string structure, the maximum accuracy βbit achievable by the R-2R resistor string structure can be determined based on the third equation.

[0129] Based on the above embodiments, different precision segmentation strategies can be adopted for different circuit conditions of the hybrid digital-to-analog converter of this disclosure: when the resistor mismatch is large, the effective precision bits of the resistor network circuit may decrease, so the precision of the PWM integrator circuit needs to be increased accordingly (i.e., the clock period corresponding to T should be appropriately increased). When the circuit has high speed requirements, the precision of the PWM integrator circuit should be appropriately reduced, the step size of the overall period T should be reduced, and the precision of the resistor network structure should be increased to meet the precision requirements of the digital-to-analog converter.

[0130] Based on the above precision segmentation strategy, a digital-to-analog converter that better balances accuracy and speed can be configured, so that both the accuracy and speed of the digital-to-analog converter meet the target requirements.

[0131] Embodiments of this disclosure also provide a chip. This chip includes a digital-to-analog converter according to embodiments of this disclosure. This chip is, for example, a chip for performing high-precision digital-to-analog signal conversion.

[0132] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, an automated testing device and an industrial process control device.

[0133] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0134] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0135] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A digital-to-analog converter, comprising: A PWM integration circuit and a resistance network type circuit; Any one of the PWM integration circuit and the resistance network type circuit is used to implement a high bit part of digital-to-analog conversion, and the other is used to implement a low bit part of digital-to-analog conversion; An input end of the first circuit for implementing the high bit part of digital-to-analog conversion is connected with a reference voltage; An output end of the first circuit is connected with an input end of a second circuit for implementing the low bit part of digital-to-analog conversion; An output end of the second circuit outputs an output voltage of the digital-to-analog converter; The PWM integration circuit is used to implement a high bit part of digital-to-analog conversion; The resistance network type circuit is used to implement a low bit part of digital-to-analog conversion; An input end of the PWM integration circuit is connected with the reference voltage; An output end of the PWM integration circuit is connected with an input end of the resistance network type circuit; An output end of the resistance network type circuit outputs an output voltage of the digital-to-analog converter; The resistance network type circuit comprises a first input end and a second input end; The PWM integration circuit comprises two sub PWM integration circuits; An output end of one of the sub PWM integration circuits is connected with the first input end of the resistance network type circuit, and an output end of the other sub PWM integration circuit is connected with the second input end of the resistance network type circuit; The sub PWM integration circuit comprises a single-pole double-throw switch, a third resistor, a capacitor and an operational amplifier; A first end of the single-pole double-throw switch is connected with a first end of the third resistor, a second end of the single-pole double-throw switch is connected with the reference voltage, and a third end of the single-pole double-throw switch is connected with the ground; A second end of the third resistor is connected with a non-inverting input end of the operational amplifier; A first end of the capacitor is connected with the non-inverting input end of the operational amplifier, and a second end of the capacitor is connected with the ground; An inverting input end of the operational amplifier is connected with an output end of the operational amplifier; The output end of the operational amplifier is the output end of the sub PWM integration circuit; The on-off states of the single-pole double-throw switches of the two sub PWM integration circuits are controlled by different PWM control signals; The PWM integration circuit is configured as: The on-off state of the single-pole double-throw switch in the first sub PWM integration circuit of the two sub PWM integration circuits is controlled by PWM control signal 1; The on-off state of the single-pole double-throw switch in the second sub PWM integration circuit of the two sub PWM integration circuits is controlled by PWM control signal 2; The first sub PWM integration circuit satisfies the following first formula: wherein, is the output voltage of the first sub-PWM integration circuit; M is the number of integration periods of the PWM control signal 1, and the precision of the high-bit digital conversion is α bits, is the reference voltage; The second sub PWM integration circuit satisfies the following second formula: wherein, is the output voltage of the second sub-PWM integration circuit; M-1 is the number of integration periods of the PWM control signal 2.

2. The digital analog converter of claim 1, the resistive network type circuit comprising: Any one of a thermometer code resistance string structure, an R-2R resistance string structure and a multi-stage cascaded resistance string voltage division structure.

3. The digital-to-analog converter of claim 2, the R-2R resistor string structure comprising: N first resistors, N+1 second resistors and N+1 single-pole double-throw switches; The N first resistors are connected in series, a first end of one of the N first resistors is a first input end of the resistor network type circuit, and first ends of the other first resistors are coupled to second ends of the previous first resistors; Each of the N+1 second resistors and a corresponding one of the N+1 SPDT switches form a second resistor-switch group, a first end of each second resistor-switch group is coupled to a second end of a corresponding first resistor, a second end of each second resistor-switch group is connected to a second input end of the resistor network type circuit, and a third end of each second resistor-switch group is connected to an output end of the R-2R resistor string structure. N is an integer greater than 1; and a resistance value of the second resistor is twice a resistance value of the first resistor.

4. The digital-to-analog converter of claim 3, the R-2R resistor string structure is configured to: The R-2R resistor string structure satisfies a third formula: wherein R is the resistance value of the first resistor, A is a resistance mismatch of the R-2R resistor string structure, and a precision of a digital-to-analog conversion of the R-2R resistor string structure is βbit.

5. A chip comprising the digital-to-analog converter of any one of claims 1-4.

6. An electronic device comprising the chip of claim 5.

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