Uninstall server, uninstall control method and uninstall program

Abstract

The offloading server (1) has a code analysis unit (112), a processing mode creation unit (115) and a performance measurement unit (116), wherein the code analysis unit (112) analyzes whether a functional module that can be executed by an accelerator is included; the processing mode creation unit (115) creates a mode for uninstalling the functional module; and the performance measurement unit (116) deploys each mode for uninstalling the functional module in a verification device (14) to measure performance. When the performance measured by the performance measurement unit (116) is the expected performance, the processing mode creation unit (115) creates a mode for uninstalling the remaining loop statements except the functional module, and the performance measurement unit (116) deploys each mode in a verification environment to measure performance. When the performance measured by the performance measurement unit (116) is not the expected performance, the processing mode creation unit (115) creates a mode for uninstalling the loop statement, and the performance measurement unit (116) deploys each mode in a verification environment to measure performance.

Description

Technical Field

[0001] The present invention relates to an uninstallation server, an uninstallation control method and an uninstallation program, which uninstall a software processing program processed in a conventional CPU (Central Processing Unit) to perform processing at high speed in an environment where accelerators such as a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), and a many-core CPU are mixed together. Background Art

[0002] In recent years, Moore's Law, which states that the semiconductor integration of CPUs doubles every 1.5 years, is said to be slowing down. In this case, not only CPUs with fewer cores are used, but also the use of devices such as FPGAs and GPUs is increasing. For example, Microsoft is using FPGAs to improve the efficiency of search engines. Amazon provides FPGAs, GPUs, etc. as examples of clouds.

[0003] However, in order to properly use devices other than ordinary CPUs with fewer cores in the system, it is necessary to consider the settings of device characteristics and program creation. That is, knowledge of OpenMP (registered trademark) (Open Multi-Processing), OpenCL (registered trademark) (Open Computing Language), and CUDA (registered trademark) (Compute Unified Device Architecture) is required, so the skill barrier is high for most programmers. In addition, the records of OpenMP (registered trademark), OpenCL (registered trademark), and CUDA (registered trademark) will be omitted from now on.

[0004] It is expected that the number of systems that utilize accelerators such as GPUs, FPGAs, and many-core CPUs in addition to CPUs with fewer cores will increase in the future, but programmers face high technical barriers to maximize their use. Therefore, in order to eliminate such barriers and fully utilize accelerators other than CPUs with fewer cores, a platform is needed that allows programmers to adaptively convert and set software that describes processing logic to the environment (FPGA, GPU, many-core CPU, etc.) of the configuration target, so that actions suitable for the environment can be performed.

[0005] Therefore, the inventor proposed an environment adaptation software in non-patent document 1, the purpose of which is to automatically perform conversion, resource settings, etc. to enable the application to run with high performance, so that the GPU, FPGA, multi-core CPU, etc. existing in the configuration target environment can utilize the already written code.

[0006] As an element of environment adaptation software, the inventor proposed in non-patent documents 2, 3, and 4 a method of automatically offloading loop statements (loop statements) and functional modules of the source code to FPGA and GPU.

[0007] [Prior art literature]

[0008] [Non-patent literature]

[0009] Non-patent document 1: Y. Yamato, H. Noguchi, M. Kataoka and T. Isoda, "Proposal of Environment Adaptive Software," The 2nd International Conference on Control and Computer Vision (ICCCV 2019), pp. 102-108, Jeju, June 2019.

[0010] Non-patent literature 2: Y. Yamato, "Study of parallel processing area extraction and data transfer number reduction for automatic GPU offloading of IoT applications," Journal of Intelligent Information Systems, Springer, DOI: 10.1007 / s10844-019-00575-8, Aug. 2019.

[0011] Non-patent document 3: Y.Yamato, "Proposal of Automatic FPGA Offloading for Applications Loop Statements," The 7th Annual Conference on Engineering and Information Technology (ACEAIT 2020), pp.111-123, 2020.

[0012] Non-patent document 4: Y.Yamato, "Proposal of Automatic Offloading for FunctionBlocks of Applications," The 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE2020), pp.4-11, Mar.2020. Summary of the invention

[0013] [Technical problem to be solved by the invention]

[0014] In recent years, CUDA has become popular as a GPGPU (General Purpose GPU) environment for executing parallel computing capabilities of GPUs also in non-image processing. CUDA is an environment developed by NVIDIA for GPGPUs.

[0015] In addition, OpenCL has emerged as a specification for processing heterogeneous devices such as FPGAs, multi-core CPUs, and GPUs in the same way, and its development environment has also emerged. CUDA and OpenCL are programmed by explicitly copying and releasing memory data between cores such as FPGAs and hosts such as CPUs, and by extensions of the C language, so the programming is difficult.

[0016] In order to utilize heterogeneous devices more easily than CUDA and OpenCL, there is a technology that specifies a portion for executing parallel processing, etc. in an instruction line, and according to the instruction line, a compiler creates an execution file for a GPU, a multi-core CPU, etc. As a specification, there are OpenACC (registered trademark) (Open ACCelerators), OpenMP, etc., and as a compiler, there are PGI compiler, gcc, etc. In addition, regarding OpenACC (registered trademark), the description of (registered trademark) is omitted hereafter.

[0017] It is possible to offload to FPGA, GPU, and multi-core CPU by using technical specifications such as CUDA, OpenCL, OpenACC, and OpenMP. However, even if accelerator processing itself can be performed, there are technical problems in speeding up.

[0018] For example, there are compilers with automatic parallelization functions for multi-core CPUs, such as Intel compilers. When these compilers automatically parallelize, they extract the parallelizable parts from the loop statements in the code and parallelize them. However, due to the influence of memory processing, etc., even if only the parallelizable loop statements are parallelized, performance cannot be exerted in most cases. In addition, the loop statement here refers to for / while / do-while in C / C++ source code.

[0019] Specifically, when speeding up in FPGA, GPU, etc., OpenCL and CUDA technicians repeatedly tune or search for an appropriate parallel processing range and try the parallel processing range by using OpenACC compiler, etc. Therefore, it is difficult for programmers who lack technical skills to speed up applications by using FPGA, GPU, and multi-core CPU. In addition, when using automatic parallelization technology, etc., trial and error work such as parallel processing part search is required.

[0020] Currently, unloading of heterogeneous devices is mainly done manually. The inventors proposed the concept of environment adaptation software and studied automatic unloading. However, there is no idea of ​​unloading to a single GPU or a migration target environment that mixes various accelerators such as GPU, FPGA, and multi-core CPU.

[0021] Therefore, the technical problem of the present invention is to automatically improve the performance even if an environment in which a plurality of accelerators are mixed is a migration target in an offload server, an offload control method, and an offload program.

[0022] [Technical solutions for solving technical problems]

[0023] In order to solve the above technical problems, the unloading server of the present invention is characterized in that it has a code analysis unit, a processing mode making unit, a performance measurement unit and a control unit, wherein the code analysis unit analyzes whether the source code of the software program contains a functional module that can be executed by the accelerator; the processing mode making unit makes a mode for unloading the functional module to the accelerator; the performance measurement unit deploys each of the modes for unloading the functional module in a verification environment to measure the performance; the control unit is configured to, when the performance measured by the performance measurement unit is the expected performance, make a mode for unloading the remaining loop statements in the software program except the functional module through the processing mode making unit, deploy each of the modes in the verification environment to measure the performance through the performance measurement unit, and when the performance measured by the performance measurement unit is not the expected performance, make a mode for unloading the loop statements of the software program through the processing mode making unit, and deploy each of the modes in the verification environment to measure the performance through the performance measurement unit.

[0024] Other technical solutions will be described in the form of embodiments for implementing the invention.

[0025] [Effects of the invention]

[0026] According to the present invention, even if the migration target is an environment where multiple accelerators are mixed, high performance can be automatically improved. In addition, when the migration target has multiple accelerators on the same node, by simultaneously unloading the multiple accelerators, faster unloading can be achieved than when using a single accelerator. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a functional block diagram showing a configuration example of an offload server.

[0028] Figure 2 This is a hardware configuration diagram showing an example of a computer that realizes the function of an offload server.

[0029] Figure 3A 1 is a flowchart of a process for selecting a mode to be offloaded to an accelerator.

[0030] Figure 3B 1 is a flowchart of a process for selecting a mode to be offloaded to an accelerator.

[0031] Figure 3C 1 is a flowchart of a process for selecting a mode to be offloaded to an accelerator.

[0032] Figure 4A This is a flowchart of the process of offloading a functional module to a node.

[0033] Figure 4B It is a flowchart of the process of offloading the loop statement to a node.

[0034] Figure 5A This is a flowchart of a process for selecting a mode for offloading a functional module to an accelerator.

[0035] Figure 5B This is a flowchart of a process for selecting a mode for offloading a functional module to an accelerator.

[0036] Figure 6 This is a diagram showing the automatic uninstallation process of the uninstallation server.

[0037] Figure 7 This is a diagram showing the search state of the control unit using a simple genetic algorithm of the offload server.

[0038] Figure 8 Diagram showing the mapping of loop statements to gene sequences of a many-core CPU.

[0039] Fig.9AThis is a flowchart of the process of selecting a mode for offloading loop statements to a multi-core CPU.

[0040] Fig. 9B This is a flowchart of the process of selecting a mode for offloading loop statements to a multi-core CPU.

[0041] Fig.10 It is a diagram showing the mapping of loop statements to the gene sequence of the GPU.

[0042] Fig.11A This is a flowchart of the process of selecting a mode for offloading loop statements to the GPU.

[0043] Fig. 11B This is a flowchart of the process of selecting a mode for offloading loop statements to the GPU.

[0044] Fig. 12A This is a flowchart of the process of selecting a mode for offloading loop statements to the FPGA.

[0045] Fig. 12B This is a flowchart of the process of selecting a mode for offloading loop statements to the FPGA. DETAILED DESCRIPTION

[0046] Modes for carrying out the present invention will be described in detail below with reference to the drawings.

[0047] In order to concretize the concept of environment adaptation software, the inventor has proposed the automatic unloading of the program loop statement GPU, FPGA, and the automatic unloading of the program function module. Based on the research of these element technologies, the object is defined for the migration target environment, and the basic idea that is followed even when the object is diversified is described, and then the automatic unloading to each migration target environment and the automatic unloading method when the migration target environment is diversified are proposed.

[0048] Basic ideas for multiple target environments

[0049] In this embodiment, the target environments for the diversified migration include three types: GPU, FPGA, and multi-core CPU. GPU and FPGA have a long history as heterogeneous hardware different from CPU, and there are many examples of speed-up based on manual offloading using CUDA and OpenCL, and the market is also large. In addition, regarding multi-core CPUs, CPUs equipped with more than 16 cores have been launched in recent years at low prices ranging from thousands of dollars, and there have been examples of speed-up by parallelization using technical specifications such as OpenMP and manual tuning.

[0050] When the migration target environment is not limited to the CPU, in order to automatically and quickly offload, the performance is measured on a real machine in the verification environment, and a method of gradually discovering a high-speed offloading pattern is adopted in combination with methods such as evolutionary computing.

[0051] This is the same as the GPU offloading proposed by the inventor so far. The reason is that performance is considered to vary greatly not only by the code structure but also by the actual processing content such as the specifications of the hardware being processed, the data size, the number of loops, etc., so it is difficult to predict statically and dynamic measurement is required. In the market, there are automatic parallelization compilers that discover loop statements and parallelize them at the compilation stage, but if the performance is measured only by parallelizing the parallelizable loop statements, it often becomes slow, so it is considered necessary to measure the performance.

[0052] In addition, the objects to be offloaded are the loop statements and functional modules of the program. This is the same as the GPU and FPGA offloading studied so far. Regarding loop statements, since most of the processing time of the program is consumed in the loop, loop statements are considered as the target of offloading.

[0053] On the other hand, for functional modules, when making specific processing faster, algorithms suitable for the processing content and processing hardware are often used, so compared with the parallel processing of each loop statement, it is sometimes possible to achieve a significant speed-up. In this embodiment, frequently used functional modules such as matrix accumulation and Fourier transform are replaced with processing (IP core, CUDA library, etc.) installed by algorithms corresponding to accelerators such as multi-core CPUs, FPGAs, and GPUs, thereby achieving speed-up.

[0054] Figure 1 2 is a functional block diagram showing a configuration example of the off-load server 1 .

[0055] The offload server 1 is a device that automatically offloads specific processing of an application to an accelerator such as a GPU, FPGA, or a multi-core CPU.

[0056] like Figure 1 As described above, the offload server 1 is configured to include a control unit 11, an input / output unit 12, a storage unit 13, and a verification device 14 (accelerator verification apparatus).

[0057] The input / output unit 12 is composed of a communication interface 950 (see Figure 2 ) and input / output interface 960 (refer to Figure 2 ) is composed of, wherein the communication interface is used to send and receive information between various devices belonging to the cloud layer 2, the network layer 3 and the device layer 4; the input and output interface is used to send and receive information between input devices such as touch screens and keyboards, and output devices such as monitors.

[0058] The storage unit 13 is composed of a hard disk, a flash memory, a RAM (Random Access Memory), etc. In the storage unit 13, a test case database 131 and a code pattern database 133 are stored, and a program (uninstaller) for executing each function of the control unit 11, information required for the processing of the control unit 11, such as an intermediate language file 132, etc. are temporarily stored.

[0059] The test case database 131 stores data of test items corresponding to the verification target software. For example, if it is a database system such as MySQL, it is a transaction processing test such as TPC-C. The code pattern database 133 stores replaceable accelerator libraries or accelerator IP cores corresponding to program library names.

[0060] The verification device 14 includes accelerators such as GPU, FPGA, and multi-core CPU, which serve as the verification environment of the environment adaptation software system.

[0061] The control unit 11 is an automatic uninstallation function unit that is responsible for controlling the entire uninstallation server 1. The control unit 11 can be configured to automatically uninstall the server 1. Figure 2 This is achieved by the CPU 910 executing a program (uninstall program) stored in the storage unit 13.

[0062] The control unit 11 includes a code specifying unit 111 , a code analyzing unit 112 , a processing specifying unit 114 , a processing pattern creating unit 115 , a performance measuring unit 116 , an executable file creating unit 117 , a formal environment configuring unit 118 , a performance measuring test extracting and executing unit 119 , and a user providing unit 120 .

[0063] 《Code Designation Department 111》

[0064] The code specifying unit 111 specifies the input source code. Specifically, the code specifying unit 111 passes the source code described in the received file to the code analyzing unit 112.

[0065] 《Code Analysis Department 112》

[0066] The code analysis unit 112 analyzes the source code of the software program to grasp loop statements such as for / do-while / while, FFT library, matrix operation, random number generation, etc. These loop statements and functional modules can be executed by the accelerator.

[0067] <<Processing Designation Department 114>>

[0068] The process designation unit 114 replaces each functional module with a process to be offloaded to the accelerator and compiles each loop statement by designating a parallel process designation statement to be offloaded to the accelerator. The process designation unit 114 includes an offload range extraction unit 114a and an intermediate language file output unit 114b.

[0069] The offload range extraction unit 114a determines the processing that can be offloaded to the multi-core CPU, GPU, and FPGA, such as loop statements such as for / do-while / while, FFT, matrix operation, random number generation, and other functional modules, and extracts the offload range. The intermediate language file output unit 114b outputs the extracted intermediate language file 132 of the offloadable processing. The intermediate language extraction is not completed once, and the intermediate language extraction is repeatedly performed in order to search for a suitable offload area and to optimize the execution through trial.

[0070] 《Processing Model Production Department 115》

[0071] The processing pattern creation unit 115 creates a pattern for offloading functional modules and loop statements to the accelerator based on the extracted offload range.

[0072] When the GPU is used as an accelerator for loop statements, the processing mode creation unit 115 creates a parallel processing mode, which means that loop statements (loop statements) with compilation errors are excluded from the unloading objects, and whether to parallel process loop statements without compilation errors is specified.

[0073] 《Performance Measurement Department 116》

[0074] The performance measurement unit 116 compiles the source code of the processing pattern, places it in the verification device 14, and executes the performance measurement process when offloading to the accelerator.

[0075] The performance measurement unit 116 includes a binary file configuration unit 116a. The binary file configuration unit 116a deploys (configures) an executable file derived from an intermediate language in the verification device 14 including a multi-core CPU, a GPU, and an FPGA.

[0076] The performance measurement unit 116 executes the deployed binary file, measures the performance during uninstallation, and returns the performance measurement result to the processing pattern creation unit 115. In this case, the processing pattern creation unit 115 creates another uninstallation pattern. The performance measurement unit 116 tries to measure the performance of the created another uninstallation pattern.

[0077] 《Executable File Production Department 117》

[0078] The executable file creation unit 117 selects an offload mode with the highest processing performance from a plurality of offload modes based on the performance measurement results repeated a predetermined number of times, and compiles the offload mode with the highest processing performance to create an executable file.

[0079] 《Formal Environment Configuration Department 118》

[0080] The production environment configuration unit 118 configures the created executable file in the production environment for users ("deployment of the final binary file to the production environment"). The production environment configuration unit 118 determines the pattern that specifies the final uninstallation area and deploys it in the production environment for users.

[0081] <<Performance measurement test extraction execution unit 119>>

[0082] After the executable file is deployed, the performance measurement test extraction and execution unit 119 extracts the performance test items from the test case database 131 and executes the performance test ("deployment of the final binary file to the production environment").

[0083] After the executable file is arranged, in order to show the performance to the user, the performance measurement test extraction and execution unit 119 extracts the performance test items from the test case database 131 and automatically executes the extracted performance test.

[0084] <<User Provisioning Unit 120>>

[0085] The user providing unit 120 presents the user with information such as price and performance based on the performance test results (“Provision of information such as price and performance to the user”). The test case database 131 stores data of test items corresponding to the verification target software. The user providing unit 120 presents the user with data such as performance obtained by executing the test items stored in the test case database 131, and data such as price information of resources (virtual machines, GPUs, etc.) configuring the user software. The user determines the start of paid use of the service based on the presented information such as price and performance.

[0086] [Application of Genetic Algorithm]

[0087] The offload server 1 can use a genetic algorithm for offload optimization. The configuration of the offload server 1 when using a genetic algorithm is as follows.

[0088] That is, the processing designation unit 114 uses the number of loop statements as the gene length according to the genetic algorithm. The processing pattern creation unit 115 sets the case of performing accelerator processing as either 1 or 0, and sets the case of not performing accelerator processing as the other 0 or 1, and maps whether accelerator processing is possible to the gene pattern.

[0089] When a genetic algorithm is used, the processing pattern creation unit 115 prepares a gene pattern of a specified number of individuals in which each value of a gene is randomly created to be 1 or 0. The performance measurement unit 116 compiles a source code specifying a parallel processing specification statement in the accelerator for each individual, and configures it in the verification device 14. The performance measurement unit 116 executes a performance measurement process in the verification device 14.

[0090] Here, when a genetic algorithm is used and genes of the same parallel processing pattern as before are generated in an intermediate generation, the performance measurement unit 116 uses the same value as the performance measurement value without compiling source code that conforms to the parallel processing pattern and performing performance measurement.

[0091] Furthermore, the performance measurement unit 116 treats source code in which a compilation error occurs and source code for which performance measurement has not been completed within a predetermined time as timed out, and sets the performance measurement value thereof to a predetermined time (long time).

[0092] The executable file creation unit 117 measures the performance of all individuals and evaluates them in a manner that the individuals with shorter processing time have higher fitness. The executable file creation unit 117 selects individuals with fitness higher than a specified value (for example, the upper n% of the total number, or the upper m of the total number: n, m are natural numbers) from all individuals as high-performance individuals, and performs crossover and sudden mutation processing on the selected individuals to create individuals of the next generation. After the processing of the specified number of generations is completed, the executable file creation unit 117 selects the parallel processing mode with the highest performance as the solution.

[0093] FIG. 3 is a diagram showing a hardware configuration of an example of a computer that realizes the function of the offload server.

[0094] The computer 900 includes a CPU 910 , a RAM 920 , a ROM 930 , an HDD 940 , a communication interface 950 , an input / output interface 960 , and a media interface 970 .

[0095] The CPU 910 operates based on a program stored in the ROM 930 or the HDD 940 to control each unit. The ROM 930 stores a boot program executed by the CPU 910 when the computer 900 is activated, a program depending on the hardware of the computer 900, and the like.

[0096] The HDD 940 stores programs executed by the CPU 910 and data used by the programs, etc. The communication interface 950 receives data from other devices via the communication network 80 and transmits the data to the CPU 910 , and transmits data generated by the CPU 910 to other devices via the communication network 80 .

[0097] The CPU 910 controls output devices such as a display and a printer and input devices such as a keyboard and a mouse via the input / output interface 960. The CPU 910 acquires data from the input device via the input / output interface 960. In addition, the CPU 910 outputs generated data to the output device via the input / output interface 960.

[0098] The media interface 970 reads a program or data stored in the recording medium 980, and provides the program or data to the CPU 910 through the RAM 920. The CPU 910 loads the program from the recording medium 980 to the RAM 920 through the media interface 970, and executes the loaded program. The recording medium 980 is, for example, an optical recording medium such as a DVD (Digital Versatile Disc), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a tape medium, a magnetic recording medium, or a semiconductor memory.

[0099] For example, when the computer 900 functions as the off-load server 1 according to the present embodiment, the CPU 910 of the computer 900 implements the functions of each unit of the off-load server 1 by executing the program loaded on the RAM 920. In addition, the HDD 940 stores data in each unit of the off-load server 1. The CPU 910 of the computer 900 reads and executes these programs from the recording medium 980, but as another example, these programs may be obtained from other devices via the communication network 80.

[0100] Figure 3A , Figure 3B and Figure 3C 1 is a flowchart of a process for selecting a mode to be offloaded to an accelerator.

[0101] The offloading server 1 studies automatic offloading for three migration target environments of GPU, FPGA, and multi-core CPU through two methods: functional module and loop statement.

[0102] When the C / C++ source code is input (S200), the control unit 11 executes a series of uninstall mode selection processes. The control unit 11 calls Figure 5A and Figure 5B In the selection process in , the offloading of the functional module to the multi-core CPU is checked (S201), and it is determined whether the expected performance is obtained (S202). If the expected performance is obtained (yes), the control unit 11 selects the highest performance mode from all measurements (S208) and ends the processing of this figure. If the expected performance is not obtained (no), the control unit 11 proceeds to step S203.

[0103] In step S203, the control unit 11 calls Figure 5A and Figure 5B , and checks the unloading of the functional module to the GPU. Then, the control unit 11 determines whether the desired performance is obtained (S204). If the desired performance is obtained (yes), the control unit 11 selects the highest performance mode from all measurements (S208) and ends the processing of this figure. If the desired performance is not obtained (no), the control unit 11 proceeds to step S205.

[0104] In step S205, the control unit 11 calls Figure 5A and Figure 5B The control unit 11 then determines whether the desired performance is obtained (S206). If the desired performance is obtained (Yes), the control unit 11 selects the highest performance mode from all measurements (S208), and ends the processing of this figure. If the desired performance is not obtained (No), the control unit 11 removes the portion of the function module that has been unloaded from the code, and the processing proceeds to Figure 3B Step S209 in .

[0105] Through the processing of steps S201 to S208, even if the environment where multiple accelerators are mixed is the migration target, the functional module can be automatically made high-performance. In addition, the control unit 11 can efficiently search for a pattern that can be accelerated by trying in the order of multi-core CPU, GPU, and FPGA.

[0106] In step S209, the control unit 11 calls Fig.9A and Fig. 9B The selection process in checks the unloading of the loop statement to the multi-core CPU. Then, the control unit 11 determines whether the desired performance is obtained (S210). If the desired performance is obtained (yes), the control unit 11 selects the highest performance mode from all measurements (S208) and ends the processing of this figure. If the desired performance is not obtained (no), the control unit 11 proceeds to step S211.

[0107] In step S211, the control unit 11 calls Fig.11A and Fig. 11B The selection process in the loop statement is checked for unloading to the GPU. Then, the control unit 11 determines whether the desired performance is obtained (S212). If the desired performance is obtained (Yes), the control unit 11 selects the highest performance mode from all measurements (S208) and ends the processing of the figure. If the desired performance is not obtained (No), the control unit 11 proceeds to step S213.

[0108] In step S213, the control unit 11 calls Fig. 12A and Fig. 12BThe control unit 11 then performs selection processing to check the unloading of the loop statement to the FPGA. Then, the control unit 11 determines whether the desired performance is obtained (S214). If the desired performance is obtained (Yes), the control unit 11 selects the highest performance mode from all measurements (S208) and ends the processing of this figure. If the desired performance is not obtained (No), the control unit 11 selects the highest performance mode from the 6 verifications for each migration target (S215).

[0109] Through the processing of these steps S209 to S215, even if the environment where multiple accelerators are mixed is the migration target, the loop statement can be automatically made high-performance. In addition, the control unit 11 can efficiently search for a high-speed mode by trialing in the order of the multi-core CPU, GPU, and FPGA. The control unit trials the loop statement as an offload target to the accelerator after trialing the functional module, thereby efficiently searching for a high-speed mode.

[0110] Then, the control unit 11 determines whether there are a plurality of candidates for offloading to one node ( S216 ).

[0111] If there are no candidates for multiple offloading to one node (No), the control unit 11 ends the processing in the figure. If there are candidates for multiple offloading to one node (Yes), the control unit 11 proceeds to Figure 3C Step S217.

[0112] exist Figure 3C In step S217, the control unit 11 determines whether there is a candidate for uninstalling multiple functional modules. If there is a candidate for uninstalling multiple functional modules (yes), the control unit 11 proceeds to step S218. If there is no candidate for uninstalling multiple functional modules (no), the control unit 11 proceeds to step S223.

[0113] In step S218, the control unit 11 creates a combination pattern of uninstalling a plurality of functional modules. The control unit 11 measures the performance of the combination pattern (S219). Then, the control unit 11 determines whether the speed can be increased by the combination of uninstalling the functional modules (S220).

[0114] In step S220, if uninstallation of the combined functional modules is faster, the control unit 11 removes the combined functional modules from the source code (S221), and proceeds to the process of step S223. If uninstallation of the functional modules without combining them is faster, the control unit 11 removes one functional module that can achieve faster performance from the uninstallation targets of the source code (S222), and proceeds to the process of step S223.

[0115] In step S223, the control unit 11 determines whether there is a loop statement unloading mode that can be accelerated, and determines whether it is a single accelerator or multiple accelerators. If there is no loop statement unloading mode that can be accelerated, the process proceeds to step S227, and when the control unit 11 selects the highest performance mode from all measurements, the selection process ends. Here, in the example where loop statement unloading mode B unloads 30 for statements to the GPU and loop statement unloading mode C unloads 50 for statements to the multi-core CPU, the case where only loop statement unloading mode B can be accelerated is recorded as a single accelerator, and the case where both loop statement unloading mode B and loop statement unloading mode C can be accelerated is recorded as multiple accelerators.

[0116] If the result of the determination in step S223 is the unloading mode of the loop statement of the single accelerator that can be accelerated, the control unit 11 creates a combination of unloading of the removed functional module and unloading of the loop statement of the single accelerator (S224). Then, the control unit 11 measures the performance of the combined mode (S226), and when the mode with the highest performance is selected from all the measurements (S227), the selection process ends.

[0117] If the result of the determination in step S223 is that the loop statement offloading mode of multiple accelerators can be accelerated, the control unit 11 creates a combination of the offloading of the removed functional modules and the offloading of the loop statements of multiple accelerators (S225). For example, in the case where the function module offloading A to the GPU, the loop statement offloading mode B to the GPU, and the loop statement offloading mode C to the multi-core CPU can be accelerated, four combinations of A+B+C, A+B, A+C, and B+C can be considered.

[0118] Then, the control unit 11 measures the performance of the combined patterns (S226), and when selecting the pattern with the highest performance from all the measurements (S227), the selection process ends.

[0119] Through the processing of these steps S217 to S227, when the migration destination has multiple types of accelerators at the same node, by simultaneously unloading to the multiple types of accelerators, it is possible to achieve faster unloading than when using a single accelerator.

[0120] 《Verification sequence for uninstallation trial》

[0121] Study on automatic unloading on various moving targets.

[0122] Even if the processing is the same, the performance will vary significantly depending on the specifications of the processing hardware and the processing content (data size, number of loops, etc.), so it is necessary to measure it on a real machine in the verification environment. Since there are two methods of offloading for the three target environments of migration, GPU, FPGA, and multi-core CPU, namely loop statements and functional modules, a total of 6 offloading methods can be considered, namely 3×2.

[0123] First, when comparing the unloading of the functional module and the unloading of the loop statement, the unloading of the functional module according to the processing content including the algorithm can be accelerated.

[0124] Next, when virtualization is not performed, among GPU, FPGA and multi-core CPU, the central price range of multi-core CPU is higher than that of GPU, and FPGA is higher than them. In addition, the verification time of one mode of multi-core CPU and GPU is roughly the same, and the verification time of one mode of FPGA is longer than that of multi-core CPU and GPU. The current situation is that the circuit setting of FPGA takes many hours, and performance measurement takes time.

[0125] Considering these current situations, the following solution is proposed: unloading the functional modules for many-core CPUs, unloading the functional modules for GPUs, unloading the functional modules for FPGAs, unloading the loop statements for many-core CPUs, unloading the loop statements for GPUs, and unloading the loop statements for FPGAs is used as the verification sequence through six unloadings. Unloading is tried in this order to search for a high-performance mode.

[0126] The first three uninstalls and the second three uninstalls can change the target code. Specifically, if the function module can be uninstalled in the first three uninstalls, the third three loop statement uninstalls are to try out the code without the uninstallable function module.

[0127] In addition, in the uninstallation trial, the user can specify the target performance and price. If a sufficiently high-speed and low-price uninstallation mode is found in the front side of the 6 trials within the user-specified range, the subsequent trials can be omitted. This is because compared with loop statement uninstallation, the objects that can be uninstalled in function module uninstallation are fewer, but when they can be uninstalled, higher speed can be achieved.

[0128] In addition, when automatically uninstalling, it is preferred to search for a mode that is as cheap as possible and high-speed in a short time. Therefore, the FPGA that takes time to verify is placed last, and if a mode that fully meets the user's requirements is found in the previous stage, the uninstallation mode for FPGA is not verified.

[0129] Although there is no big difference between GPU and multi-core CPU in terms of price and verification time, the difference between multi-core CPU and ordinary CPU is smaller than that between GPU, which has different memory space and different device itself. Therefore, the verification order is first for multi-core CPU, and if a mode that fully meets the user's requirements is found in multi-core CPU, the offload mode for GPU is not verified.

[0130] Since the CPU and GPU are different devices, even if the offloading is performed correctly, the calculation results may be different due to rounding errors and the like.

[0131] 《Making a high-performance model based on a combination of multiple offloads》

[0132] Trial and error is also required when creating a solution model. In the case that only one of the six uninstall trials has a faster than normal CPU, the executable file of the model can be deployed in a commercial environment.

[0133] In addition, when configuring the executable file, in addition to selecting the highest performance mode, you can also select a cost-effective mode based on the price of the device being used. In addition, when there are multiple modes that can be accelerated during verification, it is necessary to study the mode that becomes the solution.

[0134] When unloading, although the GPU, FPGA, and multi-core CPU of the same node are easy to speed up, when unloading at other nodes, technical specifications such as MPI are required. In addition, it is difficult to speed up due to communication overhead. In addition, the server generally has a structure that includes multi-core CPUs and GPUs, or a structure that includes multi-core CPUs and FPGAs, but rarely has a structure that includes multi-core CPUs, GPUs, and FPGAs.

[0135] The initial condition for being able to speed up multiple accelerators is that they can be offloaded on the same node. The multi-core CPU and GPU on the same node can be candidates, but GPUs and FPGAs on different nodes cannot be candidates.

[0136] First, the function module uninstallation is studied. In the function module uninstallation, the following rules are adopted.

[0137] (a) When the same functional module can be offloaded to multiple accelerators, select the offload target that has a higher performance improvement effect.

[0138] (b) When different functional modules can be offloaded to different types of accelerators but cannot be offloaded to the same node, a functional module that has a greater effect of improving performance is selected as an offload target.

[0139] (c) When different functional modules can be offloaded to different types of accelerators and can be offloaded to the same node, these functional modules are designated as offload targets.

[0140] As an example of rule (a), consider the case where an FFT process that takes 10 seconds in a single-core CPU takes 2 seconds when offloaded to a GPU, 1 second when offloaded to an FPGA, and 5 seconds when offloaded to a multi-core CPU. In this case, an FPGA can be selected as the accelerator for the offload target.

[0141] As an example of rule (b), consider the case where random number processing that takes 20 seconds in a single-core CPU takes 2 seconds when it is offloaded to the GPU, FFT processing that takes 100 seconds in a single-core CPU takes 1 second when it is offloaded to the FPGA, and matrix calculation that takes 50 seconds in a single-core CPU takes 10 seconds when it is offloaded to the multi-core CPU. In this case, the mode that offloads the most effective FFT processing to the FPGA can be selected.

[0142] Regarding rule (c), different functional modules are offloaded to multiple accelerators on the same node to verify the performance, and the case that is faster than the single accelerator is taken as the solution.

[0143] As an example of rule (c), consider the case where random number processing that takes 20 seconds in a single-core CPU takes 20 seconds when it is offloaded to the GPU, FFT processing that takes 10 seconds in a single-core CPU takes 1 second when it is offloaded to the FPGA, and matrix calculation that takes 50 seconds in a single-core CPU takes 10 seconds when it is offloaded to the many-core CPU. Furthermore, suppose there is a node equipped with both a GPU and a many-core CPU. In this case, on the same node, the random number processing can be selected to be offloaded to the GPU, and the matrix calculation can be selected to be offloaded to the many-core CPU.

[0144] When offloading to multiple accelerators on the same node, it is not necessarily possible to reliably achieve high speed by offloading to multiple accelerators at the same time. Therefore, the offloading server 1 simultaneously offloads to multiple accelerators to verify the performance and confirms that it is faster than offloading to a single accelerator.

[0145] According to this, in an environment where multiple accelerators are mixed, it is possible to search for a pattern that can efficiently accelerate a functional module.

[0146] In addition, a frequently used process, that is, a functional module, can be uninstalled with a high priority. In this case, in the six uninstall verifications previously performed, a sample test focusing on a high-priority process can be adopted in the sample test for performance measurement.

[0147] Figure 4A This is a flowchart of the process of offloading a functional module to a node.

[0148] The control unit 11 of the offloading server 1 determines whether the same functional module can be offloaded to multiple accelerators (S50). If the same functional module can be offloaded to multiple accelerators (yes), the control unit 11 selects an offloading target with a higher performance effect (S51), and ends. Figure 4A If the same functional module cannot be offloaded to a plurality of accelerators (No), the processing of the control unit 11 proceeds to step S52.

[0149] In step S52, the control unit 11 determines whether different functional modules can be unloaded to different types of accelerators. If different functional modules can be unloaded to different types of accelerators (yes), the control unit 11 takes these functional modules as unloading objects and ends. Figure 4A processing.

[0150] If it is not possible to offload different functional modules to different types of accelerators (No), the control unit 11 selects a functional module with a higher performance improvement effect as an offload target (S54), and ends the process. Figure 4A processing.

[0151] Next, we will study the unloading of the loop statement.

[0152] When the function module can be uninstalled, the loop statement is uninstalled for the code other than the function module part that can be uninstalled. When the speed improvement in the loop statement uninstallation is the uninstallation of the uninstallation target and other nodes in the function module uninstallation, and the effect of high performance improvement is small, the loop statement is not uninstalled.

[0153] For example, when an FFT process that takes 100 seconds to be offloaded to a single-core CPU and can be processed in 1 second in an FPGA, even if it is known that the remaining loop statements can be accelerated from 20 seconds to 5 seconds by offloading to the GPU, the high-performance effect is small and therefore the process will not be offloaded to the GPUs of other nodes.

[0154] The following rules apply to the unloading of loop statements.

[0155] (d) When the same loop statement can be offloaded to multiple accelerators, select the offload target with higher performance.

[0156] (e) When different loop statements can be offloaded to different types of accelerators but cannot be offloaded to the same node, a group of loop statements that have a higher performance improvement effect is selected as an offload target.

[0157] (f) When different loop statements can be offloaded to different types of accelerators and can be offloaded to the same node, loop statements with high performance improvement effect are offloaded first, and the remaining loop statement groups that have not been offloaded are offloaded to offload targets with low performance improvement effect.

[0158] As an example of rule (d), consider the case where the loop statement ABCDE that takes 20 seconds in a single-core CPU takes 2 seconds to be offloaded to a GPU, 1 second to be offloaded to an FPGA, and 5 seconds to be offloaded to a multi-core CPU. In this case, the mode of offloading the loop statement ABCDE to the FPGA can be selected.

[0159] As an example of rule (e), consider the case where the loop statement of ABC, which takes 50 seconds in a single-core CPU, takes 2 seconds to be offloaded to the GPU, the loop statement of BCD, which takes 100 seconds in a single-core CPU, takes 1 second to be offloaded to the FPGA, and the loop statement of CDE, which takes 50 seconds in a single-core CPU, takes 10 seconds to be offloaded to the multi-core CPU. In this case, the mode of offloading the loop statement of BCD to the FPGA can be selected.

[0160] Regarding rule (f), different loops are offloaded to multiple accelerators on the same node to verify the performance. When it is faster than the single node, this mode is selected as the solution. However, multiple loop statements defined in the same file are restricted so that they cannot be processed separately by other accelerators. This is to avoid the increase in complexity caused by the accelerator separating multiple loop statements on the same file with a deep correlation.

[0161] As an example of rule (f), assume that when the loop statement ABC that takes 50 seconds in a single-core CPU is offloaded to the GPU, it takes 2 seconds, when the loop statement BCD that takes 10 seconds in a single-core CPU is offloaded to the FPGA, it takes 1 second, when the loop statement CDE that takes 50 seconds in a single-core CPU is offloaded to the multi-core CPU, it takes 10 seconds, and there is a node equipped with both a GPU and a multi-core CPU. In this case, on the same node, the loop statement ABC is offloaded to the GPU, and the loop statement DE is offloaded to the multi-core CPU.

[0162] Figure 4B It is a flowchart of the process of offloading the loop statement to a node.

[0163] The control unit 11 of the offload server 1 determines whether the same loop statement can be offloaded to multiple accelerators (S60). If the same loop statement can be offloaded to multiple accelerators (yes), the control unit 11 selects an offload target with a higher performance effect (S61), and ends. Figure 4B If the same loop statement cannot be offloaded to multiple accelerators (No), the control unit 11 proceeds to step S62.

[0164] In step S62, the control unit 11 determines whether different loop statements can be unloaded to different types of accelerators. If different loop statements can be unloaded to different types of accelerators (yes), the control unit 11 takes these loop statements as unload targets and ends. Figure 4B processing.

[0165] If it is not possible to offload different loop statements to different types of accelerators (No), the control unit 11 selects a loop statement with a higher performance improvement effect as an offload target (S64), and ends the process. Figure 4B processing.

[0166] When offloading to multiple accelerators on the same node, it is not always possible to reliably achieve higher speeds. Therefore, after actual offloading, performance verification was performed to confirm that it was faster than offloading to a single accelerator.

[0167] Based on this, in an environment where multiple accelerators are mixed, it is possible to search for a pattern that can efficiently speed up loop statements.

[0168] Thus, among the six performance measurements, the highest performance mode is created based on the mode that can be accelerated. For the same node, although it is also possible to offload to multiple accelerators, when combining multiple offload modes, the highest performance mode is created by using performance measurements to confirm whether the combination can achieve higher performance than the single mode, so multiple measurements are required.

[0169] Figure 5A and Figure 5B This is a flowchart of a selection process for a mode of offloading a functional module to an accelerator. This selection process uses the method of Non-Patent Document 4.

[0170] First, the code analysis unit 112 performs uninstall analysis of the C / C++ source code (S30). Specifically, the code analysis unit 112 uses a syntax analysis tool such as Clang to call libraries included in the code and analyze functional processing.

[0171] The offload range extraction unit 114a detects the external library call of the source code (S31), and obtains an accelerator library or an accelerator IP core that can be replaced using the library name as a key from the code pattern database 133 (S32). Here, the accelerator refers to any one of a multi-core CPU, a GPU, and an FPGA. Specifically, the offload range extraction unit 114a uses the called library as a key to obtain an executable file, OpenCL, etc. that can be accelerated from the records registered in the code pattern database 133.

[0172] Here, the offload range extraction unit 114a compares the external library calls it has grasped with the code pattern database 133 using the called library name as a key, thereby obtaining a replaceable accelerator library or accelerator IP core. Here, the accelerator library refers to an executable file for a multi-core CPU or GPU. The accelerator IP core refers to OpenCL, etc.

[0173] In addition, for functional modules, the search for whether there are high-speed libraries and IP cores is performed by using similarity detection tools in addition to the consistency of library names. Similarity detection tools are tools used in software engineering such as Deckard to detect copied code or code that has been changed after copying. Similarity detection tools observe abstract syntaxtree similarity, etc., to determine code similarity, and when the CPU is used for calculation, it can detect situations where the same processing is recorded, or other people's reference code is copied and changed.

[0174] The processing mode making unit 115 replaces the processing description of the replacement source of the source code with the processing description of the library for the multi-core CPU, GPU or the IP core for the FPGA according to the accelerator of the replacement target (S33). In addition, the processing mode making unit 115 unloads the processing description of the replaced accelerator library or accelerator IP core to the accelerator as the functional module of the unloading object (S34). At this time, since it is unknown whether the processing that can be unloaded can actually achieve high speed or whether the cost effect is sufficient, the unloading and non-unloading are tried through the performance measurement in the verification environment, thereby automatically extracting a faster unloading mode.

[0175] The processing pattern creation unit 115 describes an interface process for calling the accelerator library or the accelerator IP core (S35). The interface process is, for example, the OpenCL API for the FPGA.

[0176] Next, the executable file creation unit 117 compiles the created pattern (S36). The performance measurement unit 116 performs performance measurement on the created pattern in the verification environment (S37). This is the first performance measurement.

[0177] After the first performance measurement, the executable file creation unit 117 creates a combination pattern of the patterns that can be accelerated in the first measurement (S38), and compiles the created combination pattern (S39). Then, the performance measurement unit 116 performs performance measurement on the created combination pattern under the verification environment (S40). This is the second performance measurement.

[0178] After the second performance measurement, the production environment configuration unit 118 selects the highest performance mode in the first and second measurements ( S41 ), and ends the processing of this flow.

[0179] As evaluated in Non-Patent Document 4, the degree of speed-up is higher when offloading a function module that has been tuned for an accelerator that performs processing in units of function modules including a plurality of loop statements is offloaded, compared with offloading each loop statement.

[0180] "Install"

[0181] The uninstall server 1 understands the program structure such as the called library or the defined class and structure by code analysis.

[0182] Next, the offload server 1 detects a GPU library, an FPGA IP core, and the like that can speed up the called library.

[0183] The uninstall server 1 uses the called library as a key to obtain an executable file, OpenCL, etc. that can be accelerated from the records registered in the code pattern database 133. When a replacement function that can be accelerated is detected, the uninstall server 1 creates the executable file.

[0184] In the case of multi-core CPU and GPU libraries, the original part is deleted and replaced with a description to call the replacement library (CUDA library, etc.). In the case of FPGA IP cores, after deleting the original part from the host code, the OpenCL code obtained by the description is replaced with the kernel code. After the replacement description is completed, the compilation is performed with gcc for multi-core CPU, with PGI compiler for GPU, and with Intel Acceleration Stack for FPGA.

[0185] Although the library call is recorded, the processing is also executed in parallel when similarity detection is used. Deckard is used to perform similarity detection between the detected partial code of the class, structure, etc. and the comparison code registered in the DB, and the functional modules, corresponding GPU libraries, FPGA IP cores, etc. whose similarity exceeds the threshold are found. In particular, when the interface of the library, IP core to be replaced is different from that of the replacement source code, such as the independent variable, return value, type, etc., the uninstall server 1 confirms with the user who commissioned the uninstallation whether the interface can be changed according to the replacement target library, IP core, and creates an executable file after confirmation.

[0186] Here, the offload server 1 creates an executable file that can be used to measure the performance of the GPU and FPGA in the verification environment.

[0187] During the function module uninstallation, the uninstallation server 1 measures the performance of the replacement function module with and without uninstallation one by one to confirm whether it can be accelerated. In the six uninstallation trials, if there is only one mode with a higher CPU speed than the normal CPU speed, the mode is selected, but if there are multiple modes, the following logic is used to create the solution mode.

[0188] [Automatic uninstall action]

[0189] The offload server 1 of the present embodiment is an example of a technology that is suitable for automatically offloading user application logic to an accelerator as an element technology of an environment adaptation software system.

[0190] Figure 6 This is a diagram showing the automatic uninstallation process of the uninstallation server 1.

[0191] like Figure 6 As shown, the uninstall server 1 is adapted to the element technology of the environment adaptation software system. The uninstall server 1 has a control unit 11 , a test case database 131 , an intermediate language file 132 , and a verification device 14 .

[0192] The uninstall server 1 obtains the source code 130 used by the user.

[0193] The user uses resource 15. Resource 15 is, for example, device 151, device 152 with CPU and GPU, device 153 with CPU and FPGA, and device 154 with CPU. The offload server 1 automatically offloads the function processing to the accelerator of device 152 with CPU and GPU and device 153 with CPU and FPGA.

[0194] Below, refer to Figure 6 The operation of each part is described by the step number.

[0195] 《Step S11: Specifying Source Code》

[0196] In step S11, the code designation unit 111 (see Figure 1 ) determines the processing function (image analysis, etc.) of the service provided to the user. Specifically, the code specifying unit 111 specifies the input source code.

[0197] 《Step S12: Analyze source code》

[0198] In step S12, the code analysis unit 112 (see Figure 1 )Analyze the source code of the processing function and master the structure of loop statements, FFT library calls, etc.

[0199] 《Step S13: Extracting the uninstallation range》

[0200] In step S13, the processing designation unit 114 (see Figure 1 ) determines the loop statements contained in the source code of the application, and for each loop statement, specifies the parallel processing specified statement in the accelerator for compilation. Specifically, the unloading range extraction unit 114a (refer to Figure 1 ) Extract loop statements, FFT, etc. that can be offloaded to GPU and FPGA.

[0201] <Step S14: Output intermediate language file>

[0202] In step S14, the processing designation unit 114 (see Figure 1 ) The intermediate language file output unit 114b outputs the intermediate language file 132. The output of the intermediate language is not completed once, but is repeated in order to search for a suitable uninstallation area and to optimize execution through trial.

[0203] 《Step S15: Processing when compiling errors occur》

[0204] In step S15, the processing mode creation unit 115 (see Figure 1 ) creates a parallel processing mode, which means that loop statements with compilation errors are excluded from the uninstallation objects, and specifies whether to parallel process loop statements without compilation errors.

[0205] 《Step S21: Configuring executable files》

[0206] In step S21, the executable file configuration unit 116a (see Figure 1 ) Deploy the executable file exported by the intermediate language in the verification device 14 with many-core CPU, GPU and FPGA.

[0207] <Step S22: Performance measurement>

[0208] In step S22, the performance measuring unit 116 (see Figure 1 ) to execute the configured file and measure the performance during uninstallation.

[0209] In order to make the unloading area more suitable, the performance measurement result is returned to the processing mode preparation unit 115, and the processing mode preparation unit 115 prepares another unloading mode. Then, the performance measurement unit 116 measures the performance of the other unloading mode (refer to Figure 6 denoted by reference numeral e).

[0210] like Figure 6 As shown by arrow e, the control unit 11 repeatedly executes the processing from step S12 to step S22.

[0211] The automatic uninstallation function of the control unit 11 is summarized as follows.

[0212] That is, the processing designation unit 114 determines the loop statements of the source code, specifies the parallel processing designation statements for each loop statement and compiles it. Then, the processing mode making unit 115 makes a parallel processing mode, which means that the loop statements with compilation errors are excluded from the uninstallation objects, and specifies whether the loop statements without compilation errors are processed in parallel. Then, the performance measurement unit 116 compiles the source code of the parallel processing mode, and configures it in the verification device 14, and performs performance measurement processing in the verification device 14. The executable file making unit 117 selects the mode with the highest processing performance from a plurality of parallel processing modes based on the performance measurement results repeated a specified number of times, and compiles the selected mode to make an executable file.

[0213] 《Step S23: Configuration to the official environment》

[0214] In step S23 , the production environment configuration unit 118 determines a mode that specifies the final uninstallation area and deploys it in the production environment for the user.

[0215] <Step S24: Performance Measurement Test and Execution>

[0216] In step S24 , after the executable file is arranged, in order to show the performance to the user, the performance measurement test extraction and execution unit 119 extracts the performance test items from the test case database 131 and automatically executes the extracted performance tests.

[0217] 《Step S25: Providing prices and performance, etc. to users》

[0218] In step S25, the user providing unit 120 presents the user with information such as price and performance based on the performance test result. The user determines whether to start paid use of the service based on the presented information such as price and performance.

[0219] It is assumed that the above steps S11 to S25 are performed in the background of the user using the service, for example, during the first day of temporary use.

[0220] As described above, the control unit 11 of the uninstall server 1, in the case of the element technology applicable to the environment adaptation software system, extracts the uninstall area from the source code of the application used by the user and outputs the intermediate language (S11~S15) in order to uninstall the functional processing. The control unit 11 configures the executable file exported by the intermediate language in the verification device 14 and executes it, and verifies the uninstall effect (S21~S22). After repeating the verification and determining the appropriate uninstall area, the control unit 11 deploys the executable file in the formal environment actually provided to the user and provides it as a service (S23~S25).

[0221] [Automatic unloading using the loop statement of the genetic algorithm]

[0222] Automatically offloading loop statements to GPU and multi-core CPU is used for repeated Figure 6 Steps S12 to S22 are performed, and finally the uninstall code deployed in step S23 is processed.

[0223] GPU is a device that generally does not guarantee latency, but is suitable for increasing throughput through parallel processing. There are various applications for GPU. Data encryption processing, image processing for camera image analysis, machine learning processing for large-scale sensor data analysis, etc. are representative, and these processes are mostly repetitive. Therefore, the unloading server 1 automatically unloads the loop statement contained in the source code of the application to the GPU to achieve high speed.

[0224] However, as described in the prior art, high-speed processing requires appropriate parallel processing. In particular, when using a GPU, due to the dump between the CPU and the GPU, in most cases, the performance is not good if the amount of data is small or the number of loops is small. In addition, depending on the time of memory data transfer, sometimes the combination of various loop statements (loop statements) that can be parallelized and high-speed is not the fastest. For example, among 10 loop statements (loop statements), when the first, fifth, and tenth three can be high-speed compared to the CPU, the combination of the first, fifth, and tenth three is not necessarily the fastest.

[0225] In order to specify an appropriate parallel region, the PGI compiler is sometimes used to optimize loop statements by trial and error to see if they can be parallelized. However, trial and error requires a lot of work, and when provided as a service, there is a problem of delaying the start of user use and increasing costs.

[0226] Therefore, in this embodiment, a suitable offloading area is automatically extracted from a general program without hypothetical parallelization. Therefore, the offloading server 1 checks the offloading of functional modules in the order of many-core CPU→GPU→FPGA, and then checks the offloading of loop statements in the order of many-core CPU→GPU→FPGA. By checking the functional modules with high offloading effects before the loop statement, and checking the functional modules with high offloading effects in the order of low verification cost, that is, many-core CPU→GPU→FPGA, it is possible to efficiently search for a pattern that can be accelerated.

[0227] [Searching method of the control unit 11 using a simple genetic algorithm]

[0228] Figure 7 This is a diagram showing a search state of the control unit 11 using a simple genetic algorithm of the offload server.

[0229] Genetic algorithm is one of the combinatorial optimization methods that imitates the evolution process of organisms. The flowchart of genetic algorithm is initialization → evaluation → selection → crossover → sudden mutation → end judgment.

[0230] In this embodiment, a simplified genetic algorithm is used to simplify the process in the genetic algorithm. The simplified genetic algorithm is a simplified genetic algorithm in which genes are only 1 and 0, and the value of a gene at one position is changed to the opposite value through roulette wheel selection, one-point crossover, and sudden mutation.

[0231] "initialization"

[0232] During initialization, after checking whether all loop statements in the source code can be parallelized, the loop statements that can be parallelized are mapped to the gene sequence. When GPU processing is performed, it is set to 1, and when GPU processing is not performed, it is set to 0. A specified number of individuals M is prepared for the gene, and 1 or 0 is randomly assigned to 1 loop statement.

[0233] Specifically, the control unit 11 (see Figure 1 ) Get the source code used by the user 130 (refer to Figure 6 ), check whether the loop statement can be parallelized according to the code pattern 141 of the source code 130. Figure 8 As shown, when three loop statements are detected from the code pattern 141d, 1 bit is randomly assigned to each loop statement, and here, 3 bits of 1 or 0 are randomly assigned to the three loop statements. For example, it is set to 0 when processed by a single-core CPU, and it is set to 1 when output to a multi-core GPU. However, 1 or 0 is randomly assigned at this stage.

[0234] The code equivalent to the gene length is 3 bits, and the code equivalent to the gene length of 3 bits is 2 3= 8 modes, for example, 100, 110, ... In addition, Figure 7 , the circular mark (○ mark) in the code pattern 141 is shown as a code.

[0235] "evaluate"

[0236] In the evaluation of step S300, the deployment and performance are measured. That is, the performance measurement unit 116 (see Figure 1 ) compiles the code corresponding to the gene and deploys it in the verification device 14 for execution. The performance measurement unit 116 performs a benchmark performance measurement to improve the fitness of the gene in the mode with good performance (parallel processing mode).

[0237] "choose"

[0238] In the selection of step S301, the high performance coding mode is selected according to the suitability. Figure 1 ) According to the fitness, only the genes with high fitness of the specified number of individuals are selected. In this embodiment, roulette wheel selection corresponding to the fitness and elite selection of the genes with the highest fitness are performed.

[0239] exist Figure 7 , it is shown that the number of circular marks (○ marks) in the selected code pattern 142 is reduced to 3 as a search appearance.

[0240] "cross"

[0241] In crossover, a portion of genes is replaced at a certain point between selected individuals at a certain crossover rate Pc to produce offspring individuals.

[0242] The gene of a certain mode (parallel processing mode) selected by the roulette wheel is crossed with the gene of another mode. The position of the crossover is arbitrary, for example, the crossover is performed at the second position in the above three-position code.

[0243] Sudden Mutation

[0244] In a sudden mutation, the values ​​of individual genes are changed from 0 to 1 or from 1 to 0 according to a certain sudden mutation rate Pm.

[0245] In addition, sudden mutation is introduced to avoid local solutions. In addition, it can also be a way to reduce the amount of calculation without sudden mutation. Then, as shown in step S302, each code that has implemented crossover and sudden mutation is used as the code of the next generation.

[0246] End judgment

[0247] Generate the next generation of code patterns after crossover and mutation.

[0248] In the termination judgment, the process is terminated after repeating the designated number of generations T times, and the gene with the highest fitness is taken as the solution.

[0249] For example, a performance measurement is performed, and three individuals with fast processing speeds are selected, such as individuals with genes 110, 010, and 001. The next generation recombines these three through a genetic algorithm, for example, creating a new mode (parallel processing mode) 011 (an example). At this time, sudden mutations such as changing from 0 to 1 are randomly inserted into the recombined mode. The above operation is repeated to find the mode with the fastest processing speed. A specified generation (for example, 20 generations) is determined, and the remaining mode in the last generation is used as the final solution.

[0250] 《Deployment (Configuration)》

[0251] It is redeployed in the formal environment in a parallel processing mode with the highest processing performance, which is equivalent to the gene with the highest fitness, and provided to users.

[0252] Supplementary Notes

[0253] The following describes a case where there are a considerable number of loop statements that cannot be offloaded to the GPU. For example, although there are 200 loop statements, only about 30 can be offloaded to the GPU. Here, excluding the wrong loop statements, the genetic algorithm is performed on these 30 loop statements.

[0254] OpenACC has a compiler that extracts and executes bytecodes for the GPU specified by the instruction "#pragma acc kernels", thereby enabling GPU offloading. By writing a loop statement command in this "#pragma", it is possible to determine whether the loop statement is running in the GPU.

[0255] For example, when C / C++ is used, the C / C++ code is analyzed and loop statements are detected. When a loop statement is detected, the loop statement is written in OpenACC using "#pragma acc kernels", which is a grammar for parallel processing. In detail, loop statements are added one by one to the empty "#pragma acc kernels" for compilation. If an error occurs, the loop statement itself cannot be processed by the GPU, so it is excluded. The remaining loop statements are detected in this way. And, the loop statements without errors are used as the length (gene length). If there are 5 loop statements without errors, the gene length is 5, and if there are 10 loop statements without errors, the gene length is 10. In addition, parallel processing cannot be performed in cases where there is a dependency on data, such as using the previous processing for the next processing.

[0256] The above is the preparation stage. Then the genetic algorithm processing is carried out.

[0257] A code pattern with a gene length corresponding to the number of loop statements is obtained. First, the parallel processing patterns 10010, 01001, 00101, etc. are randomly assigned. Genetic algorithm processing is performed and compiled. At this time, although it is a loop statement that can be unloaded, errors sometimes occur. This is the case where the loop statement is a hierarchical structure (any one of which can be specified to perform GPU processing). In this case, the wrong loop statement can be left. Specifically, there is a method to make it time out by making it a form in which the processing time becomes longer.

[0258] Deployed in the verification device 14, standard tests are performed. For example, if it is image processing, standard tests are performed through the image processing. The shorter the processing time, the higher the fitness is evaluated. For example, set it as the reciprocal of the processing time, and set the fitness of an individual who takes 10 seconds to process as 1. Set the fitness of an individual who takes 100 seconds to process as 0.1. Set the fitness of an individual who takes 1 second to process as 10.

[0259] The unloading server 1 selects a loop statement with high adaptability. The unloading server 1 selects 3 to 5 from 10 individuals, for example, and reorganizes them to create a new code pattern. During the production process, sometimes the same code pattern as before is produced. In this case, there is no need to perform the same standard test, so the unloading server 1 uses the data with the same adaptability as before. The unloading server 1 of this embodiment stores the code pattern and its processing time in the storage unit 13.

[0260] The above has described the search mode of the control unit 11 based on a simple genetic algorithm.

[0261] Figure 8 It is a diagram showing the mapping of loop statements to the gene sequence of a multi-core CPU.

[0262] The code pattern 141d includes three loop statements. Here, a 1-bit binary number is assigned to each loop statement, and three bits of 1 or 0 are randomly assigned to the three loop statements.

[0263] The instruction "#pragma omp parallelfor" is given to the first for loop statement of the code pattern 141d. At this time, the first for loop statement is compiled to be offloaded to the many cores. In addition, the gene sequence 100 of the code pattern 141d is shown on the left side of the code pattern 141d.

[0264] Fig.9A and Fig. 9BThis is a flowchart of the process of selecting a mode for offloading loop statements to a multi-core CPU.

[0265] First, the code analysis unit 112 analyzes the loop statement of the C / C++ source code (S90). The process specification unit 114 specifies the loop statement and reference relationship of the C / C++ source code (S91).

[0266] The process specification unit 114 operates the standard test tool to grasp the number of cycles of each loop statement, and when each cycle is allocated using a threshold value ( S92 ), the possibility of parallel processing of each loop statement is checked ( S93 ).

[0267] In addition, the PGI compiler used in the automatic unloading of the GPU outputs an error when parallelization is not possible. However, the OpenMP compilers such as gcc regard the above errors as the responsibility of the programmer. Therefore, in order to achieve automation, the processing performed by the OpenMP directive is simplified to whether the loop statement is processed in parallel using the multi-core CPU, and when the performance is measured, it is also checked whether the final calculation result after parallel processing is correct, thereby becoming a structure that only leaves the pattern of obtaining the correct calculation result in evolutionary computing.

[0268] Next, the processing designation unit 114 counts the number of loop statements that have the possibility of parallel processing as the gene length (S94), and prepares a gene sequence of a specified number of individuals as an initial value (S95). Here, the processing designation unit 114 only produces a gene sequence of a specified number of individuals by randomly assigning 0 and 1.

[0269] The processing designation unit 114 maps the C / C++ source code to the gene and prepares a pattern for designating the number of individuals (S96). Specifically, the processing designation unit 114 inserts the instruction for designating parallel processing into the C / C++ code (for example, referring to Figure 8 The #pragma directive).

[0270] The control unit 11 repeats the processing of steps S100 to S108 a designated number of times.

[0271] In addition, in the process of repeating the designated number of generations, the processing of steps S101 to S104 is further repeated for the designated number of individuals. That is, in the process of repeating the designated number of generations, the repeated processing for the designated number of individuals is performed in a nested state.

[0272] In the process of repeating the designated number of individuals, the processing pattern creation unit 115 (refer to Figure 1), using the gcc compiler to compile the C / C++ source code specified by the gene mode, that is, each offload mode (S102). That is, the processing mode creation unit 115 uses the gcc compiler on the verification device 14 with a multi-core CPU to compile the created C / C++ code.

[0273] Here, if parallel processing is specified for multiple nested loop statements, a compile error may occur. In this case, the same processing is performed as when the processing time exceeds the performance measurement.

[0274] Performance measurement unit 116 (see Figure 1 ) The executable file obtained by compiling the uninstallation mode, that is, the compiled uninstallation mode, is deployed on the verification device 14 equipped with a multi-core CPU (S103), the configured executable file is executed, and the standard test performance during uninstallation is measured (S104).

[0275] Here, in the intermediate generation, the gene of the same pattern as before is not measured, but the same value is used. That is, in the genetic algorithm process, when the gene of the same pattern as before is generated, the individual is not compiled or the performance is measured, but the same measurement value as before is used.

[0276] In step S105 , if the designated number of repetitions has not been completed, the control unit 11 returns to the process of step S101 , and if all designated numbers of repetitions have been completed, the process proceeds to step S106 .

[0277] In step S106, the executable file creation unit 117 (see Figure 1 ) The individuals with shorter processing time are evaluated in a way that the fitness is higher, and individuals with higher performance are selected.

[0278] Executable file creation unit 117 (see Figure 1 ) evaluates the difference between the calculation results of each individual and the calculation results of the single-core CPU, and selects individuals within the allowable range (S107). During performance measurement, the executable file creation unit 117 compares the final calculation result with the same result when parallel processing is not performed and with the case where the source code is processed using a normal CPU. If the difference is too large to be allowed, the fitness of the mode is set to 0 and it is not selected in the next generation. During performance measurement, the executable file creation unit 117 also checks whether the final calculation result during parallel processing is correct, so that it can be narrowed down to the mode that obtains the correct calculation result in evolutionary computing.

[0279] The executable file generation unit 117 performs crossover and mutation processing on the selected individuals to generate individuals of the next generation (S108). This is to perform compilation, performance measurement, fitness setting, selection, crossover, and mutation processing on the individuals of the next generation.

[0280] That is, for all individuals, after measuring the standard test performance, the executable file production unit 117 sets the fitness of each gene sequence according to the standard test processing time. The executable file production unit 117 selects the remaining individuals according to the set fitness. Then, the executable file production unit 117 performs genetic algorithm processing of crossover, sudden mutation, and direct copy processing on the selected individuals to produce the next generation of individual groups.

[0281] In step S109 , if the designated number of iterations has not been completed, the control unit 11 returns to the process of step S100 . If the designated number of iterations has been completed, the control unit 11 proceeds to step S110 .

[0282] In step S110, after the execution of the genetic algorithm processing for the specified number of generations, the executable file creation unit 117 terminates the execution when the C / C++ code corresponding to the gene sequence with the highest performance (the parallel processing mode with the highest performance) is used as the solution. Fig. 9B processing.

[0283] In this way, even if the environment of a multi-core CPU is the migration target, it is possible to search for a pattern that can efficiently speed up the loop statement.

[0284] Like GPUs, multi-core CPUs also use multiple computing cores to speed up processing through parallelization. The difference from GPUs is that in the case of multi-core CPUs, the memory is shared, so there is no need to consider the overhead caused by data transfer between the CPU and GPU memories, which often becomes a problem when offloading to the GPU. In addition, the OpenMP specification is frequently used in the parallelization of program processing in multi-core CPUs. OpenMP is a specification that specifies parallel processing for programs using directives such as "#pragma omp parallel for". Processing parallelization in OpenMP is the responsibility of the OpenMP programmer, and when processing that cannot be parallelized is parallelized, the compiler does not output an error, but instead outputs the calculation result incorrectly.

[0285] In view of this, in this embodiment, the automatic offloading of loop statements for multi-core CPUs adopts the following evolutionary computing method: multiple parallel processing modes are created in OpenMP to specify whether the loop can be performed using "#pragma", and actual performance measurements are repeatedly performed in a verification environment to gradually increase the speed.

[0286] "Install"

[0287] The offload server 1 analyzes the C / C++ source code, finds the loop statement, and understands the program structure such as the variable data used in the loop statement and the processing of the variable.

[0288] Since loop statements that cannot be processed in parallel need to be excluded, the offload server 1 attempts to insert instructions for processing by the GPU for each loop statement, and excludes loop statements with errors from the target of the genetic algorithm. Here, the number of loop statements without errors is the gene length.

[0289] Next, the offload server 1 prepares a gene sequence of a designated number of individuals as an initial value. Each gene value is randomly assigned to 0 and 1. The offload server 1 inserts an instruction to specify GPU or multi-core CPU processing into the C / C++ code according to the prepared gene sequence when the gene value is 1.

[0290] The offload server 1 compiles the C / C++ code into which the instruction is inserted by gcc, and deploys the compiled executable file to measure the performance. In the performance measurement, the offload server 1 checks whether the difference between the calculation result and the original code is large when the processing time and the PCAST ​​function of the PGI compiler are used for parallel processing, and sets the fitness to 0 if the difference is outside the allowable range.

[0291] The offloading server 1 sets the fitness of each individual according to the processing time after the performance measurement for all individuals. According to the set fitness, the remaining individuals are selected. The selected individuals are processed by a genetic algorithm based on crossover, sudden mutation, and direct copying to produce the next generation of individual groups.

[0292] The offloading server 1 further performs instruction insertion, compilation, performance measurement, fitness setting, selection, crossover, and sudden mutation processing on the individuals of the next generation, and repeats the designated number of generations. After the designated number of generations of genetic algorithm processing is completed, the offloading server 1 uses the C / C++ code with instructions corresponding to the gene sequence with the highest performance as the solution.

[0293] Fig.10 It is a diagram showing the mapping of loop statements to the gene sequence of the GPU.

[0294] "#pragma acc kernels" is added to the initial for loop statement of the code pattern 141e. At this time, the initial for loop statement is compiled to be offloaded to the GPU. In addition, the gene sequence 100 of the code pattern 141e is displayed on the left side of the code pattern 141e.

[0295] Fig.11A and Fig. 11B This is a flowchart of the selection process of the mode of offloading loop statements to the GPU. This selection process uses the method of Non-Patent Document 2.

[0296] The offload server 1 performs the following processing using the OpenACC compiler for C / C++.

[0297] Code analysis unit 112 (see Figure 1 ) analyzes the loop statement by code parsing of the C / C++ source code (S120). Then, when the loop statement of the C / C++ source code and its reference relationship are determined (S121), the processing designation unit 114 (reference Figure 1 ) activates the standard test tool, grasps the number of cycles of each loop statement, and allocates them according to the threshold value (S122). Then, the processing designation unit 114 checks the parallel processing possibility of each loop statement (S123).

[0298] Next, the control unit 11 repeats the processing of steps S124 to S127 for the number of loop statements.

[0299] The processing designation unit 114 designates parallel processing for each loop statement and compiles it (S125). Fig.10 As shown, parallel processing in OpenACC is specified as "#pragma acc kernels".

[0300] When a compilation error occurs, the process designation unit 114 deletes the designation of parallel processing and excludes the loop statement from the uninstall target (S126). Then, if the process has been repeated for all loop statements, the control unit 11 proceeds to step S128.

[0301] The processing designation unit 114 counts the number of loop statements without compile errors as the gene length (S128), and prepares a gene sequence of a specified number of individuals. Here, a gene sequence of a specified number of individuals is created by randomly assigning 0 and 1 as initial values. Next, the processing designation unit 114 maps the C / C++ source code to the gene and prepares a pattern of a specified number of individuals (S129). Specifically, the processing designation unit 114 inserts instructions for specifying parallel processing into the C / C++ code (for example, referring to the prepared gene sequence) when the value of the gene is 1. Fig.10 ) in the #pragma directive.

[0302] The control unit 11 repeats the processing of steps S130 to S137 a designated number of times.

[0303] In addition, in the process of repeating the designated number of generations, the processing of steps S131 to S134 is further repeated the designated number of individuals. That is, in the process of repeating the designated number of generations, the repeated processing is performed the designated number of individuals in a nested state.

[0304] In the repetition process of the designated number of individuals, the processing pattern creation unit 115 (refer to Figure 1 ) The C / C++ source code that specifies the instructions according to the gene pattern, that is, each offload pattern, is compiled by the PGI compiler (S132). That is, the processing pattern creation unit 115 compiles the created C / C++ code by the PGI compiler on the verification device 14 having a GPU.

[0305] Here, a compile error may occur when multiple nested loop statements are specified in parallel, etc. In this case, it is treated in the same way as when the processing time is exceeded during performance measurement.

[0306] Performance measurement unit 116 (see Figure 1 ) deploys the executable file obtained by compiling the uninstall mode, that is, the compiled uninstall mode (S133) on the verification device 14 equipped with a CPU and a GPU, executes the configured executable file, and measures the standard test performance during uninstallation (S134).

[0307] Here, in the intermediate generation, the gene of the same pattern as before is not measured, but the same value is used. That is, in the genetic algorithm process, when the gene of the same pattern as before is generated, the individual is not compiled or the performance is measured, but the same measurement value as before is used.

[0308] In step S135 , if the designated number of repetitions has not been completed, the control unit 11 returns to the process of step S131 , and if all designated number of repetitions have been completed, the process proceeds to step S136 .

[0309] In step S136, the executable file creation unit 117 (see Figure 1 ) The individual with the shorter processing time is evaluated in a way that the fitness is higher, and the individual with high performance is selected. Then, the executable file production unit 117 performs crossover and sudden mutation processing on the selected individual to produce the next generation of individuals (S137). This is because the next generation of individuals are compiled, performance measured, fitness set, selected, crossover, and sudden mutation processing is performed.

[0310] That is, for all individuals, after measuring the standard test performance, the executable file production unit 117 sets the fitness of each gene sequence according to the standard test processing time. In addition, the executable file production unit 117 selects the remaining individuals according to the set fitness. In addition, the executable file production unit 117 performs genetic algorithm processing such as crossover, sudden mutation, and direct copy on the selected individuals to produce the next generation of individual groups.

[0311] In step S138, if the designated number of iterations has not been completed, the control unit 11 returns to the process of step S130. If the designated number of iterations has been completed, the process proceeds to step S139.

[0312] In step S139 after the genetic algorithm processing of the specified number of generations is completed, the execution file creation unit 117 uses the C / C++ code corresponding to the highest performance gene sequence (highest performance parallel processing mode) as the solution, and ends Fig. 11B processing.

[0313] As a basic technical problem, the compiler can find the limitation that the loop statement cannot be processed in parallel on the GPU, but it is difficult to find the suitability of the loop statement for parallel processing on the GPU.

[0314] Generally speaking, loops with a large number of loops are considered suitable for GPU offloading, but it is difficult to predict what level of performance will be achieved by actually offloading to the GPU without actual measurement. Therefore, the instructions to offload the loop to the GPU are manually performed, and trial and error of performance measurement is frequently performed.

[0315] Non-patent document 2 proposes to automatically discover appropriate loop statements to be offloaded to the GPU using a genetic algorithm, which is one of the evolutionary computing methods. Based on a general program for a normal CPU that does not assume GPU processing, a check for parallelizable loop statements is first performed, and then for a group of parallelizable loop statements, a setting of 1 when executed by the GPU and 0 when executed by the CPU is performed to generate genes, and performance verification is repeatedly performed in a verification environment to search for an appropriate area.

[0316] Based on the concentration on the parallel loop statements, the high-speed parallel processing patterns are maintained and reorganized in the form of gene parts, thereby efficiently searching for high-speed patterns from the huge number of parallel processing patterns that can be obtained.

[0317] In non-patent document 2, in addition to appropriately extracting loop statements, the following solution is proposed regarding variables used in nested loop statements: when unloading loop statements to the GPU, if CPU-GPU transfer is performed at the nested lower level, it is inefficient to perform the transfer in each lower loop. Therefore, for variables that have no problem performing CPU-GPU transfer at the upper level, they are transferred at the upper level.

[0318] GPU automatic offloading of loop statements can be automatically performed by optimizing and reducing CPU-GPU transfer using evolutionary computing methods.

[0319] Fig. 12A and Fig. 12B This is a flowchart of the selection process of the mode of offloading loop statements to the FPGA. This selection process uses the method of Non-Patent Document 3.

[0320] First, the code analysis unit 112 analyzes the source code to be uninstalled (S150), and analyzes the loop statement and the information of the variables according to the language of the source code.

[0321] Then, after the offload range extraction unit 114a identifies the loop statement and the reference relationship of the source code (S151), it narrows down the candidate range for whether to try FPGA offload for the identified loop statement. Arithmetic strength is an indicator of whether the loop statement has an offload effect.

[0322] The offload range extraction unit 114a uses an arithmetic strength analysis tool to calculate the arithmetic strength of the loop statement of the application (S152). The arithmetic strength is an indicator that increases when the number of calculations is large and decreases when the number of accesses is large. For a processor, a process with high arithmetic strength is a heavy process. Therefore, the offload range extraction unit 114a uses the arithmetic strength analysis tool to analyze the arithmetic strength of the loop statement, and reduces the loop statements with high arithmetic strength to offload candidates.

[0323] Even if the loop statement is a high-arithmetic-intensity one, there is a problem of excessive consumption of FPGA resources when processing the loop statement in the FPGA. Therefore, this article describes the calculation of the amount of resources when the FPGA processes a high-arithmetic-intensity loop statement.

[0324] As a process when compiling in FPGA, a high-level language such as OpenCL is converted to a level such as HDL that describes the hardware, and actual wiring processing is performed based on this. At this time, wiring processing takes a lot of time, but the time until the intermediate stage of HDL is only a few minutes. Even at the intermediate stage of HDL, the resources such as Flip Flop and LookUp Table used in FPGA are known. Therefore, if you observe the intermediate stage of HDL, you can know the amount of resources used in a short time even if the compilation is not completed.

[0325] Therefore, in this embodiment, the processing mode creation unit 115 converts the target loop statement into a high-level language such as OpenCL, and first calculates the resource amount. In addition, since the arithmetic intensity and the resource amount when the loop statement is offloaded are determined, the arithmetic intensity / resource amount or the arithmetic intensity×number of loops / resource amount is used as the resource efficiency. Then, the loop statements with high resource efficiency are further narrowed down to offload candidates.

[0326] return Fig. 12A The processing pattern creation unit 115 uses a profiling tool such as gcov or gprof to measure the number of loops of the applied loop statement (S153), and reduces the number of loops with high arithmetic intensity from the loop statements (S154).

[0327] The processing pattern creation unit 115 creates OpenCL for offloading the reduced loop statements to the FPGA ( S155 ).

[0328] Here, we will explain the OpenCLization of loop statements. That is, when the loop statement is converted to a high-level language through OpenCL, etc., two processes are required. One process is to split the CPU processing program into the core (FPGA) and the host (CPU) according to the high-level language syntax of OpenCL, etc. The other process is to add a technique for speeding up the split. Generally speaking, in order to use FPGA for speeding up, there are local caches, stream processing, multiple instantiations, loop statement expansion processing, a collection of nested loop statements, memory cross processing, etc. These are not absolutely effective depending on the loop statement, but they are widely used as a method for speeding up.

[0329] Next, since several loop statements with high resource efficiency are selected, they are used to create a number of offload patterns for actual performance measurement. The speed-up in FPGA can be achieved by concentrating FPGA resources in one process or by distributing FPGA resources in multiple processes. The offload server 1 creates a certain number of patterns of the selected single loop statements and performs pre-compilation as a pre-stage for working in the actual FPGA device.

[0330] The processing pattern creation unit 115 precompiles the created OpenCL to calculate the amount of resources to be used ( S156 ), and reduces loop statements with high resource efficiency ( S157 ).

[0331] Then, the executable file creation unit 117 compiles OpenCL for unloading the reduced loop statements (S158). The performance measurement unit 116 measures the performance of the compiled program (S159). This is the first performance measurement.

[0332] The processing mode making unit 115 lists loop statements that are more efficient than the CPU in the performance measurement (S160), and makes a combination of the loop statements in the list to offload OpenCL (S161). The processing mode making unit 115 performs precompilation using the combined offload OpenCL and calculates the amount of resources used (S162). This is the second calculation of the amount of resources. In addition, the processing mode making unit 115 may not perform precompilation, but the sum of the amount of resources in the precompilation before the first measurement. In this way, the number of precompilations can be reduced.

[0333] The executable file creation unit 117 compiles the combined uninstalled OpenCL (S163). The performance measurement unit 116 measures the performance of the compiled program (S164). This is the second performance measurement.

[0334] The production environment configuration unit 118 selects the highest performance mode in the first and second measurements ( S165 ), and ends the processing of this flow.

[0335] In this way, the FPGA automatic offloading of loop statements focuses on loop statements with high arithmetic intensity and number of loops and high resource efficiency, creates offload patterns, and performs high-speed pattern searches through actual measurements in a verification environment.

[0336] In FPGA, when considering offloading specific loop statements that take a long time to process to FPGA for speeding up, it is difficult to predict which loop will be faster to offload, so it is proposed to automatically measure performance in a verification environment similar to GPU. However, it takes more than several hours to compile OpenCL on FPGA and run it on actual devices, so it is not realistic to repeatedly measure performance using genetic algorithms that automatically offload GPUs because the processing time becomes huge.

[0337] Therefore, in this embodiment, after reducing the candidate loop statements to be offloaded to the FPGA, a performance measurement trial is performed. Specifically, first, an arithmetic strength analysis tool such as the ROSE framework is used to extract loop statements with high arithmetic strength from the discovered loop statements. In addition, analysis tools such as gcov and gprof are also used to extract loop statements with a large number of cycles.

[0338] Then, loop statements with high arithmetic intensity and high number of loops are selected as candidates for OpenCL. For candidate loop statements with high arithmetic intensity and high number of loops, the created OpenCL is pre-compiled to find loop statements with high resource efficiency. Since the resources such as Flip Flop and Look Up Table created are known during the compilation process, loop statements with low resource utilization can be further reduced.

[0339] Since several loop statements are selected, they are used to measure the performance. Speed-up in FPGA can be achieved by concentrating FPGA resources in one process or by distributing FPGA resources in multiple processes. Therefore, the selected single loop statement is compiled and performance measured so that it can work in the actual FPGA device. For the single loop statement that can be further accelerated, a combination pattern is also created and a second performance measurement is performed. The unloading server 1 selects the highest speed pattern as the solution among the multiple patterns for performance measurement in the verification environment.

[0340] For automatic FPGA unloading of loop statements, arithmetic intensity, number of loops, and resource quantity are used to reduce candidate loop statements, and then multiple mode performance measurements are performed in a verification environment to enable automatic unloading.

[0341] "Install"

[0342] The offload server 1 analyzes the C / C++ source code, finds the loop statement, and understands the program structure such as variable data used in the loop statement.

[0343] Next, the offload server 1 executes ROSE to obtain the arithmetic strength of each loop statement, and uses gcov to obtain the number of cycles of each loop statement.

[0344] Next, the offload server 1 generates OpenCL code that offloads each loop statement with high arithmetic intensity and high number of loops to the FPGA. The OpenCL code is a code that uses the loop statement as the FPGA core and divides the rest as a CPU host program.

[0345] Next, the offload server 1 precompiles the generated OpenCL code and calculates the amount of resources used, such as flip flops. The amount of resources used is expressed as a ratio of the total amount of resources. Here, the offload server 1 selects a loop statement with high arithmetic intensity, high number of loops, and low amount of resources (high resource efficiency) based on the arithmetic intensity, number of loops, and amount of resources.

[0346] Next, the offload server 1 uses the selected loop statement as a candidate, creates a measured pattern, and compiles it. The offload server 1 performs performance measurement when each selected loop statement is offloaded to confirm whether it can be accelerated. As a result, in the case where multiple high-speed can be achieved, the offload server 1 also creates its combined OpenCL to perform performance measurement to confirm whether it can be accelerated compared to the single unit. However, since the amount of resources of FPGA is limited, the offload server 1 does not make it if the amount of resources does not reach the upper limit value during multiple offloads.

[0347] Finally, the off-load server 1 selects a high-speed mode as a solution from among the plurality of measurement modes.

[0348] The present invention and its effects

[0349] In the invention described in technical solution 1, an unloading server is provided, characterized in that it has a code analysis unit, a processing mode production unit, a performance measurement unit and a control unit, wherein the code analysis unit analyzes whether the source code of the software program contains a functional module that can be executed by an accelerator; the processing mode production unit produces a mode for unloading the functional module to the accelerator; the performance measurement unit deploys each of the modes for unloading the functional module in a verification environment to measure performance; the control unit is configured to, when the performance measured by the performance measurement unit is the expected performance, produce a mode for unloading the remaining loop statements in the software program except the functional module through the processing mode production unit, deploy each of the modes in the verification environment to measure performance through the performance measurement unit, and when the performance measured by the performance measurement unit is not the expected performance, produce a mode for unloading the loop statements of the software program through the processing mode production unit, and deploy each of the modes in the verification environment to measure performance through the performance measurement unit.

[0350] Thus, even if the migration target is an environment where multiple accelerators are mixed, high performance can be automatically improved. In addition, when the migration target has multiple accelerators on the same node, by simultaneously offloading the multiple accelerators, faster offloading can be achieved than when using a single accelerator.

[0351] Based on the offloading server described in technical solution 1, in the invention described in technical solution 2, it is characterized in that there are multiple types of accelerators, and the control unit selects the fastest mode among the modes of offloading to each of the accelerators.

[0352] According to this, even if the target environment is an environment where multiple accelerators are mixed, the performance can be automatically improved.

[0353] Based on the unloading server described in technical solution 1 or 2, in the invention described in technical solution 3, it is characterized in that the control unit tries the loop statement as an unloading object to the accelerator after trying the functional module, and the accelerator as the unloading target of the functional module and / or the loop statement is tried in the order of multi-core CPU, GPU, and FPGA.

[0354] According to this, in an environment where multiple types of accelerators are mixed, a pattern that can be accelerated can be efficiently searched.

[0355] Based on the unloading server described in Technical Solution 1, in the invention described in Technical Solution 4, it is characterized in that the control unit is configured to, during the unloading of the functional module or the loop statement, when a mode with a higher speed than the original processing is found for multiple accelerators and the same functional module or loop statement can be unloaded to the multiple accelerators, set the accelerator with higher performance as the unloading target; when different functional modules or different loop statements can be unloaded to different accelerators and cannot be unloaded to accelerators of the same node, set the accelerator with higher performance as the unloading target; when different functional modules or different loop statements can be unloaded to different accelerators and can be unloaded to accelerators of the same node, set the unloading targets of the functional modules or the loop statements to different accelerators respectively.

[0356] Based on this, in an environment where multiple accelerators are mixed, it is possible to search for a pattern that can efficiently speed up a functional module or a loop statement.

[0357] Based on the uninstallation server described in Technical Solution 1, in the invention described in Technical Solution 5, it is characterized in that the control unit is configured such that, during the uninstallation of the functional module and the loop statement, when the uninstallation target of the loop statement is a node different from the uninstallation target of the functional module, if the performance improvement brought about by the uninstallation based on the loop statement is lower than the performance improvement brought about by the uninstallation based on the functional module, the mode of uninstalling the loop statement is not tried, and the mode of uninstalling the functional module is tried; if the performance improvement brought about by the uninstallation based on the loop statement exceeds the performance improvement brought about by the uninstallation of the functional module, the mode of uninstalling the functional module is not tried, and the mode of uninstalling the loop statement is tried; when the uninstallation target of the loop statement and the uninstallation target of the functional module are the same node, the mode of uninstalling the functional module and the loop statement is tried.

[0358] Based on this, in an environment where multiple accelerators are mixed, it is possible to search for a pattern that can efficiently speed up a functional module or a loop statement.

[0359] In the invention described in technical solution 6, an unloading server is provided, characterized in that it has a code analysis unit, a processing mode production unit and a performance measurement unit, wherein the code analysis unit analyzes whether the source code of the software program contains a loop statement that can be executed by the multi-core CPU; the processing mode production unit produces a mode for unloading the loop statement to the multi-core CPU; the performance measurement unit maps each of the loop statements to a gene pattern, deploys each of the modes for unloading each of the loop statements in a verification environment to measure performance, sets high performance as high fitness, and repeatedly produces the next generation mode through elite selection, crossover and sudden mutation processing of a genetic algorithm, and in the performance measurement in the verification environment, the performance measurement unit compares the calculation result when the multi-core CPU is processed with the calculation result of the original processing, and sets the fitness of the gene pattern to be low when the error of the calculation result when the multi-core CPU is processed exceeds an allowable threshold.

[0360] According to this, even if the migration target is an environment of a multi-core CPU, it is possible to search for a pattern that can efficiently speed up the loop statement.

[0361] In the invention described in technical solution 7, there is provided an unloading control method, characterized in that the following steps are executed: a code analysis unit analyzes whether the source code of a software program contains a functional module that can be executed by an accelerator; a processing mode production unit produces a mode for unloading the functional module to the accelerator; a performance measurement unit deploys each of the modes for unloading the functional module in a verification environment to measure performance, and further executes the following steps: when the performance measured by the performance measurement unit is the expected performance, the processing mode production unit produces a mode for unloading the remaining loop statements in the software program except the functional module; the performance measurement unit deploys each of the modes in the verification environment to measure performance, and further executes the following steps: when the performance measured by the performance measurement unit is not the expected performance, the processing mode production unit produces a mode for unloading the loop statements of the software program; the performance measurement unit deploys each of the modes in the verification environment to measure performance.

[0362] Thus, even if the migration target is an environment where multiple accelerators are mixed, high performance can be automatically improved. In addition, when the migration target has multiple accelerators on the same node, by simultaneously offloading the multiple accelerators, faster offloading can be achieved than when using a single accelerator.

[0363] In the invention described in technical solution 8, an uninstaller is provided, which is used to enable a computer to execute the following steps: analyzing whether the source code of a software program contains a functional module that can be executed by an accelerator; creating a mode for unloading the functional module to the accelerator; deploying each of the modes for unloading the functional module in a verification environment to measure performance; when the measured performance is the expected performance, creating a mode for unloading the remaining loop statements in the software program except the functional module, and deploying each of the modes in the verification environment to measure performance; when the measured performance is not the expected performance, creating a mode for unloading the loop statements of the software program, and deploying each of the modes in the verification environment to measure performance.

[0364] Thus, even if the migration target is an environment where multiple accelerators are mixed, high performance can be automatically improved. In addition, when the migration target has multiple accelerators on the same node, by simultaneously offloading the multiple accelerators, faster offloading can be achieved than when using a single accelerator.

[0365] [Explanation of Reference Numerals]

[0366] 1: Offload server; 2: Cloud layer; 3: Network layer; 4: Device layer; 10: Gateway; 20: Network edge; 30: Data center; 11: Control unit; 12: Input / output unit; 13: Storage unit; 14: Verification device; 15: Resource; 111: Code designation unit; 112: Code analysis unit; 114: Processing designation unit; 114a: Offload range extraction unit; 114b: Intermediate language file output unit; 115: Processing mode creation unit; 116: Performance measurement unit; 116a: Executable file configuration unit; 117: Executable file creation unit ; 118: Formal environment configuration unit; 119: Performance measurement test extraction execution unit; 120: User-provided unit; 130: Source code; 131: Test case database; 132: Intermediate language file; 133: Code pattern database; 141, 142: Code pattern; 151~154: Device; 80: Communication network; 900: Computer; 910: CPU; 920: RAM; 930: ROM; 940: HDD; 950: Communication interface; 960: Input / output interface; 970: Media interface; 980: Recording medium.

Claims

1. An uninstall server, characterized in that: It has a code analysis unit, a processing mode creation unit, a performance measurement unit and a control unit, wherein: The code analysis unit analyzes whether the source code of the software program contains a functional module that can be executed by the accelerator; The processing mode making unit makes a mode for offloading the functional module to any one of the accelerators, and makes a mode for offloading the loop statement of the software program to any one of the accelerators; The performance measurement unit deploys each of the modes of offloading the functional module or the loop statement to the accelerator in a verification environment to measure performance; The control unit is configured as follows: When the performance measurement unit determines that the performance of the mode of offloading the functional module to any one of the accelerators is the expected performance, the processing mode production unit produces a mode of offloading the remaining loop statements in the software program except the functional module to any one of the accelerators, and the performance measurement unit deploys each of the modes in the verification environment to measure performance. When the performance measurement unit determines that the performance of the mode of offloading the functional module to any one of the accelerators is not the expected performance, the processing mode production unit produces a mode of offloading the loop statement of the software program to any one of the accelerators, and the performance measurement unit deploys each of the modes in the verification environment to measure performance. The control unit tests the loop statement as an unloading target to the accelerator after testing the functional module, and the accelerator as the unloading target of the functional module and / or the loop statement is tested in the order of the multi-core CPU, GPU, and FPGA.

2. The unloading server according to claim 1, characterized in that: The accelerators are of various types. The control unit selects a fastest mode among modes for offloading the functional module or the loop statement to any one of the accelerators.

3. The unloading server according to claim 1, characterized in that: The control unit is configured as follows: In the unloading of the functional module or the loop statement, when a mode with a higher processing speed than the original is found for multiple accelerators and the same functional module or loop statement can be unloaded to the multiple accelerators, the accelerator with higher performance is set as the unloading target, When different functional modules or different loop statements can be offloaded to different accelerators, but cannot be offloaded to the accelerator on the same node, the accelerator with higher performance is set as the offload target. When different functional modules or different loop statements can be offloaded to different accelerators and can be offloaded to an accelerator of the same node, the offloading destinations of the functional modules or the loop statements are set to different accelerators.

4. The unloading server according to claim 1, characterized in that: The control unit is configured as follows: In uninstalling the functional module and the loop statement, when the uninstallation target of the loop statement is a node different from the uninstallation target of the functional module, if the performance improvement due to the uninstallation of the loop statement is lower than the performance improvement due to the uninstallation of the functional module, the mode of uninstalling the loop statement is not tried, and the mode of uninstalling the functional module is tried, If the performance improvement brought by the unloading based on the loop statement exceeds the performance improvement brought by the unloading based on the functional module, the mode of unloading the functional module is not tried, and the mode of unloading the loop statement is tried, In the case where the uninstallation target of the loop statement and the uninstallation target of the functional module are the same node, a pattern of uninstalling the functional module and the loop statement is tried.

5. The unloading server according to claim 1, characterized in that: The code analysis unit analyzes whether the source code of the software program contains a loop statement that can be executed by the many-core CPU; The processing mode making unit makes a mode for offloading the loop statement to the multi-core CPU; The performance measurement unit maps each of the loop statements to a gene pattern, deploys each of the patterns that uninstall each of the loop statements in a verification environment to measure performance, sets high performance as high fitness, and repeatedly produces a next generation pattern through elite selection, crossover, and sudden mutation processing of a genetic algorithm, The performance measurement unit compares the calculation result of the multi-core CPU processing with the calculation result of the original processing in the performance measurement in the verification environment, and sets the fitness of the gene model to be low if the error of the calculation result of the multi-core CPU processing exceeds an allowable threshold.

6. An unloading control method, characterized in that: Perform the following steps: The code analysis unit analyzes whether the source code of the software program contains a functional module that can be executed by the accelerator; The processing mode making unit makes a mode for offloading the functional module to any one of the accelerators; The performance measurement unit deploys each of the modes of offloading the functional module to any of the accelerators in a verification environment to measure performance. Also perform the following steps: When the performance measuring unit measures that the performance of the mode of offloading the functional module to any one of the accelerators is the expected performance, the processing mode making unit makes a mode of offloading the remaining loop statements in the software program except the functional module to any one of the accelerators; The performance measurement unit deploys each of the modes in the verification environment to measure performance, Also perform the following steps: When the performance measuring unit measures that the performance of the mode of offloading the functional module to any one of the accelerators is not the expected performance, the processing mode creating unit creates a mode of offloading the loop statement of the software program to any one of the accelerators; The performance measurement unit deploys each of the modes in the verification environment to measure performance, The control unit tests the loop statement as an offload target to the accelerator after testing the functional module, and tests the accelerator as an offload target of the functional module and / or the loop statement in the order of the multi-core CPU, GPU, and FPGA.

7. An uninstallation program, characterized in that: Have your computer perform the following steps: Analyze whether the source code of the software program contains functional modules that can be executed by the accelerator; Creating a mode for offloading the functional module to any one of the accelerators; Deploying each of the modes of offloading the functional modules to any of the accelerators in a verification environment to measure performance; When it is determined that the performance of the mode of offloading the functional module to any one of the accelerators is the expected performance, a mode of offloading the remaining loop statements in the software program except the functional module to any one of the accelerators is created, and each of the modes is deployed in the verification environment to measure the performance; When it is determined that the performance of the mode of offloading the functional module to any one of the accelerators is not the expected performance, creating a mode of offloading the loop statement of the software program to any one of the accelerators, and deploying each of the modes in the verification environment to measure the performance; After trialing the functional module, the loop statement is trialed as an unloading object to the accelerator, and the accelerator as the unloading target of the functional module and / or the loop statement is trialed in the order of the multi-core CPU, GPU, and FPGA.

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