Memory

Abstract

The disclosed embodiment provides a memory, comprising: a bit line extending along a first direction and a word line extending along a second direction; a plurality of storage modules arranged along the first direction; a column selection circuit and a read-write control driving circuit, wherein the column selection circuit and the read-write control driving circuit are both located on the same side of the plurality of storage modules perpendicular to the first direction; a column selection line extending along the first direction and a column connection line extending along a third direction, wherein each column selection line is electrically connected to an amplification unit arranged along the first direction, and the column selection line is electrically connected to the column selection circuit via the column connection line, and the column selection circuit is used to drive the amplification unit electrically connected to the column selection line; a global data line extending along the first direction and a global connection line extending along the third direction, wherein the global data line is electrically connected to the read-write control driving circuit via the global connection line, and the read-write control driving circuit is used to drive the storage module corresponding to the global data line. The disclosed embodiment is conducive to improving the storage performance of the memory.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] Semiconductor memory can be divided into non-volatile memory and volatile memory. As a volatile memory, dynamic random access memory (DRAM) has the advantages of high storage density and fast read and write speed, and is widely used in various electronic systems. As the process technology becomes more and more advanced, the storage performance of memory needs to be further improved. Summary of the invention

[0003] The embodiments of the present disclosure provide a memory, which is at least beneficial to improving the storage performance of the memory.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a memory, comprising: bit lines extending along a first direction and word lines extending along a second direction; a plurality of storage modules arranged along the first direction, the storage modules comprising: a memory array and an amplifier array arranged along the first direction, the memory array comprising at least one storage unit, the amplifier array comprising at least one amplifier unit, each of the bit lines being electrically connected to one end of a corresponding amplifier unit, and each of the word lines being electrically connected to a corresponding storage unit; a column selection circuit and a read-write control drive circuit, the column selection circuit and the read-write control drive circuit being both located on the same side of the plurality of storage modules perpendicular to the first direction; a plurality of storage modules extending along the first direction Column selection lines and column connection lines extending along a third direction, each of the column selection lines is electrically connected to the amplification units arranged along the first direction, and the column selection lines are electrically connected to the column selection circuit via the column connection lines, and the column selection circuit is used to drive the amplification units electrically connected to the column selection lines; global data lines extending along the first direction and global connection lines extending along the third direction, the global data lines are electrically connected to the read-write control driving circuit via the global connection lines, and the read-write control driving circuit is used to drive the storage module corresponding to the global data line, so that data is written into the storage unit via the global data line, or, data is read out from the storage unit and the data is transmitted to the global data line.

[0005] In some embodiments, the column selection circuit and the read / write control driving circuit are arranged along the first direction.

[0006] In some embodiments, each of the column selection lines is electrically connected to a plurality of columns of the amplifying units arranged along the first direction.

[0007] In some embodiments, the column selection circuit includes a plurality of column selection units arranged along the first direction, each of the column selection units being electrically connected to at least two of the column selection lines via the electrical connection line; wherein each of the column selection units is electrically connected to at least two of the column selection lines that are adjacently distributed via the column connection line; or, each of the column selection units is electrically connected to at least two of the column selection lines that are spaced apart from each other via the column connection line.

[0008] In some embodiments, along the first direction, the multiple storage modules are arranged in ascending order of natural numbers, the storage modules at odd positions are defined as first storage modules, and the storage modules at even positions are defined as second storage modules; the global data lines include: a first global data line, the first global data line corresponds to the first storage module; a second global data line, the second global data line corresponds to the second storage module; the global connection lines include: a first global connection line, the first global connection line electrically connects the first global data line and the read-write control drive circuit; a second global connection line, the second global connection line electrically connects the second global data line and the read-write control drive circuit.

[0009] In some embodiments, each of the first global data lines corresponds to all of the first storage modules; and each of the second global data lines corresponds to all of the second storage modules.

[0010] In some embodiments, the number of the first global data lines and the number of the second global data lines are both plural, wherein each of the first global data lines corresponds to a portion of the first storage modules, and each of the second global data lines corresponds to a portion of the second storage modules.

[0011] In some embodiments, the read / write control driving circuit includes: a plurality of read / write control driving units arranged along the first direction, each of the read / write control driving units being electrically connected to at least one of the first global data lines and at least one of the second global data lines.

[0012] In some embodiments, the plurality of storage modules are divided into at least two module areas arranged along the first direction, each module area including at least two storage modules; the column selection circuit includes: at least two column selection modules arranged along the first direction, each column selection module is located on one side of the corresponding module area, and the column selection module is electrically connected to the corresponding column selection line via the column connection line; the read-write control drive circuit includes: at least two read-write control drive modules arranged along the first direction, each read-write control drive module is located on one side of the corresponding module area, and the read-write control drive module is electrically connected to the corresponding global data line via the global connection line.

[0013] In some embodiments, the global data lines of different module areas are independent of each other; or, the global data line corresponds to at least two module areas, and at least a part of the storage modules in at least two module areas connected to the same global data line share the global data line.

[0014] In some embodiments, the column selection circuit is configured such that when the word line corresponding to the module area is enabled, the column selection module corresponding to the module area drives the amplification unit within the module area via the column selection line; the read-write control drive circuit is configured such that when the word line corresponding to the module area is enabled, the read-write control drive circuit corresponding to the module area drives the storage module within the module area via all the global data lines.

[0015] In some embodiments, for the same module area, the number of the column connection lines is the same as the number of the column selection lines, and each of the column connection lines is electrically connected to one of the column selection lines; or, for the same module area, the same column connection line is electrically connected to at least two of the column selection lines.

[0016] In some embodiments, the column selection module includes at least two column selection units arranged along the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the column connection lines.

[0017] In some embodiments, for the same module area, each of the column selection units is electrically connected to at least two adjacently distributed column selection lines via the column connection line; or, for the same module area, each of the column selection units is electrically connected to at least two spaced-apart column selection lines via the column connection line.

[0018] In some embodiments, each of the column selection units is electrically connected to at least two of the column selection lines via the same column connection line; or each of the column selection units is electrically connected to at least two of the column selection lines via different column connection lines.

[0019] In some embodiments, the same module area has a plurality of the global data lines, and the plurality of the global data lines are divided into at least two groups, and each group of the global data lines corresponds to at least two adjacent storage modules.

[0020] In some embodiments, for the same module area, all the global data lines are arranged adjacent to each other, or different groups of global data lines are arranged alternately.

[0021] In some embodiments, for the same module area, the read / write control driving module includes a plurality of read / write control driving units arranged along the first direction, and each of the read / write control driving units is electrically connected to at least one group of the global data lines and global connection lines.

[0022] In some embodiments, the first direction is perpendicular to the third direction; and the second direction is the same as the third direction.

[0023] In some embodiments, it also includes: a row decoding circuit, which is used to select the storage unit electrically connected to the word line through the word line; the row decoding circuit is located on the side of the column selection circuit and the read-write control drive circuit away from the multiple storage modules.

[0024] The technical solution provided by the embodiments of the present disclosure has the following advantages:

[0025] The embodiments of the present disclosure provide a memory with superior structural performance, wherein a plurality of storage modules are arranged along a first direction, a read-write control driving circuit and a column selection circuit are located on the same side of the plurality of storage modules, the arrangement direction of the storage modules and the read-write control driving circuit is different from the first direction, a global data line extends along the first direction, a global connection line extends along a third direction, and the global data line is electrically connected to the read-write control driving circuit via the global connection line, and the read-write control driving circuit is used to drive the storage modules corresponding to the global data lines; a column selection line extends along the first direction, a column connection line extends along the third direction, and the column selection line is electrically connected to the column selection circuit via the column connection line. The position setting of the read / write control driving circuit and the column selection circuit makes the chip layout corresponding to the memory more flexible; in addition, the global data line and the global connection line form a T-shaped structure, and the difference in the signal transmission path required for the read / write control driving circuit to drive the storage modules at the head and the tail is small, which improves the RC delay characteristics driven by the read / write control driving circuit, which is beneficial to improving the read / write speed of the memory; and, the column selection circuit, the column connection line and the column selection line form a T-shaped morphology, and the difference in the signal transmission path required for the column selection circuit to drive the storage modules at the head and the tail is small, which improves the RC delay characteristics driven by the column selection circuit, which is beneficial to improving the read / write speed of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0027] Figure 1 A schematic diagram of the structure of a memory;

[0028] Figure 2 A schematic diagram of the structure of a memory provided in some embodiments of the present disclosure;

[0029] Figure 3 A schematic diagram of the structure of a storage module in a memory provided in some embodiments of the present disclosure;

[0030] Figure 4 A schematic diagram of the circuit structure of an amplifying unit and a storage unit in a memory provided in some embodiments of the present disclosure;

[0031] Figure 5 A schematic diagram of the layout of each data routing line in a memory provided in some embodiments of the present disclosure;

[0032] Figures 6 to 12 Schematic diagrams of different structures of memories provided in embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] Figure 1 This is a schematic diagram of the structure of a memory. Figure 1 The memory includes: a plurality of memory blocks (banks, also called storage bodies) 10, each memory block 10 includes a plurality of memory modules, each memory module (section, also called a section) includes a memory array (array) 11 and a sense amplifier array 12, the memory array 11 includes a plurality of memory cells arranged along the x direction, the sense amplifier array 12 includes a plurality of amplifying units arranged along the x direction, the memory cells and the amplifying units in the same column constitute a section, it can be understood that the columns are defined as the columns along the y direction, and the rows are defined as the rows along the x direction; a read-write control driving circuit 14, a column selection circuit (ydec) 13 and a row decoding circuit 15; a plurality of word lines WL extending along the x direction, each word line WL is connected to the memory array 11 of the corresponding row; a plurality of bit lines BL extending along the y direction, each bit line BL is connected to the memory array 11 of the corresponding column; a column selection line CSL (column select line CSL) extending along the y direction The invention relates to a plurality of memory cells, wherein each column selection line csl is connected to an amplifying unit in a sense amplifier array 12 of a corresponding column; a global data line Gdata extending along the y direction, the global data line is electrically connected to the amplifying unit and is also electrically connected to a read / write control driving circuit 14, the read / write control driving circuit 14 is used to drive a storage module corresponding to the global data line Gdata; a row decoding circuit 15 is used to provide a voltage to a word line WL so that the corresponding word line WL is enabled.

[0034] In the above-mentioned memory, the read-write control driving circuit 14 is located on one side of each storage block 10, and the row decoding circuit 15 is located on the other side of each storage block 10, which has certain restrictions on the size and shape of the chip, affecting the packaging of the chip or the optimization of the production efficiency. In addition, the above-mentioned memory also has the problem that the RC delay of the read-write control driving circuit 14 driving different storage modules is relatively different. Specifically, the storage module closest to the read-write control driving circuit 14 is defined as the first storage module, and the storage module farthest from the read-write control driving circuit 14 is defined as the second storage module. The distance between the connection point of the same global data line Gdata and the first storage module and the connection point with the second storage module is relatively large, which leads to a large difference in the time delay between the read-write control driving circuit driving the first storage module and the second storage module, and the time required for the read-write control driving circuit 14 to drive the second storage module is relatively long, which has an adverse effect on the read-write speed of the memory.

[0035] In addition, the above-mentioned memory also has a problem that the RC delay of different storage modules driven by the column selection circuit 13 is quite different. Specifically, the column selection line CSL provides a column selection signal, defines the storage module closest to the read-write control driving circuit 14 as the first storage module, and defines the storage module farthest from the read-write control driving circuit 14 as the second storage module. The difference between the transmission paths of the column selection signal to the first storage module and the second storage module is quite large, which results in a large time difference between the column selection signal reaching the two storage modules, causing a signal delay problem, and affecting the normal operation of the memory.

[0036] The disclosed embodiment provides a memory, in which a read / write control driving circuit and a column selection circuit are arranged on a side perpendicular to the arrangement direction of multiple storage modules to solve the RC delay problem, make the chip design more flexible, and improve the storage performance of the memory.

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it can be understood by those skilled in the art that in the embodiments of the present disclosure, many technical details are provided in order to enable readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0038] Figure 2 A schematic diagram of the structure of a memory provided in some embodiments of the present disclosure, Figure 3 A schematic diagram of the structure of a storage module in a memory provided in some embodiments of the present disclosure, Figure 4 A schematic diagram of the circuit structure of an amplifying unit and a storage unit in a memory provided in some embodiments of the present disclosure, Figure 5 is a schematic diagram of the layout of each data routing in the memory provided in some embodiments of the present disclosure, Figures 6 to 12 Several structural schematic diagrams of memories provided for some embodiments of the present disclosure.

[0039] refer to Figure 2 and Figure 3A memory provided by an embodiment of the present disclosure includes: a bit line BL extending along a first direction Y and a word line WL extending along a second direction X1; a plurality of storage modules 102 arranged along the first direction Y, the storage module 102 including: a memory array 112 and an amplifier array 122 arranged along the first direction Y, the memory array 112 including at least one storage unit 21, the amplifier array 122 including at least one amplifier unit 22, each bit line BL is electrically connected to one end of the corresponding amplifier unit 22, each word line WL is electrically connected to the corresponding storage unit 21; a column selection circuit 103 and a read-write control driving circuit 101, the column selection circuit 103 and the read-write control driving circuit 101 are both located on the same side of the plurality of storage modules 102 perpendicular to the first direction Y; a column selection line CLS extending along the first direction Y and a Column connection lines CCL extending in the third direction X2, each column selection line CSL is electrically connected to the amplification units 22 arranged along the first direction Y, and the column selection line CSL is electrically connected to the column selection circuit 103 via the column connection line CCL, and the column selection circuit 103 is used to drive the amplification unit 22 electrically connected to the column selection line CSL; global data lines Gdata extending along the first direction Y and global connection lines GGL extending along the third direction X2, the global data lines Gdata are electrically connected to the read-write control driving circuit 101 via the global connection lines GGL, and the read-write control driving circuit 101 is used to drive the storage module 102 corresponding to the global data line Gdata, so that data is written into the storage unit 21 via the global data line Gdata, or, data is read from the storage unit 21 and the data is transmitted to the global data line Gdata.

[0040] It should be noted that Figure 2 Only one bit line BL and one word line WL are shown in the figure. Actually, the memory includes multiple bit lines BL and multiple word lines WL. Figure 3 In the figure, only one bit line BL and one column selection line CSL are shown in one memory cell. Actually, a plurality of bit lines BL and a plurality of column selection lines CSL are connected in one memory cell.

[0041] In the above embodiment, the column selection circuit 103 and the read-write control driving circuit 101 are not arranged in the arrangement direction of the plurality of storage modules 102, so that the shape and size of the storage can be adjusted more flexibly, and the manufacturing efficiency is optimized. In addition, the arrangement direction of the read-write control driving circuit 101 and the storage module 102 is different from the extension direction of the global data line Gdata, so that the signal transmission paths required by the read-write control driving circuit 101 to drive different storage modules 102 are less different, thereby improving the RC delay characteristics, which is conducive to improving the read-write speed. In addition, by using the above memory, different storage modules 102 have the opportunity to be driven by the universal read-write control driving circuit 101 via the global connection line GCL, which is conducive to reducing the structural complexity of the read-write control driving circuit 101, reducing the size of the read-write control driving circuit 101, and saving the chip area of ​​the memory.

[0042] Furthermore, the time difference between the column selection signal transmitted by the same column selection line CSL reaching different amplification units 22 can be shortened, thereby improving the RC delay characteristic, which is beneficial to improving the read and write speed. In addition, with the above-mentioned memory, different column selection lines CSL have the opportunity to transmit the same column selection signal via the column connection line CCL, that is, the column selection circuit 103 does not need to design a separate circuit structure for each column selection line CSL, thereby reducing the structural complexity of the column selection circuit 103, reducing the size of the column selection circuit 103, and saving the chip area of ​​the memory.

[0043] In some embodiments, the memory may be a DRAM memory, such as a DDR (double data rate) 4 DRAM memory, a DDR5 DRAM memory, or a SRAM (Static Random-Access Memory) memory, a NAND memory, a NOR memory, a FeRAM memory, or a PcRAM memory.

[0044] refer to Figure 3 , Figure 3 for Figure 21 is an enlarged schematic diagram of two adjacent storage modules 102, each storage module 102 is called a slice, the memory array 112 may include a plurality of storage cells 21 arranged along the second direction X1, and the amplifier array 122 may include a plurality of amplifying cells 22 arranged along the second direction X1. In some embodiments, each amplifying cell 22 may be electrically connected to a storage cell 21 in the same storage module 102, and is used to amplify the data read out or to be stored in the storage cell 21 during a read operation. In other embodiments, the amplifying unit 22 may also be electrically connected to a storage cell 21 in an adjacent storage module 102, and is used to amplify the data read out or to be stored in the storage cell 21 during a read operation. It can be understood that the embodiments of the present disclosure do not specifically limit the electrical connection correspondence between the storage cells and the amplifying units in the storage module, as long as the amplifying unit can amplify the data to be stored in the storage cell or the data read from the storage cell.

[0045] In some embodiments, the memory cell 21 may be a DRAM memory cell.

[0046] refer to Figure 4 , Figure 4 Schematic diagram of the functional modules of the amplifying unit 22 and the storage unit 21. The amplifying unit 22 is also called the first sense amplifier (FSA). The amplifying unit 22 has a control end, a first end and a second port. The control end is used to be electrically connected to the column selection line CSL to receive the column selection signal, the first end is electrically connected to the bit line BL, and the second end is electrically connected to the local data line Ldata (Local Data Line); the storage unit 21 is electrically connected to the word line WL and the bit line BL. If the word line WL is enabled, the storage unit 21 electrically connected to the word line WL can perform a read operation, and the corresponding storage unit 21 and the bit line BL perform data transmission. Specifically, when the control end receives the column selection signal, the amplifying unit 22 can realize the function of data amplification, and the first end and the second end are conductive, so that data is transmitted between the bit line BL and the local data line Ldata.

[0047] The bit lines BL are electrically connected to the memory cells 21 arranged along the first direction Y in the plurality of memory arrays 112, and the same bit line BL is electrically connected to a column of memory cells 21 arranged along the first direction Y. It can be understood that the bit lines BL can be presented in the form of a bus, and the same bit line BL refers to the same bit line bus.

[0048] The word line WL electrically connects the memory cells 21 arranged along the second direction X1 in the plurality of memory arrays 112, that is, the same word line WL electrically connects a row of memory cells 21 arranged along the second direction X1 in the same memory array 112. It can be understood that the word line WL can be presented in the form of a bus, and the same word line WL refers to the same word line bus.

[0049] The column selection circuit 103 is generally referred to as a YDEC circuit, and is used to provide a column selection signal to the amplifier unit 22 to select the amplifier unit 22, so that data is transmitted between the bit line BL and the local data line Ldata. The column selection line CSL is electrically connected to the column selection circuit 103 via the global connection line GCL, and is used to provide a column selection signal to the control terminal of the corresponding amplifier unit 22 to select the corresponding amplifier unit 22, so that the amplifier unit 22 can realize the functions of data transmission and amplification.

[0050] The global connection line GCL is used to electrically connect the read / write control driving circuit 101 and the global data line Gdata (GlobalData Line) so that the read / write control driving circuit 101 is electrically connected to the corresponding storage module 102. In some embodiments, the third direction X2 can be the same as the second direction X1, that is, the extension direction of the global connection line GCL can be the same as the extension direction of the word line WL, and the first direction Y can be perpendicular to the third direction X2. In this way, the length of the global connection line GCL can be as short as possible, so that the path required for the read / write control driving circuit 101 to drive the storage module 102 is as short as possible, which is conducive to further improving the read / write performance of the memory. At the same time, the length of the column connection line CCL can be as short as possible, so that the transmission path of the column selection signal is as short as possible, which is conducive to further improving the read / write performance of the memory.

[0051] Each storage module 102 arranged along the first direction Y can be defined as a slice. In some embodiments, the read / write control driving circuit 101 can be arranged in the middle position of one side of the plurality of storage modules 102, which is conducive to further shortening the signal transmission time difference required for the read / write control driving circuit 101 to drive the slices at the head and tail ends, so as to further improve the overall performance of the memory.

[0052] As analyzed above, in some embodiments, the memory may further include: local data lines Ldata, each local data line extending along the second direction X1, and the same local data line being electrically connected to the second end of the amplifying unit 22 in the same amplifier array 122. It is understandable that one amplifier array 122 may be connected to a plurality of local data lines Ldata.

[0053] The column selection line CSL is used to conduct multiple bit lines BL and corresponding local data lines Ldata in the same slice. Each slice includes multiple column selection lines CSL, and may also include regular column selection lines CSL and redundant column selection lines CSL. When the memory is working, one column selection line CSL in each slice is selected and turned on.

[0054] In some embodiments, the memory may further include complementary bit lines, and accordingly, the memory may further include: local complementary data lines.

[0055] In some embodiments, reference Figure 3 and Figure 4 , the storage module 102 may also include: a local read-write conversion circuit 132, the local read-write conversion circuit 132 is electrically connected to the second end of the amplification unit 22, specifically, the local read-write conversion circuit 132 is electrically connected to the second end of the amplification unit 22 through a local data line. The local read-write conversion circuit 132 is used to realize data transmission between the local data line and the global data line Gdata. More specifically, the same global data line Gdata can be electrically connected to multiple local read-write conversion circuits 132. The read-write control driving circuit 101 drives the storage module 102, which means that in the write phase, the read-write control driving circuit 101 drives the local read-write conversion circuit 132 corresponding to the storage module 102 to perform data transmission from the local data line to the global data line Gdata, and in the read phase, the read-write control driving circuit 101 drives the local read-write conversion circuit 132 corresponding to the storage module 102 to perform data transmission from the global data line Gdata to the local data line.

[0056] refer to Figure 3 , the local read-write conversion circuit 132 can be arranged on one side of the amplifier array 122, and the local read-write conversion circuit 132 of each storage module 102 is arranged on the same side of the corresponding amplifier array 132, so that the length of the global data line Gdata can be saved, which is conducive to improving the read-write rate. In other embodiments, the local read-write conversion circuit 132 can be arranged in the amplifier array 122, that is, the local read-write conversion circuit 132 is arranged between any adjacent amplifier units 22, and the local read-write conversion circuits 132 of different storage modules 102 are arranged at the same position of the corresponding amplifier array 122. For example, the local read-write conversion circuit 132 of each storage module 102 is arranged between the fifth amplifier unit 22 and the sixth amplifier unit 22, or the local read-write conversion circuit 132 of each storage module 102 is arranged between the tenth amplifier unit 22 and the eleventh amplifier unit 22.

[0057] Reference Figure 5 , Figure 5A schematic diagram of the layout of data routing in a memory provided in an embodiment of the present disclosure, wherein the data routing includes a global data line Gdata, a global connection line GCL, a column selection line CSL, a bit line BL, and a word line WL, wherein the bit line BL, the global data line Gdata, and the column selection line CSL have the same routing direction, and the global connection line GCL and the word line WL have the same routing direction.

[0058] In some embodiments, reference Figure 2 The memory may further include: a row decoding circuit 104, the row decoding circuit 104 is used to select the storage unit 21 electrically connected to the word line WL through the word line WL, so that the storage unit 21 electrically connected to the word line WL performs a read and write operation. Specifically, the row decoding circuit 104 and the read-write control driving circuit 101 may be located on the same side of the multiple storage modules 102, and the row decoding circuit 104 may be located on a side of the column selection circuit 103 and the read-write control driving circuit 101 away from the multiple storage modules 102.

[0059] In some embodiments, the row decoding circuit 104 and the read / write control driving circuit 101 may be located in the same layer of the memory. In other embodiments, the row decoding circuit 104 and the read / write control driving circuit 101 may also be located in different layers of the memory. For example, in the semiconductor structure of the memory, the row decoding circuit 104 and the read / write control driving circuit 101 may be formed by the same semiconductor material layer and / or metal layer, or may be formed by different semiconductor material layers and / or metal layers.

[0060] In some embodiments, the column selection circuit 103 and the read / write control driving circuit 101 may be arranged along the first direction Y. That is, the arrangement direction of the column selection circuit 103 and the read / write control driving circuit 101 may be the same as the arrangement direction of the plurality of storage modules 102, which is beneficial to reduce the size of the memory in a direction perpendicular to the first direction Y.

[0061] In some embodiments, Figure 2 As shown, each column selection line CSL can be electrically connected to multiple columns of amplifying units 22 arranged along the first direction Y. That is, each column selection line CSL is electrically connected to multiple columns of amplifying units 22 arranged along the first direction Y in the same slice, and the number of column selection lines CSL can be the same as the number of slices.

[0062] In some embodiments, reference Figure 6 , Figure 6Schematic diagrams of different structures of the memory provided by the embodiments of the present disclosure, the column selection circuit 103 may include a plurality of column selection units 113 arranged along the first direction Y, and each column selection unit 113 is electrically connected to at least two column selection lines CSL via a column connection line CCL. In this way, a plurality of column selection lines CSL may share a column selection unit 113, and the amplification units 22 connected to the plurality of column selection lines CSL may be driven by the same column selection unit 113, thereby reducing the circuit complexity of the column selection circuit 103 and saving chip area.

[0063] In some embodiments, each column selection unit 113 can be electrically connected to at least two adjacent column selection lines CSL via a column connection line CCL. In this way, the same column selection unit 113 can conduct the bit line BL of the adjacent slice area, so that the amplification unit 22 of the adjacent slice area has an amplification function, and the amplification units 22 of different slice areas can share the column selection unit 113, which is conducive to reducing the number of column selection units 113 and saving chip area. Among them, each column selection unit 113 can be electrically connected to at least two column selection lines CSL via the same column connection line CCL, or each column selection unit 113 can also be electrically connected to at least two column selection lines CSL via different column connection lines CCL.

[0064] In some embodiments, each column selection unit 113 may also be electrically connected to at least two column selection lines CSL that are spaced apart via a column connection line CCL. In this way, the same column selection unit 113 may be used to enable the amplification unit 22 of the spaced apart area, which is not only conducive to reducing the number of decoding units 113 and saving chip area, but also the spaced apart column selection lines CSL are electrically connected to the same column selection unit 113, which is conducive to avoiding the signal interference problem between different column selection lines CSL, and further improving the read and write performance of the memory. Among them, each column selection unit 113 may be electrically connected to at least two column selection lines CSL via the same column connection line CCL, or each column selection unit 113 may also be electrically connected to at least two column selection lines CSL via different column connection lines CCL.

[0065] In the first direction Y, the plurality of storage modules 102 are arranged in ascending order of natural numbers, the storage modules 102 at odd positions are defined as first storage modules, and the storage modules 102 at even positions are defined as second storage modules; the global data lines Gdata include: a first global data line G1, the first global data line G1 corresponds to the first storage module; and a second global data line G2, the second global data line G2 corresponds to the second storage module. Figure 6The global connection line GCL includes: a first global connection line GCL1, the first global connection line GCL1 electrically connects the first global data line G1 and the read / write control driving circuit 101; a second global connection line GCL2, the second global connection line GCL2 electrically connects the second global data line G2 and the read / write control driving circuit 101. The first global data line G1 and the second global data line G2 are independent of each other, and the first global connection line GCL1 and the second global connection line GCL2 are independent of each other; wherein the first global connection line GCL1 and the second global connection line GCL2 both extend along the third direction X2.

[0066] Specifically, in some embodiments, reference Figure 2 Each first global data line G1 can correspond to all first storage modules, and each second global data line G2 can correspond to all second storage modules, that is, the read-write control driving circuit 101 can simultaneously drive all first storage modules through the same first global data line G1, and the read-write control driving circuit 101 can simultaneously drive all second storage modules through the same second global data line G2, which is beneficial to reducing the number of first global data lines 1 and second global data lines G2 and reducing the power consumption of the memory.

[0067] In other embodiments, reference Figure 6 , the number of the first global data line G1 and the second global data line G2 can be multiple, each first global data line G1 corresponds to a part of the number of first storage modules, and each second global data line G2 corresponds to a part of the number of second storage modules, that is, the read-write control driving circuit 101 only needs to drive a part of the number of first storage modules or a part of the number of second storage modules each time, which is beneficial to reduce the load required to be driven by the read-write control driving circuit 101 each time and improve the signal transmission speed. For example, one of the first global data lines G1 is connected to the storage modules 102 arranged in 1, 5, 9, and 13, and one of the second global data lines G2 is connected to the storage modules 102 arranged in 2, 6, 10, and 14; another first global data line G1 is connected to the storage modules 102 arranged in 3, 7, and 11, and another second global data line G2 is connected to the storage modules 102 arranged in 4, 8, and 12.

[0068] In some embodiments, reference Figure 7 The read / write control driving circuit (not shown) may include: a plurality of read / write control driving units 111 arranged along the first direction Y, and each read / write control driving unit 111 is electrically connected to at least one first global data line G1 and at least one second global data line G2 via a global connection line GCL. In this way, different regions can be driven by different read / write control driving units 111, making the driving method of different regions in the memory more flexible.

[0069] In some embodiments, the global data lines Gdata electrically connected to different read / write control driving units 111 are spaced apart. For example, a portion of the global data lines Gdata are distributed at the edges of multiple storage modules 102, and the remaining global data lines Gdata are distributed in the middle area of ​​the multiple storage modules 102. Since different global data lines Gdata are spaced apart, signal interference between different global data lines Gdata can be avoided, which is conducive to further improving the storage performance of the memory.

[0070] It can be understood that, in some embodiments, there may be multiple global data lines Gdata, and all global data lines Gdata may be distributed at the edges of multiple storage modules 102 .

[0071] In addition, the read / write control driving units 111 may be located at both sides of all the column selection units 113 ; or, the read / write control driving units 111 may be alternately arranged with the column selection units 113 .

[0072] In some embodiments, in conjunction with reference Figure 3 , Figures 8 to 12 , Figures 8 to 12 Different structural schematic diagrams of memories provided in some embodiments of the present disclosure, multiple storage modules 102 can be divided into at least two module areas I arranged along a first direction Y, and each module area I includes at least two storage modules 102.

[0073] Accordingly, reference Figure 8 , the column selection circuit 103 may include: at least two column selection modules 130 arranged along the first direction Y, each column selection module 130 is located at one side of the corresponding module area I, and the column selection module 130 is electrically connected to the corresponding column selection line CSL via the column connection line CCL. The read-write control driving circuit 101 may include: at least two read-write control driving modules 110 arranged along the first direction Y, each read-write control driving module 110 is located at one side of the corresponding module area I, and the read-write control driving module 110 is electrically connected to the corresponding global data line Gdata via the global connection line GCL.

[0074] It should be noted that Figures 8 to 12 The amplifier array, storage unit, amplifying unit, word line and bit line are not shown in the figure. Only the memory array is shown in the box. The amplifier array between adjacent memory arrays is not shown. For the arrangement of the amplifier array, storage unit, amplifying unit, word line and bit line, please refer to the above Figures 2 to 7 Refer to the corresponding instructions in .

[0075] Specifically, each module region I may include the same number of storage modules 102. In addition, the memory may be further divided into a high address storage block U and a low address storage block V, and both the high address storage block U and the low address storage block V include multiple storage modules 102.

[0076] The storage cells 21 in different module regions I are connected to different word lines, that is, there is a situation where the word line in one module region I is enabled while the word lines in the other module regions I are not enabled. In this case, since different module regions I have independent global data lines Gdata, the read-write control driving module 110 can only select the global data line Gdata corresponding to the module region I corresponding to the enabled word line WL to drive the storage module 102 of the module region I, and the other module regions I do not need to be driven by the read-write control driving module 110, which can save more power consumption. In addition, compared with the solution in which each global data line is electrically connected to the storage modules of all module regions, each module region I has independent global data lines Gdata, so that the length of each global data line Gdata is reduced, which is conducive to reducing the resistance of the global data line Gdata; and the load on each global data line Gdata is reduced, which is conducive to reducing heat loss and power consumption. It can be understood that the load includes the storage module 102 electrically connected to the global data line Gdata.

[0077] In addition, in this case, since different module regions I have independent column selection lines CSL, only the column selection line CSL corresponding to the module region I corresponding to the enabled word line WL can be selected to transmit the column selection signal, while the column selection lines CSL corresponding to the remaining module regions I may not transmit the column selection signal, which can save more power consumption. Moreover, compared with the solution in which each column selection line is electrically connected to the amplification units of all module regions, each module region I has independent column selection lines CSL, so that the length of each column selection line CSL is reduced, which is conducive to reducing the resistance of the column selection line CSL; and the load on each column selection line CSL is reduced, which is conducive to reducing heat loss and power consumption. It can be understood that the load includes the amplification unit electrically connected to the column selection line CSL.

[0078] like Figure 8 As shown, in some embodiments, the number of module regions I may be 2. Fig.11 As shown, in other embodiments, the number of module areas I may also be 3. It is understandable that the number of module areas I may be reasonably set according to actual conditions, and the embodiment of the present disclosure does not limit the number of module areas I.

[0079] In some embodiments, Figures 8 to 11As shown, the global data lines Gdtata of different module areas I can be independent of each other.

[0080] In some embodiments, Fig.12 , the global data line Gdata corresponds to at least two module regions I, and at least a portion of the storage modules 102 in at least two module regions I connected with the same global data line Gdata share the global data line. For example, the global data line Gdata may correspond to at least two module regions I, and at least a portion of the storage modules 102 in at least two module regions I connected with the same global data line Gdata share the global data line Gdata. In this way, the global data line Gdata may be shared between adjacent module regions I, which is beneficial to reducing the number of global data lines Gdata, and the read / write control driver module 110 may be shared between adjacent module regions I.

[0081] In some embodiments, the column selection circuit 103 can be configured such that when the word line corresponding to the module area is enabled, the column selection module 130 corresponding to the module area I drives the amplification unit 22 in the module area I via the column selection line CSL; the read-write control driving circuit 101 is configured such that when the word line corresponding to the module area is enabled, the read-write control driving circuit 101 corresponding to the module area I drives the storage module in the module area I via the global data line Gdata. As mentioned above, this is conducive to reducing the power consumption of the memory.

[0082] In some embodiments, Figure 8 As shown, for the same module area I, the number of column connection lines CCL is the same as the number of column selection lines CSL, and each column connection line CCL is electrically connected to a column selection line CSL. Figures 9 to 11 For the same module area I, the same column connection line CCL is electrically connected to at least two column selection lines CSL.

[0083] like Figure 8 As shown, the column selection module 130 may include at least two column selection units 113 arranged along the first direction, and each column selection unit 113 is electrically connected to at least two column selection lines CSL via a column connection line CCL. The number of column connection lines CCL is less than the number of column selection lines CSL. In this way, different column selection lines CSL can be electrically connected to the same column connection line CCL, that is, the amplification units in different slices can be driven / enabled by the same column selection signal, which is conducive to reducing the circuit complexity of the corresponding column selection circuit 103 and saving chip area.

[0084] For the same module area I, each column selection unit 113 is electrically connected to at least two adjacently distributed column selection lines CSL via a column connection line CCL. Each column selection unit 113 may also be electrically connected to at least two column selection lines CSL via the same column connection line CCL, wherein the at least two column selection lines CSL are adjacently distributed. It is understandable that each column selection unit 113 may be electrically connected to at least two column selection lines CSL via different column connection lines CCL, wherein the at least two column selection lines CSL are adjacently distributed.

[0085] In other embodiments, Figure 8 , for the same module area I, each column selection unit 113 is electrically connected to at least two column selection lines CSL that are spaced apart via a column connection line CCL. That is to say, each column selection unit 113 can enable the amplification units of the spaced apart slices of the same module area I, so that the spacing between the column selection lines CSL that transmit the same column selection signal can be avoided to be too close, thereby avoiding the problem of signal crosstalk. Specifically, each column selection unit 113 can be electrically connected to at least two column selection lines CSL via different column connection lines CCL, wherein the at least two column selection lines CSL are spaced apart. Each column selection unit 113 can also be electrically connected to at least two column selection lines CSL via the same column connection line CCL, wherein the at least two column selection lines CSL are spaced apart.

[0086] In addition, it can be understood that each column selection unit 113 is electrically connected to at least two column selection lines CSL via the same column connection line CCL; or, each column selection unit 113 can also be electrically connected to at least two column selection lines CSL via different column connection lines CCL.

[0087] refer to Fig.10 and Fig.11 In some embodiments, the same module area I may have multiple global data lines Gdata, and the multiple global data lines Gdata are divided into at least two groups, and each group of global data lines Gdata corresponds to at least two adjacent storage modules 102. The storage modules 102 corresponding to the two groups of global data lines Gdata can be driven by the read-write control driving circuit 101 respectively, so that the driving mode selection of different storage modules 102 is more flexible; in addition, each group of global data lines Gdta corresponds to at least two adjacent storage modules 102, ensuring that adjacent storage modules 102 can be driven simultaneously.

[0088] Specifically, in some embodiments, reference Fig.10 For the same module area I, all global data lines Gdata can be arranged adjacent to each other. In this way, there is no need to consider the layout interference problem between the global data lines Gdata and the column selection lines CSL.

[0089] In other embodiments, reference Fig.11 For the same module area I, different groups of global data lines Gdata can be arranged at intervals. Since different groups of global data lines Gdata are spaced apart from each other, signal interference between different groups of global data lines Gdata can be avoided. It should be noted that, for the convenience of illustration, Fig.11 A group of global data lines Gdata are represented by dashed lines with arrows.

[0090] refer to Fig.10 and Fig.11 In some embodiments, for the same module area I, the read-write control driver module (not shown) may include a plurality of read-write control driver units 111 arranged along the first direction Y, and each read-write control driver unit 111 is electrically connected to at least one group of global data lines Gdata. In this way, different storage modules 102 in the same module area I can be independently driven by different read-write control driver units 111. Moreover, the global data lines Gdata connected to different read-write control driver units 111 may be arranged at intervals, which is beneficial to avoid signal interference between different groups of global data lines Gdata, and further improve the storage performance of the memory. It should be noted that Fig.10 Only two module areas I are illustrated in the figure, and the embodiment of the present disclosure does not limit the number of module areas I, and the number of module areas I can be 3, 4 or even more.

[0091] In addition, for the same module area I, the column selection units 113 and the read / write control driving units 111 may be alternately arranged at intervals, so that the layout of the column selection lines CLS and the global data lines Gdata may be more flexible.

[0092] The disclosed embodiment provides a memory with superior structural performance. The column selection circuit 103 and the read-write control driving circuit 101 are arranged on one side of the plurality of storage modules 102, and the column selection circuit 103 and the read-write control driving circuit 101 are not arranged in the arrangement direction of the plurality of storage modules 102, so that the chip design of the memory is more flexible, which is conducive to saving chip area; the global data line Gdata, the global connection line GCL and the read-write control driving circuit 101 form a T-shaped morphology, which shortens the time required for the column selection signal to be transmitted to the amplifying unit 22 far away from the read-write control driving circuit 101, which is conducive to improving the RC delay problem and improving the read-write performance of the memory. In addition, the column selection circuit 103, the column selection line CSL and the column connection line CCL form a T-shaped performance, which is conducive to shortening the time required for the column selection signal to be transmitted to the amplifying unit 22 far away from the read-write control driving circuit 101, which is conducive to improving the RC delay problem and improving the read-write performance of the memory.

[0093] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A memory, It is characterized in that include: bit lines extending along a first direction and word lines extending along a second direction; A plurality of memory modules arranged along the first direction, the memory modules comprising: a memory array and an amplifier array arranged along the first direction, the memory array comprising at least one memory cell, the amplifier array comprising at least one amplifier cell, each of the bit lines being electrically connected to one end of a corresponding amplifier cell, and each of the word lines being electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module areas arranged along the first direction, each of the module areas comprising at least two memory modules; A column selection circuit and a read-write control driving circuit, wherein the column selection circuit and the read-write control driving circuit are both located on the same side of the plurality of storage modules perpendicular to the first direction; A column selection line extending along the first direction and a column connection line extending along a third direction, each of the column selection lines being electrically connected to the amplification units arranged along the first direction, and the column selection line being electrically connected to the column selection circuit via the column connection line, the column selection circuit being used to drive the amplification units electrically connected to the column selection line; A global data line extending along the first direction and a global connection line extending along the third direction, the global data line being electrically connected to the read / write control driving circuit via the global connection line, the read / write control driving circuit being used to drive the storage module corresponding to the global data line so that data is written into the storage unit via the global data line, or so that data is read out from the storage unit and the data is transmitted to the global data line; The column selection circuit comprises: at least two column selection modules arranged along the first direction, each of the column selection modules is located at one side of the corresponding module area, and the column selection module is electrically connected to the corresponding column selection line via the column connection line; The read-write control driving circuit comprises: at least two read-write control driving modules arranged along the first direction, each of the read-write control driving modules is located at one side of the corresponding module area, and the read-write control driving module is electrically connected to the corresponding global data line via the global connection line; The global data lines in different module areas are independent of each other; or, the global data line corresponds to at least two module areas, and at least part of the storage modules in at least two module areas connected to the same global data line share the global data line.

2. The memory according to claim 1, It is characterized in that The column selection circuit and the read / write control driving circuit are arranged along the first direction.

3. The memory according to claim 1, It is characterized in that Each of the column selection lines is electrically connected to a plurality of columns of the amplifying units arranged along the first direction.

4. The memory as claimed in claim 3, It is characterized in that The column selection circuit includes a plurality of column selection units arranged along the first direction, each of the column selection units being electrically connected to at least two of the column selection lines via an electrical connection line; wherein each of the column selection units is electrically connected to at least two of the column selection lines that are adjacently distributed via the column connection line; or, each of the column selection units is electrically connected to at least two of the column selection lines that are spaced apart from each other via the column connection line.

5. The memory according to claim 1, It is characterized in that Along the first direction, the plurality of storage modules are arranged in ascending order of natural numbers, the storage modules at odd positions are defined as first storage modules, and the storage modules at even positions are defined as second storage modules; the global data lines include: a first global data line, the first global data line corresponding to the first storage module; a second global data line, the second global data line corresponding to the second storage module; The global connection line includes: A first global connection line, the first global connection line electrically connecting the first global data line and the read-write control driving circuit; A second global connection line is provided, wherein the second global connection line is electrically connected to the second global data line and the read / write control driving circuit.

6. The memory as claimed in claim 5, It is characterized in that Each of the first global data lines corresponds to all of the first storage modules; and each of the second global data lines corresponds to all of the second storage modules.

7. The memory according to claim 5, It is characterized in that There are multiple first global data lines and multiple second global data lines, wherein each of the first global data lines corresponds to a portion of the first storage modules, and each of the second global data lines corresponds to a portion of the second storage modules.

8. The memory as claimed in claim 7, It is characterized in that The read-write control driving circuit comprises: A plurality of read / write control driving units are arranged along the first direction, and each of the read / write control driving units is electrically connected to at least one of the first global data lines and at least one of the second global data lines.

9. A memory, It is characterized in that include: bit lines extending along a first direction and word lines extending along a second direction; A plurality of memory modules arranged along the first direction, the memory modules comprising: a memory array and an amplifier array arranged along the first direction, the memory array comprising at least one memory cell, the amplifier array comprising at least one amplifier cell, each of the bit lines being electrically connected to one end of a corresponding amplifier cell, and each of the word lines being electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module areas arranged along the first direction, each of the module areas comprising at least two memory modules; A column selection circuit and a read-write control driving circuit, wherein the column selection circuit and the read-write control driving circuit are both located on the same side of the plurality of storage modules perpendicular to the first direction; A column selection line extending along the first direction and a column connection line extending along a third direction, each of the column selection lines being electrically connected to the amplification units arranged along the first direction, and the column selection line being electrically connected to the column selection circuit via the column connection line, the column selection circuit being used to drive the amplification units electrically connected to the column selection line; A global data line extending along the first direction and a global connection line extending along the third direction, the global data line being electrically connected to the read / write control driving circuit via the global connection line, the read / write control driving circuit being used to drive the storage module corresponding to the global data line so that data is written into the storage unit via the global data line, or so that data is read out from the storage unit and the data is transmitted to the global data line; The column selection circuit comprises: at least two column selection modules arranged along the first direction, each of the column selection modules is located at one side of the corresponding module area, and the column selection module is electrically connected to the corresponding column selection line via the column connection line; The read-write control driving circuit comprises: at least two read-write control driving modules arranged along the first direction, each of the read-write control driving modules is located at one side of the corresponding module area, and the read-write control driving module is electrically connected to the corresponding global data line via the global connection line; The column selection circuit is configured such that when the word line corresponding to the module area is enabled, the column selection module corresponding to the module area drives the amplification unit within the module area via the column selection line; the read-write control drive circuit is configured such that when the word line corresponding to the module area is enabled, the read-write control drive circuit corresponding to the module area drives the storage module within the module area via all the global data lines.

10. A memory, It is characterized in that include: bit lines extending along a first direction and word lines extending along a second direction; A plurality of memory modules arranged along the first direction, the memory modules comprising: a memory array and an amplifier array arranged along the first direction, the memory array comprising at least one memory cell, the amplifier array comprising at least one amplifier cell, each of the bit lines being electrically connected to one end of a corresponding amplifier cell, and each of the word lines being electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module areas arranged along the first direction, each of the module areas comprising at least two memory modules; A column selection circuit and a read-write control driving circuit, wherein the column selection circuit and the read-write control driving circuit are both located on the same side of the plurality of storage modules perpendicular to the first direction; A column selection line extending along the first direction and a column connection line extending along a third direction, each of the column selection lines being electrically connected to the amplification units arranged along the first direction, and the column selection line being electrically connected to the column selection circuit via the column connection line, the column selection circuit being used to drive the amplification units electrically connected to the column selection line; A global data line extending along the first direction and a global connection line extending along the third direction, the global data line being electrically connected to the read / write control driving circuit via the global connection line, the read / write control driving circuit being used to drive the storage module corresponding to the global data line so that data is written into the storage unit via the global data line, or so that data is read out from the storage unit and the data is transmitted to the global data line; The column selection circuit comprises: at least two column selection modules arranged along the first direction, each of the column selection modules is located at one side of the corresponding module area, and the column selection module is electrically connected to the corresponding column selection line via the column connection line; The read-write control driving circuit comprises: at least two read-write control driving modules arranged along the first direction, each of the read-write control driving modules is located at one side of the corresponding module area, and the read-write control driving module is electrically connected to the corresponding global data line via the global connection line; For the same module area, the number of the column connection lines is the same as the number of the column selection lines, and each of the column connection lines is electrically connected to one column selection line; or, for the same module area, the same column connection line is electrically connected to at least two column selection lines.

11. A memory, It is characterized in that include: bit lines extending along a first direction and word lines extending along a second direction; A plurality of memory modules arranged along the first direction, the memory modules comprising: a memory array and an amplifier array arranged along the first direction, the memory array comprising at least one memory cell, the amplifier array comprising at least one amplifier cell, each of the bit lines being electrically connected to one end of a corresponding amplifier cell, and each of the word lines being electrically connected to a corresponding memory cell, wherein the plurality of memory modules are divided into at least two module areas arranged along the first direction, each of the module areas comprising at least two memory modules; A column selection circuit and a read-write control driving circuit, wherein the column selection circuit and the read-write control driving circuit are both located on the same side of the plurality of storage modules perpendicular to the first direction; A column selection line extending along the first direction and a column connection line extending along a third direction, each of the column selection lines being electrically connected to the amplification units arranged along the first direction, and the column selection line being electrically connected to the column selection circuit via the column connection line, the column selection circuit being used to drive the amplification units electrically connected to the column selection line; A global data line extending along the first direction and a global connection line extending along the third direction, the global data line being electrically connected to the read / write control driving circuit via the global connection line, the read / write control driving circuit being used to drive the storage module corresponding to the global data line so that data is written into the storage unit via the global data line, or so that data is read out from the storage unit and the data is transmitted to the global data line; The column selection circuit comprises: at least two column selection modules arranged along the first direction, each of the column selection modules is located at one side of the corresponding module area, and the column selection module is electrically connected to the corresponding column selection line via the column connection line; The read-write control driving circuit comprises: at least two read-write control driving modules arranged along the first direction, each of the read-write control driving modules is located at one side of the corresponding module area, and the read-write control driving module is electrically connected to the corresponding global data line via the global connection line; The column selection module includes at least two column selection units arranged along the first direction, and each of the column selection units is electrically connected to at least two of the column selection lines via the column connection lines.

12. The memory according to claim 11, It is characterized in that For the same module area, each of the column selection units is electrically connected to at least two adjacently distributed column selection lines via the column connection line; or, for the same module area, each of the column selection units is electrically connected to at least two alternately distributed column selection lines via the column connection line.

13. The memory according to claim 11, It is characterized in that Each of the column selection units is electrically connected to at least two of the column selection lines via the same column connection line; or each of the column selection units is electrically connected to at least two of the column selection lines via different column connection lines.

14. The memory as claimed in claim 1 or 9 or 10 or 11, It is characterized in that The same module area has a plurality of the global data lines, and the plurality of the global data lines are divided into at least two groups, and each group of the global data lines corresponds to at least two adjacent storage modules.

15. The memory as claimed in claim 14, It is characterized in that For the same module area, all the global data lines are arranged adjacent to each other, or different groups of global data lines are arranged alternately.

16. The memory as claimed in claim 1 or 9 or 10 or 11, It is characterized in that For the same module area, the read / write control driving module includes a plurality of read / write control driving units arranged along the first direction, and each of the read / write control driving units is electrically connected to at least one group of the global data lines and global connection lines.

17. The memory according to claim 1 or 9 or 10 or 11, It is characterized in that The first direction is perpendicular to the third direction; the second direction is the same as the third direction.

18. The memory according to claim 1 or 9 or 10 or 11, It is characterized in that Also includes: A row decoding circuit is used to select the storage unit electrically connected to the word line through the word line; the row decoding circuit is located on a side of the column selection circuit and the read-write control drive circuit away from the plurality of storage modules.

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