Modeling Method, System, Storage Medium and Electronic Device for State Syntax Module in RTL

Abstract

The present disclosure relates to a modeling method, a modeling system, a storage medium, and an electronic device for a state syntax module in RTL. The modeling method for the state syntax module in RTL analyzes and obtains each state syntax module in each Module module in the RTL file layer by layer; analyzes the interconnection relationship of the state syntax module within the Module module to obtain the corresponding input and output ports of the state syntax module; remodels the state syntax module according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard; reconstructs the Module module into a logic expression module and instantiates it at the internal position of the Module module where the state syntax module is located; adds input and output ports and internal wire networks connected to the input and output ports to the logic expression module according to the interconnection relationship of the state syntax module within the Module module, and obtains a model file with a main hierarchical tree structure containing only the Module module and the logic expression module, which can improve the processing efficiency and correctness of EDA software.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and particularly relates to a modeling method, system, storage medium and electronic device for a state syntax module in RTL. Background Art

[0002] With the continuous development of the digital integrated circuit design field, its design methods and design approaches have gradually shown diversity, and at the same time, the demand for EDA (electronic design automation) software has also been gradually increasing. Since the hardware description language design is a hierarchical design method and the design patterns are gradually enriched, in addition to common basic core modules such as Module (a main hierarchical expression module for describing hardware design), Instance (a logical expression module for describing the internal nested inclusion relationship of a module), Port (an interface description for reflecting the external input and output of a module), wire (a description for reflecting the internal logic signal transmission of a module), etc., more state syntax modules will be introduced, such as the Always statement block module. This syntax module is used to manage logic asynchronously based on a clock in hardware design descriptions. Therefore, it is used more frequently in more complex digital integrated circuit designs, and there are various nested patterns for different grammars in the Always module. However, when current EDA tools process state syntax modules, whether it is for digital integrated circuit synthesis or digital integrated circuit simulation, current EDA tools reduce the RTL-level hardware description language design to the gate-level description by a refinement method or directly map it to a netlist structure for processing, rather than being able to process it directly at the RTL-level hardware description language level. The main reason is that in traditional methods, when processing state syntax modules, special state syntax modules cannot be directly processed in the RTL-level description. It is necessary to refine the RTL-level module or map it to a netlist to convert it into another expression and then process it, resulting in low processing efficiency. Summary of the Invention

[0003] The present invention overcomes one of the deficiencies of the prior art and provides a modeling method, system, storage medium and electronic device for a state syntax module in RTL, which can correctly model the state syntax module (Statement block) in the RTL-level hardware description language design as a Module module and instantiate it to the correct position in the design, thereby improving the processing efficiency and correctness of EDA software.

[0004] According to one aspect of the present disclosure, a modeling method for a state syntax module in RTL is proposed. The method includes:

[0005] Analyze and obtain each state syntax module in each Module module in the RTL file layer by layer;

[0006] Analyze the interconnection relationship of the state grammar module within the Module module to obtain the input and output ports corresponding to the state grammar module;

[0007] Re - model the state grammar module according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard;

[0008] Re - construct the Module module that conforms to the hardware description language standard into a logic expression module, and instantiate the logic expression module to the internal position of the Module module where the state grammar module is located;

[0009] Add input and output ports to the logic expression module according to the interconnection relationship of the state grammar module within the Module module, and internal wire networks connected to the input and output ports, to obtain a model file of the main hierarchical tree structure that only contains the Module module and the logic expression module.

[0010] In a possible implementation, analyze and obtain the state grammar module in each Module module in the RTL file layer by layer, including:

[0011] Use a parser to parse the syntax tree memory structure in the RTL file;

[0012] Use an iterative traversal method to analyze layer by layer from each Module module in the syntax tree memory structure to obtain pointers to each Module module;

[0013] Obtain the content of each Module module according to the pointer of each Module module;

[0014] When it is determined that the content of the Module module is a state grammar module, obtain the pointer to the state grammar module and the structure of the state grammar module.

[0015] In a possible implementation, analyze the interconnection relationship of the state grammar module within the Module module to obtain the input and output ports corresponding to the state grammar module, including:

[0016] Analyze the interconnection signals of the state grammar module within the Module module and trace the driving direction of the interconnection signals;

[0017] Obtain the interconnection relationship between the state grammar module and other modules within the Module module according to the driving direction;

[0018] Obtain the input and output ports corresponding to the state grammar module according to the interconnection relationship.

[0019] In a possible implementation, trace the driving direction of the interconnection signals, including:

[0020] Trace the input and output of the interconnected signal according to the interconnected signal of the state grammar module to obtain the driving direction of the interconnected signal.

[0021] In a possible implementation, the syntax tree memory structure is used to store the logical relationship, logical hierarchy, and syntax expression of the hardware integrated circuit design in the RTL file.

[0022] In a possible implementation, use the iterative traversal method to analyze each Module module in the syntax tree memory structure layer by layer to obtain pointers to each Module module, including:

[0023] Starting from each Module module in the syntax tree memory structure using the iterative traversal method, with each logical expression module as a branch, analyze the leaf nodes of each node in the syntax tree memory structure layer by layer;

[0024] Reconstruct a new hierarchical structure tree based on the leaf nodes of each node, and obtain pointers to each Module module according to the hierarchical structure tree.

[0025] In a possible implementation, reconstruct the Module module that conforms to the hardware description language standard into a logical expression module, including:

[0026] Perform addition, subtraction, multiplication, division, AND, OR, and NOT analysis on the logical symbols of the Module module that conforms to the hardware description language standard, and reconstruct the Module module into a logical expression module.

[0027] According to another aspect of the present disclosure, a modeling system for the state grammar module in RTL is proposed. The system includes:

[0028] A traversal module for analyzing and obtaining the state grammar module in each Module module in the RTL file layer by layer;

[0029] An analysis module for analyzing the interconnection relationship of the state grammar module within the Module module to obtain the input and output ports corresponding to the state grammar module;

[0030] A reconstruction module for re-modeling the state grammar module according to the interconnection relationship and driving direction to obtain a Module module that conforms to the hardware description language standard;

[0031] A refactoring module for refactoring the Module module that conforms to the hardware description language standard into a logical expression module and instantiating the logical expression module to the internal position of the Module module where the state grammar module is located;

[0032] An output module, configured to add input and output ports to a logic expression module according to the interconnection relationship of a state syntax module within a Module module, and internal wire networks connected to the input and output ports, and output a model file only including the main hierarchical tree structure of the Module module and the logic expression module.

[0033] According to another aspect of the present disclosure, there is provided a storage medium having a computer program stored thereon, and when the program is run by a processor, the method described above is implemented.

[0034] According to another aspect of the present disclosure, there is provided an electronic device, including: a processor and a memory storing a computer program, and the processor is configured to implement the method described above when running the computer program.

[0035] The modeling method for a state syntax module in RTL of the present disclosure analyzes and obtains each state syntax module in each Module module in the RTL file layer by layer; analyzes the interconnection relationship of the state syntax module within the Module module to obtain the corresponding input and output ports of the state syntax module; remodels the state syntax module according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard; reconstructs the Module module that conforms to the hardware description language standard into a logic expression module, and instantiates the logic expression module to an internal position of the Module module where the state syntax module is located; adds input and output ports to the logic expression module according to the interconnection relationship of the state syntax module within the Module module, and internal wire networks connected to the input and output ports, to obtain a model file only including the main hierarchical tree structure of the Module module and the logic expression module. It can correctly model the state syntax module (Statement block) in the RTL-level hardware description language design as a Module module and instantiate it to the correct position in the design, thereby improving the processing efficiency and correctness of EDA software.

[0036] Some other optional features and technical effects of the embodiments of the present invention are described below and some can be understood by reading this article. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The elements shown are not limited by the scale shown in the drawings. The same or similar reference numerals in the drawings denote the same or similar elements, where:

[0038] Figure 1 Shows a flowchart of a modeling method for a state syntax module in RTL according to an embodiment of the present disclosure;

[0039] Figure 2 Shows a schematic diagram of the data structure of a hierarchical tree according to an embodiment of the present disclosure;

[0040] Figure 3 Shows a parsing schematic diagram of a state syntax module according to an embodiment of the present disclosure;

[0041] Figure 4 Shows a statement syntax schematic diagram of a state syntax module according to an embodiment of the present disclosure;

[0042] Figure 5 Shows a schematic diagram of a modeling system for a state syntax module in RTL according to an embodiment of the present disclosure;

[0043] Figure 6 Shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0044] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the detailed implementation manners and the accompanying drawings. Herein, the illustrative implementation manners of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.

[0045] The term "including" and its variants used herein represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0046] In addition, the steps shown in the flowchart of the accompanying drawings can be executed in a computer such as a set of computer-executable instructions. And, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0047] Figure 1 Shows a flowchart of a modeling method for a state syntax module in RTL according to an embodiment of the present disclosure. As Figure 1 shown, the method may include:

[0048] Step S1: Analyze and obtain the state syntax module in each Module module in the RTL file layer by layer.

[0049] Among them, the RTL (Register Transfer Level) file can describe the HDL level of the circuit by describing the logical function between registers. The RTL file is mainly a hardware description language design file, and the main hardware description languages used are Verilog and System Verilog. According to the hierarchical design structure of the hardware description languages Verilog and System Verilog, each Module module under the entire hierarchical design can be analyzed layer by layer, and the statement block corresponding to each main hierarchical expression module (Module module) can be obtained.

[0050] In one example, analyzing each Module module in the RTL file layer by layer and obtaining the statement block in it may include:

[0051] Using a parser to parse the memory structure of the syntax tree in the RTL file and saving the memory structure of the syntax tree to the memory of the computer. Among them, the memory structure of the syntax tree is used to store the logical relationship, logical level and syntax expression of the hardware integrated circuit design in the RTL file.

[0052] Using an iterative traversal method to analyze layer by layer from each Module module of the memory structure of the syntax tree to obtain a pointer pointing to each Module module.

[0053] In one example, this step can be: starting from each Module module of the memory structure of the syntax tree by using an iterative traversal method, taking each logical expression module (Instance) as a branch, and using a recursive traversal method to analyze the leaf nodes of each node of the memory structure of the syntax tree layer by layer; while traversing, process the memory structure of the syntax tree saved in the memory of the computer, reconstruct a new hierarchy tree according to the leaf nodes of each node of the memory structure of the syntax tree, and obtain a pointer pointing to each Module module according to the hierarchy tree. Ensure the design correctness by the principle of constructing the data structure of the hierarchy tree.

[0054] Figure 2 Shows a schematic diagram of the data structure of the hierarchy tree according to an embodiment of the present disclosure.

[0055] Such as Figure 2As shown in the figure, there are mainly Module pointers, Instance pointers, Module Item pointers, Parent pointers, and child pointers in the Hierarchy Tree data structure. Among them, the Module pointer is used to point to the current Module module, the Instance pointer is used to point to the Instance contained in the current Module, the Module Item pointer is used to point to the Block structure other than the Module, the Parent pointer is used to point to the parent Module that instantiates the current Module module, and the child pointer is used to point to the Module pointer and the callback function pointer of the Inst contained in the current Module for use when executing the callback algorithm during the traversal process. The Hierarchy Tree data structure can be used as the data basis for subsequent syntax processing operations.

[0056] Obtain the content of each Module module according to the pointer of each Module module; when it is determined that the content of the Module module is a state syntax module, obtain the pointer to the state syntax module and the structure of the state syntax module.

[0057] For example, as Figure 2 shown in the figure, obtain the pointers of each Module module in the entire hierarchical design through recursive traversal, and then obtain the content (Module Item) of all the main hierarchical expression modules in the Module pointed to by the pointer of the Module module. By judging the content (Module Item) of the main hierarchical expression module, if the content (Module Item) of the main hierarchical expression module pointed to by the current Module pointer is a state syntax module (statementblock), then obtain the pointers and structures of all the state syntax modules (statement block) under the main hierarchical expression module Module.

[0058] Through this step, the state syntax module (statement block) corresponding to each main hierarchical expression module Module under the entire hierarchical design can be obtained.

[0059] Step S2: Analyze the interconnection relationship of the state syntax module within the Module module to obtain the input and output ports corresponding to the state syntax module.

[0060] In one example, this step may include: analyzing the interconnection signals of the state grammar module within the Module module and tracing the driving direction of the interconnection signals. For example, the driving direction of the interconnection signals can be obtained by tracing the input and output of the interconnection signals based on the interconnection signals of the state grammar module. Obtain the interconnection relationship between the state grammar module and other modules within the Module module according to the driving direction; obtain the corresponding input and output ports of the state grammar module according to the interconnection relationship.

[0061] For example, for different state grammar modules (statement blocks), analyze the composition grammar of the state grammar module (statement block), as well as the interconnection signals used by the current grammar block within its parent Module, and trace the driving direction of the interconnection signals, so as to obtain the interconnection relationship between the Module where the state grammar module (statement block) is located and other modules, and then extract the corresponding input and output ports. At the same time, special grammars are processed, such as complex expressions, check statements, state machine statements, interface body statements, Class class statements, register type wire network structures, etc.

[0062] Step S3: Remodel the state grammar module according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard.

[0063] For example, through the remodeling of the analyzed state grammar module (statement block) obtained in Step S2, the state grammar module (statement block) is a reasonable Module module that satisfies the Verilog grammar definition, that is, a Module module that conforms to the IEEE Verilog grammar definition standard and does not violate the grammar semantics and grammar standard.

[0064] Step S4: Reconstruct the Module module that conforms to the hardware description language standard into a logic expression module, and instantiate the logic expression module to the internal position of the Module module where the state grammar module is located. Among them, the Module module that conforms to the hardware description language standard can be reconstructed into a logic expression module by performing addition, subtraction, multiplication, division, AND, OR, and NOT analysis on the logic symbols of the Module module.

[0065] Step S5: Add input and output ports to the logic expression module according to the interconnection relationship of the state grammar module within the Module module, and internal wires connected to the input and output ports to obtain a model file of the main hierarchical tree structure that only contains the Module module and the logic expression module.

[0066] For example, as Figure 2As shown, the type of the statement block is parsed to determine whether it is a multi-timing logic grammar module (always statement) or a continuous assignment grammar module (assign statement). Then, the interconnection relationship of the statement block is further analyzed to determine the input / output interconnection of the statement block, based on the wire interconnection relationship within the parent main hierarchical expression module Module where the current statement block is located. Among them, this interconnection relationship is mainly obtained by traversing the Module pointer pointed to in the data structure of the hierarchy tree (such as Figure 2 as shown), obtaining the Net interconnection relationship, input and output, etc. within the current Module module, analyzing the specific logical expressions in the current statement block, and performing split analysis on logical symbols such as addition, subtraction, multiplication, division, AND, OR, and NOT, so as to obtain the input / output signals inside the current statement block. According to the interconnection relationship and input / output signals of the statement block, a Module module that conforms to the hardware description language standard is recreated, the input / output signals are added to the Module module that conforms to the hardware description language standard, and the original statement block is copied into the Module module that conforms to the hardware description language standard, further checking the interconnection relationship and ensuring the correctness of the currently constructed Module module that conforms to the hardware description language standard. At the same time, the Module module that conforms to the hardware description language standard is instantiated as a new logic expression module (Instance) below the original statement block.

[0067] During the process of analyzing the statement block, there may be various grammars, such as: multi-timing logic grammar module (Always block), continuous assignment grammar module (Assign block), initialization module (Initial block), function module (Function block), system function module (System Function block), type enumeration module (Typedef enum block), etc.

[0068] The following takes the state syntax module in Module A as an example to illustrate the modeling method for the state syntax module in RTL in the present disclosure.

[0069] Figure 3 Fig. shows a parsing schematic diagram of a state syntax module according to an embodiment of the present disclosure; Figure 4 Fig. shows a statement syntax schematic diagram of a state syntax module according to an embodiment of the present disclosure.

[0070] As Figure 3 shown, first, obtain the pointer of Module A through the Hierarchy Tree data structure. By analyzing the content (Module Item) of the main hierarchical expression module pointed to by the Module A pointer, when it is determined that the content (Module Item) of the current main hierarchical expression module is a statement block (state syntax module), all statement blocks (state syntax modules) can be obtained by judging the statement block (state syntax module) pointer. At the same time, further analyze the statement block syntax type of the statement block (state syntax module) and the expression information in the syntax statement block. The specific content is as Figure 4 shown.

[0071] Obtain the interconnection information in the current statement block (state syntax module) by analyzing the expression information in the syntax statement block, that is, the input and output in each expression. By constructing a new Module module that conforms to the hardware description language standard, and adding the input and output of the statement block (state syntax module) obtained in the above process as ports at the ports of the Module module that conforms to the hardware description language standard. Finally, re-instantiate the Module module that conforms to the hardware description language standard to the internal position of the Module module where the statement block (state syntax module) is located, so as to achieve that there is no other syntax logic block in Module A except the logical expression statement block (Instance).

[0072] The modeling method for the state syntax module in RTL in the present invention makes the hierarchical structure of the original input more reasonable by modeling the hardware description language at the RTL level for the state syntax module (statement block). That is, the entire design from the top layer down consists of basic Module modules, Instance modules, Ports, Wires, etc. The state statement module will not be directly reflected in the original design hierarchical structure. Thus, when performing subsequent segmentation, only the logical expression module (Instance) needs to be considered for segmentation, without considering the complex state syntax module, thereby providing convenience in operation. At the same time, it will also effectively improve the execution efficiency during simulation. Also, based on the design after modeling the state syntax module (statement block), due to its advantages of clear structure and simple syntax, it will provide convenience for secondary development. For example, when abstracting the design into a hypergraph structure or a tree structure, the efficiency will be greatly improved, and the memory occupied and processing complexity will be reduced, thereby improving the processing efficiency and correctness of the EDA software.

[0073] The following is the system embodiment of this application, which can be used to execute the method embodiment of this application. For details not disclosed in the system embodiment of this application, please refer to the method embodiment of this application.

[0074] Figure 5 The schematic diagram of the modeling system for the state syntax module in RTL according to an embodiment of the present disclosure is shown as Figure 5 shown, and the system may include:

[0075] A traversal module 501, configured to analyze and obtain the state syntax module in each Module module in the RTL file layer by layer;

[0076] An analysis module 502, configured to analyze the interconnection relationship of the state syntax module within the Module module to obtain the input and output ports corresponding to the state syntax module;

[0077] A reconstruction module 503, configured to re - model the state syntax module according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard;

[0078] A refactoring module 504, configured to refactor the Module module that conforms to the hardware description language standard into a logical expression module and instantiate the logical expression module to the internal position of the Module module where the state syntax module is located;

[0079] An output module 505 is configured to add input and output ports to a logic expression module according to the interconnection relationship of the state syntax module within the Module module, and internal wire networks connected to the input and output ports, and output a model file that only includes the main hierarchical tree structure of the Module module and the logic expression module.

[0080] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0081] In an embodiment of the present invention, an electronic device is provided, including: a processor and a memory storing a computer program, and the processor is configured to execute the method for optimizing the area power consumption of a very large scale integrated circuit according to any embodiment of the present invention when running the computer program.

[0082] Figure 6 FIG. shows a schematic diagram of an electronic device 1000 that can implement the method of the embodiments of the present invention or implement the embodiments of the present invention. In some embodiments, it may include more or fewer electronic devices than shown in the figure. In some embodiments, it can be implemented using a single or multiple electronic devices. In some embodiments, it can be implemented using cloud or distributed electronic devices.

[0083] Figure 6 It is a schematic structural diagram of an electronic device 10 provided by an embodiment of the present application. As Figure 6 shown, the electronic device 1000 includes a processor 1001, which can perform various appropriate operations and processes according to the programs and / or data stored in the read-only memory (ROM) 1002 and / or the programs and / or data loaded from the storage section 1008 into the random access memory (RAM) 1003. The processor 1001 can be a multi-core processor or include multiple processors. In some embodiments, the processor 1001 can include a general main processor and one or more special coprocessors, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a digital signal processing unit (DSP), and so on. In the RAM 1003, various programs and data required for the operation of the electronic device 1000 are also stored. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other through a bus 1004. The input / output (I / O) interface 1005 is also connected to the bus 1004.

[0084] The above-mentioned processor and memory are jointly used to execute the program stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.

[0085] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, a touch screen, etc.; an output section 1007 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 1010 as needed so that a computer program read from it can be installed into the storage section 1008 as needed. Figure 6 Only some components are schematically shown, and it does not mean that the computer system 1000 only includes Figure 6 the components shown.

[0086] The systems, devices, modules or units illustrated in the above embodiments can be implemented by a computer or its associated components. The computer can be, for example, a mobile terminal, a smart phone, a personal computer, a laptop computer, an in-vehicle human-machine interaction device, a personal digital assistant, a media player, a navigation device, a game console, a tablet computer, a wearable device, a smart TV, an Internet of Things system, a smart home, an industrial computer, a server, or a combination thereof.

[0087] Although not shown, in an embodiment of the present invention, a storage medium is provided, and the storage medium stores a computer program, and the computer program is configured to execute the compilation method based on file differences in any embodiment of the present invention when being run.

[0088] The storage medium in the embodiment of the present invention includes items that are permanent and non-permanent, removable and non-removable, and can implement information storage by any method or technology. Examples of the storage medium include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage, or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0089] The methods, programs, systems, devices, etc. of the embodiments of the present invention can be executed or implemented in a single or multiple networked computers, and can also be practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be executed by remote processing devices connected through a communication network.

[0090] Those skilled in the art should understand that the embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, those skilled in the art can conceive that the implementation of the functional modules / units or controllers and related method steps illustrated in the above embodiments can be achieved in a software, hardware, or a combination of software and hardware manner.

[0091] Unless explicitly stated, the actions or steps of the methods and programs described according to the embodiments of the present invention do not necessarily have to be executed in a specific order and still can achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0092] In this document, multiple embodiments of the present invention have been described. However, for the sake of brevity, the descriptions of each embodiment are not exhaustive, and the same or similar features or parts between the various embodiments may be omitted. In this document, "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean applicable to at least one embodiment or example according to the present invention, rather than all embodiments. The above terms do not necessarily refer to the same embodiment or example. Without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0093] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are only examples of the best modes for implementing the systems and methods. Those skilled in the art can understand that various changes can be made to the embodiments of the systems and methods described herein when implementing the systems and / or methods without departing from the spirit and scope of the present invention defined in the appended claims.

Claims

1. A modeling method for the state syntax module in RTL, characterized in that, The method includes: Analyzing and obtaining the state syntax modules in each Module module in the RTL file layer by layer; Analyzing the interconnection relationships of the state syntax modules within the Module module to obtain the corresponding input and output ports of the state syntax modules; Remodeling the state syntax modules according to the interconnection relationships and driving directions to obtain a Module module that conforms to the hardware description language standard; Reconstructing the Module module that conforms to the hardware description language standard into a logic expression module and instantiating the logic expression module to an internal position of the Module module where the state syntax module is located; Adding input and output ports to the logic expression module according to the interconnection relationships of the state syntax modules within the Module module, and internal wire networks connected to the input and output ports, to obtain a model file of the main hierarchical tree structure that only contains the Module module and the logic expression module.

2. The modeling method according to claim 1, wherein The step of analyzing and obtaining the state syntax modules in each Module module in the RTL file layer by layer includes: Using a parser to parse the syntax tree memory structure in the RTL file; Analyzing each Module module in the syntax tree memory structure layer by layer in an iterative traversal manner to obtain pointers to each Module module; Obtaining the content of each Module module according to the pointers to each Module module; When it is determined that the content of the Module module is a state syntax module, obtaining a pointer to the state syntax module and the structure of the state syntax module.

3. The modeling method according to claim 1, characterized in that Analyzing the interconnection relationships of the state syntax modules within the Module module to obtain the corresponding input and output ports of the state syntax modules, includes: Analyzing the interconnection signals of the state syntax modules within the Module module and tracing the driving directions of the interconnection signals; Obtaining the interconnection relationships between the state syntax module and other modules within the Module module according to the driving directions; Obtaining the corresponding input and output ports of the state syntax module according to the interconnection relationships.

4. The modeling method according to claim 3, wherein The step of tracing the driving directions of the interconnection signals includes: Tracing the input and output of the interconnection signals according to the interconnection signals of the state syntax module to obtain the driving directions of the interconnection signals.

5. The modeling method according to claim 2, characterized in that The syntax tree memory structure is used to store the logical relationships, logical hierarchies, and syntax expressions of the hardware integrated circuit design in the RTL file.

6. The modeling method according to claim 5, wherein Analyzing each Module module in the syntax tree memory structure layer by layer in an iterative traversal manner to obtain pointers to each Module module, includes: Starting from each Module module in the syntax tree memory structure in an iterative traversal manner, taking each logic expression module as a branch, and analyzing the leaf nodes of each node in the syntax tree memory structure layer by layer; Reconstructing a new hierarchical structure tree according to the leaf nodes of each node, and obtaining pointers to each Module module according to the hierarchical structure tree.

7. The modeling method according to claim 6, wherein Reconstructing the Module module that conforms to the hardware description language standard into a logic expression module, includes: Perform addition, subtraction, multiplication, division, AND, OR, and NOT analysis on the logic symbols of the Module module that conforms to the hardware description language standard, and reconstruct the Module module into a logic expression module.

8. A modeling system for a state syntax module in RTL, characterized in that, The system includes: A traversal module for layer-by-layer analyzing and obtaining the state syntax modules in each Module module in the RTL file; An analysis module for analyzing the interconnection relationship of the state syntax modules within the Module module to obtain the input and output ports corresponding to the state syntax modules; A reconstruction module for re-modeling the state syntax modules according to the interconnection relationship and the driving direction to obtain a Module module that conforms to the hardware description language standard; A restructuring module for restructuring the Module module that conforms to the hardware description language standard into a logic expression module and instantiating the logic expression module to an internal position of the Module module where the state syntax module is located; An output module for adding input and output ports and internal wire networks connected to the input and output ports to the logic expression module according to the interconnection relationship of the state syntax modules within the Module module, and outputting a model file that only includes the main hierarchical tree structure of the Module module and the logic expression module.

9. A storage medium having a computer program stored thereon, characterized in that, When the program is run by a processor, it implements the method according to any one of claims 1-7.

10. An electronic device, characterized in that, It includes: A processor and a memory storing a computer program, and the processor is configured to implement the method according to any one of claims 1-7 when running the computer program.

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