A method for manufacturing a flip-chip LED chip

Abstract

The present application relates to LED chip technical field, specifically to a kind of preparation method of brightening flip LED chip, comprising the following steps: S3: the middle part of Wafer1 is grown into middle part silicon dioxide layer;S4: the side of the periphery silicon dioxide layer extending towards the middle part of Wafer1 is covered on P-type gallium nitride layer, and the edge of this side is 7-9 microns away from the edge of P-type gallium nitride layer;Uniformly etch a plurality of through holes on middle part silicon dioxide layer by photoetching process.The beneficial effects of the present application are that the middle part silicon dioxide layer helps ITO layer to diffuse the current flowing through quantum well layer, improves luminous flux.Partial silver mirror reflection layer bypasses ITO layer and directly contacts P-type gallium nitride to further diffuse the current flowing through quantum well layer.The middle part silicon dioxide layer is provided with through hole, so that it can form high-low refractive index refractive layer with silver mirror reflection layer, so that light is totally reflected, and the luminous flux of LED chip is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED chip, and particularly relates to a preparation method of a brightened flip LED chip. BACKGROUND

[0002] LED (Light Emitting Diode) is a kind of solid-state semiconductor device that converts electrical energy into light energy. As a new type of light-emitting device, LED has the advantages of high light efficiency, energy saving, long service life, short response time, environmental protection, etc., and is therefore called the most potential new generation light source.

[0003] LED chips are divided into vertical and flip, and the flip LED chip applied to the headlamp requires the flip LED chip to have high brightness. Referring to the Chinese patent with the publication number CN112242461A, a high-brightness LED chip and a manufacturing method are disclosed, in which the brightness of the LED chip is improved by increasing the thickness of the ITO layer and reducing the width of the ITO layer. However, the above-mentioned scheme cannot achieve the expected brightness improvement of the LED chip. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a preparation method of a brightened flip LED chip.

[0005] In order to solve the above technical problems, a technical solution adopted by the present application is as follows: a preparation method of a brightened flip LED chip, comprising the following steps:

[0006] S1: placing a substrate into a reaction cavity, growing an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer on the substrate in sequence; etching the edges of the quantum well layer and the P-type gallium nitride layer to expose the surface of the N-type gallium nitride layer;

[0007] S2: growing an ITO layer on the P-type gallium nitride layer by sputtering process and photolithography process, and making the edge of the ITO layer be 12-16 microns away from the edge of the P-type gallium nitride layer;

[0008] S3: the structure obtained by the above steps is Wafer1; depositing silicon dioxide on Wafer1 to grow a peripheral silicon dioxide layer on the periphery of Wafer1 and a middle silicon dioxide layer in the middle of Wafer1;

[0009] S4: etching the peripheral silicon dioxide layer by photolithography process to cover the P-type gallium nitride layer with the side part of the peripheral silicon dioxide layer extending towards the middle of Wafer1, and the edge of the side part is 7-9 microns away from the edge of the P-type gallium nitride layer;

[0010] Etching the middle silicon dioxide layer by a photoetching process, so that the middle silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle silicon dioxide layer is 11-13 microns away from the edge of the P-type gallium nitride layer;

[0011] Etching multiple through holes on the middle silicon dioxide layer by a photoetching process;

[0012] S5: The structure obtained by the above steps is Wafer2, a silver mirror reflection layer is sputtered on Wafer2, and the silver mirror reflection layer on the peripheral silicon dioxide layer is etched and removed by a photoetching process;

[0013] S6: The preparation of the flip LED chip is completed.

[0014] The beneficial effects of the present application are that there is no middle silicon dioxide layer between the silver mirror reflection layer and the ITO layer of a conventional LED chip; the middle silicon dioxide layer in the preparation method of the brightened flip LED chip of the present application replaces part of the silver mirror reflection layer, saves the metal material for generating the silver mirror reflection layer, and reduces the cost.

[0015] The ITO layer is assisted by the middle silicon dioxide layer to diffuse the current flowing through the quantum well layer, and the light emission amount is improved. Part of the silver mirror reflection layer directly contacts the P-type gallium nitride layer to further diffuse the current flowing through the quantum well layer.

[0016] The middle silicon dioxide layer is provided with through holes, so that it can form a high-low refractive index refractive layer with the silver mirror reflection layer, so that the light is totally reflected, and the light emission amount of the LED chip is increased. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a schematic diagram of the overall structure of the flip LED chip of Example Three of the embodiment of the present application;

[0018] Figure 2 It is a data curve graph of photoelectric testing of the comparative example of the embodiment of the present application;

[0019] REFERENCE NUMERALS:

[0020] 1, substrate; 2, N-type gallium nitride layer; 3, quantum well layer; 4, P-type gallium nitride layer; 5, ITO layer; 6, peripheral silicon dioxide layer; 7, middle silicon dioxide layer; 8, through hole; 9, silver mirror reflection layer; 10, silver mirror protection layer; 11, silver mirror silicon dioxide layer; 12, line metal; 13, surface silicon dioxide layer; 14, pad metal. DETAILED DESCRIPTION

[0021] To explain the technical content, purposes and effects of the present application in detail, the following will be described in conjunction with the embodiments and the accompanying drawings.

[0022] The application provides a preparation method of a brightened flip LED chip.

[0023] S1: placing a substrate into a reaction cavity, sequentially growing an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer on the substrate, and etching edges of the quantum well layer and the P-type gallium nitride layer to expose a surface of the N-type gallium nitride layer;

[0024] S2: growing an ITO layer on the P-type gallium nitride layer by a sputtering process and a photolithography process, and making an edge of the ITO layer be 12-16 microns away from an edge of the P-type gallium nitride layer;

[0025] S3: obtaining a structure Wafer 1 through the above steps, depositing silicon dioxide on the Wafer 1, growing a peripheral silicon dioxide layer on a peripheral edge of the Wafer 1, and growing a middle silicon dioxide layer on a middle part of the Wafer 1;

[0026] S4: etching the peripheral silicon dioxide layer by a photolithography process, so that a side part of the peripheral silicon dioxide layer extending towards the middle part of the Wafer 1 covers the P-type gallium nitride layer, and an edge of the side part is 7-9 microns away from an edge of the P-type gallium nitride layer;

[0027] etching the middle silicon dioxide layer by a photolithography process, so that the middle silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and an edge of the middle silicon dioxide layer is 11-13 microns away from an edge of the P-type gallium nitride layer;

[0028] uniformly etching a plurality of through holes on the middle silicon dioxide layer by a photolithography process;

[0029] S5: obtaining a structure Wafer 2 through the above steps, sputtering a silver mirror reflection layer on the Wafer 2, and etching and removing the silver mirror reflection layer on the peripheral silicon dioxide layer by a photolithography process;

[0030] S6: completing preparation of the flip LED chip.

[0031] As known from the above description, the silver mirror reflection layer of a conventional LED chip has no middle silicon dioxide layer between the silver mirror reflection layer and the ITO layer; the middle silicon dioxide layer in the preparation method of the brightened flip LED chip of the application replaces part of the silver mirror reflection layer, saves metal material for generating the silver mirror reflection layer, and reduces cost.

[0032] The middle silicon dioxide layer helps the ITO layer diffuse the current flowing through the quantum well layer, and improves the light emission. Because the ITO layer is 12-16 microns away from the edge of the P-type gallium nitride layer; the etched peripheral silicon dioxide layer has a side part extending towards the middle of the Wafer 1 and covering the P-type gallium nitride layer, and the edge of the side part is 7-9 microns away from the edge of the P-type gallium nitride layer; and the edge of the middle silicon dioxide layer is 11-13 microns away from the edge of the P-type gallium nitride layer, the silver mirror reflective layer formed has a part directly contacting the P-type gallium nitride layer, and part of the silver mirror reflective layer bypasses the ITO layer to directly contact the P-type gallium nitride layer, further diffusing the current flowing through the quantum well layer.

[0033] The middle silicon dioxide layer forms a high-low refractive index refractive layer with the silver mirror reflective layer due to the through hole, so that the light is totally reflected, and the light emission of the LED chip is increased.

[0034] Further, the reaction cavity pressure in S3 and S4 is maintained at 80-100 Pa, and the temperature is 200-230 degrees.

[0035] As can be seen from the above description, the above arrangement provides a simple and efficient method of depositing silicon dioxide, and improves the quality of the peripheral silicon dioxide layer and the middle silicon dioxide layer.

[0036] Further, the S5 further comprises S5.1, S5.2 and S5.3.

[0037] S5.1: making a silver mirror protective layer;

[0038] S5.2: the structure obtained through the above steps is Wafer 3, and a silver mirror silicon dioxide layer 11 is covered on the Wafer 3;

[0039] S5.3: hole making and electrode making on the structure obtained through the above steps.

[0040] As can be seen from the above description, the above arrangement supplements a simple and efficient step between S5 and the formation of the LED chip.

[0041] Further, the S5 further comprises S5.4 and S5.5.

[0042] S5.4: the structure obtained through the above steps is Wafer 5, a surface silicon dioxide layer is covered on the Wafer 5, and a hole is made on the surface silicon dioxide layer;

[0043] S5.5: the structure obtained through the above steps is Wafer 6, a Pad metal is evaporated on the Wafer 6, and the Pad metal is connected to the electrode.

[0044] From the above description, the LED chip needs to be welded with the packaging substrate in the subsequent processing procedure, and the Pad metal can be used as a simple and efficient welding layer of the LED chip and the packaging substrate.

[0045] Further, the step S5.1 is specifically: covering the silver mirror reflection layer with a silver mirror protection layer through an evaporation process; and the metal material of the silver mirror protection layer includes chromium, aluminum, titanium and platinum.

[0046] From the above description, the chromium in the silver mirror protection layer improves the adhesion of the silver mirror protection layer and other structures, the titanium and platinum play a protective role, and the aluminum plays a role of reflecting light.

[0047] Further, the "opening holes on the structure obtained in the above step" of the S5.3 is specifically: the structure obtained through the above steps is Wafer4, N-pole holes are etched on the Wafer4, the N-pole holes penetrate the silver mirror silicon dioxide layer and the peripheral silicon dioxide layer to the N-type gallium nitride layer; and P-pole holes are etched in the middle of the silver mirror silicon dioxide layer to the silver mirror protection layer through a photoetch process.

[0048] From the above description, the above setting provides a simple and efficient method for providing an electrical connection path for the LED chip. The "etching" includes the steps of uniform coating, exposure, development, and etching, and the etching step uses a BOE solution for etching, and the BOE solution is mixed with ammonium fluoride: hydrogen fluoride = 6:1.

[0049] Further, the "making electrodes" of the S5.3 is specifically: evaporating Line metal in the N-pole holes and on the periphery of the silver mirror silicon dioxide layer.

[0050] From the above description, the Line metal has a linear appearance, hence the name "Line", and the above setting provides a simple and efficient method for making electrodes.

[0051] Further, the "opening holes on the surface silicon dioxide layer" of the S5.4 is specifically: opening holes on the surface silicon dioxide layer through etching, and the P-pole holes and the Line metal are exposed through the opening holes.

[0052] From the above description, the above setting provides a simple and efficient method for opening holes on the surface silicon dioxide layer.

[0053] Further, the S5.5 is specifically: the structure obtained through the above steps is Wafer6, Pad metal is evaporated on the Wafer6, the Pad metal is etched to divide the Pad metal into a first Pad electrode and a second Pad electrode, the first Pad electrode contacts the silver mirror protection layer, and the second Pad electrode contacts the Line metal; and the preparation of the flip-chip LED chip is completed.

[0054] From the above description, the above setting provides a simple and efficient method for generating Pad metal, which avoids short circuit of LED chips by dividing Pad metal.

[0055] Further, the S3 and S4 are specifically:

[0056] Depositing silicon dioxide on the Wafer1, coating photoresist on the silicon dioxide, covering the photoresist with a mask plate, the mask plate has a plurality of mask through holes uniformly arranged in the middle part, the diameter of the mask through hole is 8-20 microns, and the distance between adjacent mask through holes is 18-30 microns; The mask plate is provided with an annular through groove, the horizontal position of the annular through groove is between the edge of the ITO layer and the edge of the P layer; The through hole is on the side of the annular through groove away from the edge of the mask plate;

[0057] After developing and exposing the photoresist, using an etching solution to etch the silicon dioxide and the photoresist, so that the circumferential silicon dioxide layer covers the P-type gallium nitride layer on the side of the Wafer1 extending towards the middle part, and the edge of the side is 7-9 microns away from the edge of the P-type gallium nitride layer;

[0058] The middle part of the silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle part of the silicon dioxide layer is 11-13 microns away from the edge of the P-type gallium nitride layer;

[0059] Etching a plurality of through holes uniformly on the middle part of the silicon dioxide layer, so that the diameter of the through hole is 7-9 microns, and the distance between adjacent through holes is 29-31 microns.

[0060] From the above description, the above setting provides a simple and efficient method for etching silicon dioxide to form a circumferential silicon dioxide layer and a middle part of the silicon dioxide layer, and a method for etching through holes on the middle part of the silicon dioxide layer.

[0061] Embodiment one

[0062] The preparation method of the brightened flip LED chip provided in this embodiment includes the following steps:

[0063] S1: Put the substrate into the reaction cavity, and grow N-type gallium nitride layer, quantum well layer and P-type gallium nitride layer on the substrate in sequence; Etch the edge of the quantum well layer and the P-type gallium nitride layer, so that the surface of the N-type gallium nitride layer is exposed;

[0064] S2: Through sputtering process and photolithography process, ITO layer is grown on the P-type gallium nitride layer, and the edge of the ITO layer is 12 microns away from the edge of the P-type gallium nitride layer;

[0065] S3: The structure obtained through the above steps is Wafer1; set the reaction cavity pressure to 80 Pa and the temperature to 200 degrees, deposit silicon dioxide on Wafer1, and grow a peripheral silicon dioxide layer on the periphery of Wafer1 and a middle silicon dioxide layer in the middle of Wafer1;

[0066] S4: Etch the peripheral silicon dioxide layer through a photolithography process, so that the side of the peripheral silicon dioxide layer covers the P-type gallium nitride layer and the edge of the side is 7 microns away from the edge of the P-type gallium nitride layer;

[0067] Etch the middle silicon dioxide layer through a photolithography process, so that the middle silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle silicon dioxide layer is 11-13 microns away from the edge of the P-type gallium nitride layer;

[0068] Uniformly etch multiple through holes on the middle silicon dioxide layer through a photolithography process;

[0069] The reaction cavity pressure is maintained at 80 Pa and the temperature is maintained at 200 degrees in this step;

[0070] S5: The structure obtained through the above steps is Wafer2; sputter a silver mirror reflection layer on Wafer2, and etch and remove the silver mirror reflection layer on the peripheral silicon dioxide layer through a photolithography process;

[0071] S6: Cover a silver mirror protection layer on the silver mirror reflection layer through an evaporation process; the metal material of the silver mirror protection layer includes chromium, aluminum, titanium, and platinum;

[0072] S7: The structure obtained through the above steps is Wafer3; cover a silver mirror silicon dioxide layer on Wafer3;

[0073] S8: The structure obtained through the above steps is Wafer4; etch an N-pole opening on Wafer4, so that the N-pole opening penetrates through the silver mirror silicon dioxide layer and the peripheral silicon dioxide layer to the N-type gallium nitride layer; etch a P-pole opening in the middle of the silver mirror silicon dioxide layer through a photolithography process, so that the P-pole opening penetrates to the silver mirror protection layer;

[0074] S9: Evaporate Line metal in the N-pole opening and on the periphery of the silver mirror silicon dioxide layer;

[0075] S10: The structure obtained through the above steps is Wafer5; cover a surface silicon dioxide layer on Wafer5, open an opening on the surface silicon dioxide layer through etching, and expose the P-pole opening and the Line metal through the opening;

[0076] S11: The structure obtained through the above steps is Wafer 6, a Pad metal is evaporated on Wafer 6, the Pad metal is etched to divide the Pad metal into a first Pad electrode and a second Pad electrode, the first Pad electrode contacts the silver mirror protective layer, and the second Pad electrode contacts the Line metal; and the preparation of the flip LED chip is completed.

[0077] Embodiment Two

[0078] Please refer to Figure 1 The preparation method for brightening the flip LED chip provided in this embodiment comprises the following steps:

[0079] S1: A substrate is placed into a reaction cavity, and an N-type gallium nitride layer, a quantum well layer, and a P-type gallium nitride layer are sequentially grown on the substrate; the edges of the quantum well layer and the P-type gallium nitride layer are etched to expose the surface of the N-type gallium nitride layer;

[0080] S2: An ITO layer is grown on the P-type gallium nitride layer through a sputtering process and a photolithography process, and the edge of the ITO layer is 16 microns away from the edge of the P-type gallium nitride layer;

[0081] S3: The structure obtained through the above steps is Wafer 1; the pressure of the reaction cavity is set to 100 Pa, and the temperature is set to 230 degrees; a silicon dioxide layer is deposited on Wafer 1 to grow a peripheral silicon dioxide layer on the periphery of Wafer 1 and a middle silicon dioxide layer in the middle of Wafer 1;

[0082] S4: The peripheral silicon dioxide layer is etched through a photolithography process to cover the P-type gallium nitride layer on the side of the peripheral silicon dioxide layer, and the edge of the side is 9 microns away from the edge of the P-type gallium nitride layer;

[0083] The middle silicon dioxide layer is etched through a photolithography process to cover the P-type gallium nitride layer and the ITO layer, and the edge of the middle silicon dioxide layer is 13 microns away from the edge of the P-type gallium nitride layer;

[0084] A plurality of through holes are uniformly etched on the middle silicon dioxide layer through a photolithography process;

[0085] The pressure of the reaction cavity is maintained at 100 Pa, and the temperature is maintained at 230 degrees in this step;

[0086] S5: The structure obtained through the above steps is Wafer 2, a silver mirror reflective layer is sputtered on Wafer 2, and the silver mirror reflective layer on the peripheral silicon dioxide layer is etched and removed through a photolithography process;

[0087] S6: A silver mirror protective layer is covered on the silver mirror reflective layer through an evaporation process; the metal material of the silver mirror protective layer comprises chromium, aluminum, titanium, and platinum;

[0088] S7: The structure obtained through the above steps is Wafer3, and a silver mirror silicon dioxide layer is coated on the Wafer3;

[0089] S8: The structure obtained through the above steps is Wafer4, and an N-pole opening is etched on the Wafer4, so that the N-pole opening penetrates through the silver mirror silicon dioxide layer and the peripheral silicon dioxide layer to the N-type gallium nitride layer; a P-pole opening is etched in the middle of the silver mirror silicon dioxide layer to the silver mirror protective layer through a photolithography process;

[0090] S9: Line metal is evaporated in the N-pole opening and on the periphery of the silver mirror silicon dioxide layer;

[0091] S10: The structure obtained through the above steps is Wafer5, a surface silicon dioxide layer is coated on the Wafer5, an opening is etched on the surface silicon dioxide layer, and the P-pole opening and the Line metal are exposed through the opening;

[0092] S11: The structure obtained through the above steps is Wafer6, Pad metal is evaporated on the Wafer6, and the Pad metal is etched to divide the Pad metal into a first Pad electrode and a second Pad electrode, the first Pad electrode contacts the silver mirror protective layer, and the second Pad electrode contacts the Line metal; and the preparation of the flip LED chip is completed.

[0093] Example Three

[0094] The preparation method for brightening the flip LED chip provided in the embodiment includes the following steps:

[0095] S1: A substrate is placed into a reaction chamber, and an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer are sequentially grown on the substrate; the edges of the quantum well layer and the P-type gallium nitride layer are etched, and the surface of the N-type gallium nitride layer is exposed;

[0096] S2: An ITO layer is grown on the P-type gallium nitride layer through a sputtering process and a photolithography process, and the edge of the ITO layer is 14 microns away from the edge of the P-type gallium nitride layer;

[0097] S3: The structure obtained through the above steps is Wafer1; the pressure of the reaction chamber is set to 90 Pa, and the temperature is set to 215 degrees; silicon dioxide is deposited on the Wafer1, a peripheral silicon dioxide layer is grown on the periphery of the Wafer1, and a middle silicon dioxide layer is grown in the middle of the Wafer1;

[0098] S4: The peripheral silicon dioxide layer is etched through a photolithography process, so that the side of the peripheral silicon dioxide layer covers the P-type gallium nitride layer, and the edge of the side is 8 microns away from the edge of the P-type gallium nitride layer;

[0099] Etching the middle silicon dioxide layer by a photolithography process, so that the middle silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle silicon dioxide layer is 12 microns away from the edge of the P-type gallium nitride layer;

[0100] Uniformly etching a plurality of through holes on the middle silicon dioxide layer by a photolithography process;

[0101] The pressure in the reaction cavity in this step is maintained at 90 Pa, and the temperature is 215 degrees;

[0102] S3 and S4 are specifically:

[0103] Depositing silicon dioxide on Wafer1, coating photoresist on the silicon dioxide, covering the photoresist with a mask, the middle of the mask being uniformly provided with a plurality of mask through holes, the diameter of the mask through holes being 8-20 microns, and the distance between adjacent mask through holes being 18-30 microns; the mask is provided with an annular through groove, the horizontal position of the annular through groove being between the edge of the ITO layer and the edge of the P layer; the through holes are on the side of the annular through groove away from the edge of the mask;

[0104] After developing and exposing the photoresist, using an etching solution to etch the silicon dioxide and the photoresist, so that the circumferential silicon dioxide layer on the side extending towards the middle of Wafer1 covers the P-type gallium nitride layer, and the edge of the side is 8 microns away from the edge of the P-type gallium nitride layer;

[0105] Etching the middle silicon dioxide layer by a photolithography process, so that the middle silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle silicon dioxide layer is 12 microns away from the edge of the P-type gallium nitride layer;

[0106] Uniformly etching a plurality of through holes on the middle silicon dioxide layer, so that the diameter of the through holes is 8 microns, and the distance between adjacent through holes is 30 microns.

[0107] S5: The structure obtained by the above steps is Wafer2, a silver mirror reflection layer is sputtered on Wafer2, and the silver mirror reflection layer on the circumferential silicon dioxide layer is etched and removed by a photolithography process;

[0108] S6: A silver mirror protection layer is covered on the silver mirror reflection layer by an evaporation process; the metal material of the silver mirror protection layer includes chromium, aluminum, titanium and platinum;

[0109] S7: The structure obtained by the above steps is Wafer3, a silver mirror silicon dioxide layer is covered on Wafer3;

[0110] S8: The structure obtained through the above steps is Wafer 4, N-pole openings are etched on Wafer 4, the N-pole openings penetrate the silver mirror silicon dioxide layer and the peripheral silicon dioxide layer until the N-type gallium nitride layer; P-pole openings are etched in the middle of the silver mirror silicon dioxide layer until the P-pole openings penetrate the silver mirror protective layer through a photolithography process;

[0111] S9: Line metal is evaporated in the N-pole openings and on the periphery of the silver mirror silicon dioxide layer;

[0112] S10: The structure obtained through the above steps is Wafer 5, a surface silicon dioxide layer is coated on Wafer 5, openings are etched on the surface silicon dioxide layer, and the P-pole openings and the Line metal are exposed through the openings;

[0113] S11: The structure obtained through the above steps is Wafer 6, Pad metal is evaporated on Wafer 6, the Pad metal is etched to divide the Pad metal into a first Pad electrode and a second Pad electrode, the first Pad electrode contacts the silver mirror protective layer, and the second Pad electrode contacts the Line metal; the preparation of the flip LED chip is completed.

[0114] Please refer to Figure 1 , the flip LED chip structure obtained in Example Three is as follows:

[0115] The flip LED chip obtained in Example Three comprises a substrate 1, an N-type gallium nitride layer 2, a quantum well layer 3, a P-type gallium nitride layer 4, and an ITO layer 5 which are sequentially stacked; the edge of the ITO layer 5 is 14 microns away from the edge of the P-type gallium nitride layer 4;

[0116] It also comprises a peripheral silicon dioxide layer 6, a middle silicon dioxide layer 7, and a silver mirror reflection layer 9;

[0117] The peripheral silicon dioxide layer 6 covers the peripheral of the exposed P-type gallium nitride layer 4 and the ITO layer 5; the side edge of the peripheral silicon dioxide layer 6 which extends towards the middle of the ITO layer 5 is 8 microns away from the edge of the P-type gallium nitride layer 4;

[0118] The middle silicon dioxide layer 7 covers the middle of the ITO layer 5, and the edge of the middle silicon dioxide layer 7 is 12 microns away from the edge of the P-type gallium nitride layer 4;

[0119] A plurality of through holes 8 are uniformly arranged on the middle silicon dioxide layer 7; the through holes 8 are 8 microns in diameter, and the distance between adjacent through holes 8 is 30 microns. The silver mirror reflection layer 9 is injected into the through holes 8 of the middle silicon dioxide layer 7, and the silver mirror reflection layer 9 covers the exposed middle silicon dioxide layer 7, the exposed P-type gallium nitride layer 4, and the exposed ITO layer 5.

[0120] The silver mirror reflective layer 9 is further provided with a silver mirror protective layer 10 and a silver mirror silicon dioxide layer 11. A line metal 12 is provided on the silver mirror silicon dioxide layer 11. The line metal 12 penetrates the first silicon dioxide and the peripheral silicon dioxide layer 6 and connects to the N-type gallium nitride layer 2. A surface silicon dioxide layer 13 is also provided on the line metal 12 and the silver mirror silicon dioxide layer 11. A pad metal 14 is provided on the surface silicon dioxide layer 13. A portion of the pad metal 14 penetrates the surface silicon dioxide layer 13 and connects to the line metal 12. Another portion of the pad metal 14 penetrates the surface silicon dioxide layer 13 and the silver mirror silicon dioxide layer 11 and connects to the silver mirror protective layer 10.

[0121] Comparative Example

[0122] Please refer to Figure 2 , Figure 2 The solid line in the figure represents the average value of the data obtained from photoelectric testing of multiple flip-chip LEDs formed using the scheme of Embodiment 3 of the present invention.

[0123] Figure 2 The dashed line represents the average value of the data obtained from photoelectric testing of multiple flip-chip LEDs formed using conventional techniques.

[0124] The difference between the conventional technology solution and the solution of Embodiment 3 of this application lies only in that steps S3 and S4 are replaced with:

[0125] S3: The structure obtained through the above steps is Wafer1; set the reaction chamber pressure to 90Pa and the temperature to 215 degrees, deposit silicon dioxide on Wafer1, and grow a peripheral silicon dioxide layer on the periphery of Wafer1.

[0126] S4: The peripheral silicon dioxide layer is etched by photolithography so that its side covers the P-type gallium nitride layer and the edge of this side is 8 micrometers away from the edge of the P-type gallium nitride layer;

[0127] During this step, the reaction chamber pressure is maintained at 90 Pa and the temperature at 215 degrees Celsius.

[0128] from Figure 1 It is easy to see that, under the same operating current, the flip-chip LED formed using the scheme of Embodiment 3 of the present invention (solid line) has a higher brightness than the flip-chip LED formed using conventional technology (dashed line). This difference becomes increasingly pronounced as the operating current increases.

[0129] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a bright flip-chip LED chip, characterized in that, The method comprises the following steps: S1: placing a substrate into a reaction cavity, sequentially growing an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer on the substrate, and etching edges of the quantum well layer and the P-type gallium nitride layer to expose a surface of the N-type gallium nitride layer; S2: growing an ITO layer on the P-type gallium nitride layer by a sputtering process and a photolithography process, and making an edge of the ITO layer be 12-16 microns away from an edge of the P-type gallium nitride layer; S3: obtaining a structure Wafer1 by the above steps, depositing silicon dioxide on the Wafer1, growing a peripheral silicon dioxide layer on a peripheral edge of the Wafer1, and growing a middle silicon dioxide layer on a middle part of the Wafer1; S4: etching the peripheral silicon dioxide layer by a photolithography process, so that a side part of the peripheral silicon dioxide layer extending towards the middle part of the Wafer1 covers the P-type gallium nitride layer, and an edge of the side part is 7-9 microns away from an edge of the P-type gallium nitride layer; S4: etching the peripheral silicon dioxide layer by a photolithography process, so that a side part of the peripheral silicon dioxide layer extending towards the middle part of the Wafer1 covers the P-type gallium nitride layer, and an edge of the side part is 7-9 microns away from an edge of the P-type gallium nitride layer; S4: etching the peripheral silicon dioxide layer by a photolithography process, so that a side part of the peripheral silicon dioxide layer extending towards the middle part of the Wafer1 covers the P-type gallium nitride layer, and an edge of the side part is 7-9 microns away from an edge of the P-type gallium nitride layer; S4: etching the peripheral silicon dioxide layer by a photolithography process, so that a side part of the peripheral silicon dioxide layer extending towards the middle part of the Wafer1 covers the P-type gallium nitride layer, and an edge of the side part is 7-9 microns away from an edge of the P-type gallium nitride layer; S5: obtaining a structure Wafer2 by the above steps, sputtering a silver mirror reflection layer on the Wafer2, and etching and removing the silver mirror reflection layer on the peripheral silicon dioxide layer by a photolithography process; 2. The method of claim 1, wherein the flip-chip LED chip is prepared by the steps of: S6: completing preparation of the flip chip LED.

3. The method of claim 1, wherein the flip-chip LED chip is prepared by the steps of: In the steps S3 and S4, the pressure in the reaction cavity is kept at 80-100 Pa, and the temperature is kept at 200-230 degrees. The step S5 further comprises S5.1, S5.2 and S5.

3. S5.1: making a silver mirror protection layer; S5.2: obtaining a structure Wafer3 by the above steps, and covering a silver mirror silicon dioxide layer on the Wafer3; 4. The method of claim 3, wherein the flip-chip LED chip is prepared by the steps of: S5.3: making holes and electrodes on the structure obtained in the above step. The step S5 further comprises S5.4 and S5.

5. S5.4: obtaining a structure Wafer5 by the above steps, covering a surface silicon dioxide layer on the Wafer5, and making holes on the surface silicon dioxide layer; 5. The method of claim 4, wherein the flip-chip LED chip is prepared by the steps of: forming a transparent layer on the surface of the flip-chip LED chip; and forming a transparent electrode on the transparent layer. S5.5: obtaining a structure Wafer6 by the above steps, evaporating a Pad metal on the Wafer6, and connecting the Pad metal to electrodes.

6. The method of claim 4, wherein the flip-chip LED chip is prepared by the steps of: The step S5.1 specifically comprises: covering a silver mirror protection layer on the silver mirror reflection layer by an evaporation process; and the metal material of the silver mirror protection layer comprises chromium, aluminum, titanium and platinum.

7. The method of claim 6, wherein the flip-chip LED chip is prepared by the steps of: forming a transparent layer on the surface of the flip-chip LED chip; and forming a transparent electrode on the transparent layer. The "making holes on the structure obtained in the above step" in the step S5.3 specifically comprises: etching an N-pole hole on a Wafer4 obtained by the above steps by a photolithography process, so that the N-pole hole penetrates the silver mirror silicon dioxide layer and the peripheral silicon dioxide layer to reach the N-type gallium nitride layer; and etching a P-pole hole in a middle part of the silver mirror silicon dioxide layer by a photolithography process, so that the P-pole hole penetrates to the silver mirror protection layer. The "making electrodes" in the step S5.3 specifically comprises: evaporating a Line metal in the N-pole hole and on a peripheral edge of the silver mirror silicon dioxide layer.

8. The method of claim 7, wherein the flip-chip LED chip is prepared by the steps of: The "opening holes on the surface layer of silicon dioxide" of S5.4 is specifically opening holes on the surface layer of silicon dioxide by etching, and exposing the P-pole opening and the Line metal by the opening holes.

9. The method of claim 8, wherein the flip-chip LED chip is prepared by the steps of: The S5.5 is specifically: the structure obtained by the above steps is Wafer 6, evaporating Pad metal on Wafer 6, and etching the Pad metal to divide the Pad metal into a first Pad electrode and a second Pad electrode, the first Pad electrode contacts the silver mirror protective layer, and the second Pad electrode contacts the Line metal; and the preparation of the flip chip LED is completed.

10. The method of claim 1, wherein the flip-chip LED chip is prepared by the steps of: The S3 and S4 are specifically: ​ Depositing silicon dioxide on Wafer 1, coating photoresist on the silicon dioxide, covering the photoresist with a mask plate, the mask plate having a plurality of mask through holes uniformly arranged in the middle part, the diameter of the mask through holes being 8-20 microns, and the distance between adjacent mask through holes being 18-30 microns; the mask plate is provided with a ring-shaped through groove, the horizontal position of the ring-shaped through groove being between the edge of the ITO layer and the edge of the P layer; the through holes are on the side of the ring-shaped through groove away from the edge of the mask plate; After developing the exposed photoresist, using an etching solution to etch the silicon dioxide and the photoresist, the circumferential silicon dioxide layer on the side extending towards the middle part of the Wafer 1 covers the P-type gallium nitride layer, and the edge of the side is 7-9 microns away from the edge of the P-type gallium nitride layer; The middle part of the silicon dioxide layer covers the P-type gallium nitride layer and the ITO layer, and the edge of the middle part of the silicon dioxide layer is 11-13 microns away from the edge of the P-type gallium nitride layer; Uniformly etching a plurality of through holes on the middle part of the silicon dioxide layer, the diameter of the through holes being 7-9 microns, and the distance between adjacent through holes being 29-31 microns.

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