LED chip and method for manufacturing an LED chip

Abstract

The application discloses an LED chip and a method for manufacturing the same. The LED chip comprises, from bottom to top, a substrate, a protective layer, an active layer and a transmission unit. The transmission unit comprises a p-type transmission unit and an n-type transmission unit. The p-type transmission unit comprises a p-type transmission layer and a first conductive layer located on a side of the p-type transmission layer away from the active layer. The p-type transmission layer is electrically connected with a first electrode through the first conductive layer. The n-type transmission unit comprises an n-type transmission layer and a second conductive layer located on a side of the n-type transmission layer away from the active layer. The n-type transmission layer is electrically connected with a second electrode through the second conductive layer.

Description

LED chips and methods for fabricating LED chips Technical Field

[0001] This invention relates to the field of LED chips, and more specifically, to an LED chip and a method for manufacturing an LED chip. Background Technology

[0002] Currently, LED chips are being used more and more widely in production and daily life. The area of ​​the active layer of an LED chip is the light-emitting area of ​​the LED chip. Therefore, the utilization rate of the active layer is crucial to the light emission of the LED chip. However, in related technologies, there is a problem of low utilization rate of the active layer of flip-chip LEDs. Therefore, how to improve the utilization rate of the active layer of flip-chip LEDs is a current challenge.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides an LED chip and a method for fabricating an LED chip, thereby at least solving the technical problem of low active layer utilization in flip-chip LEDs in related technologies.

[0005] According to one aspect of the present invention, an LED chip is provided, comprising: a substrate, a protective layer, an active layer, and a transmission unit disposed sequentially from bottom to top, wherein the transmission unit includes a p-type transmission unit and an n-type transmission unit, the p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer, the p-type transmission layer being electrically connected to a first electrode through the first conductive layer, and the n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer, the n-type transmission layer being electrically connected to a second electrode through the second conductive layer.

[0006] Optionally, the protective layer includes a buffer layer and an insulating layer, the buffer layer being located between the insulating layer and the substrate, wherein the insulating layer is used to block charge carriers transported in the active layer from entering the buffer layer, and the buffer layer is used to ensure that the lattice of the substrate matches the lattice of the epitaxial structure, the epitaxial structure including the protective layer, the active layer, and the transport unit.

[0007] Optionally, there are multiple p-type transmission units and multiple n-type transmission units, wherein the multiple p-type transmission units and the multiple n-type transmission units are alternately arranged.

[0008] Optionally, in the alternating arrangement of the plurality of p-type transmission units and the plurality of n-type transmission units, two adjacent p-type transmission units share the n-type transmission unit in between them, and two adjacent n-type transmission units share the p-type transmission unit in between them.

[0009] Optionally, the first electrode is used to inject holes, and the second electrode is used to inject electrons.

[0010] Optionally, the active layer is a quantum well active layer.

[0011] Optionally, the protective layer includes a buffer layer, the dielectric constant of which is determined based on the doping elements of the buffer layer.

[0012] According to one aspect of the present invention, a method for fabricating an LED chip is provided, comprising: depositing a protective layer on a substrate; depositing an active layer on the protective layer; fabricating a transmission unit on the active layer, wherein the transmission unit includes a p-type transmission unit and an n-type transmission unit, the p-type transmission unit including a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer, and the n-type transmission unit including an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer; fabricating a first electrode on the first conductive layer; and fabricating a second electrode on the second conductive layer to obtain an LED chip.

[0013] Optionally, depositing a protective layer on the substrate includes: depositing the buffer layer on the substrate if the protective layer includes a buffer layer and an insulating layer; and depositing the insulating layer on the buffer layer.

[0014] Optionally, the fabrication of the transmission unit on the active layer includes: depositing a p-type semiconductor layer on the active layer; depositing a first mask layer on the p-type semiconductor layer; etching the first mask layer and the p-type semiconductor layer to form a first groove, wherein the first groove extends downward to the upper surface of the active layer, and a second mask layer and a p-type semiconductor intermediate layer are obtained; depositing a first n-type semiconductor layer on the second mask layer; depositing a second n-type semiconductor layer on the exposed surface of the first groove on the active layer, wherein the second n-type semiconductor layer is connected to the p-type semiconductor intermediate layer; removing the second mask layer and the first n-type semiconductor layer; depositing a conductive layer on the second n-type semiconductor layer and the p-type semiconductor intermediate layer to obtain a transmission unit layer, wherein the transmission unit layer includes the second n-type semiconductor layer, the p-type semiconductor intermediate layer, and the conductive layer; cutting the transmission unit layer at a position corresponding to the connection between the second n-type semiconductor layer and the p-type semiconductor intermediate layer to separate the second n-type semiconductor layer from the p-type semiconductor intermediate layer, thereby obtaining the p-type transmission unit and the n-type transmission unit.

[0015] In this embodiment of the invention, an LED chip is provided, comprising, from bottom to top, a substrate, a protective layer, an active layer, and transmission units. The transmission units include p-type transmission units and n-type transmission units. The p-type transmission units are electrically connected to a first electrode through a corresponding first conductive layer, and the n-type transmission units are electrically connected to a second electrode through a corresponding second conductive layer. Since both the p-type and n-type transmission units are located on the active layer, and the first electrode can be electrically connected to the p-type transmission layer through the first conductive layer in the p-type transmission unit, and the second electrode can be electrically connected to the n-type transmission layer through the second conductive layer in the n-type transmission unit, the electrodes can be constructed without etching the active layer. This LED chip achieves the goal of having a light-emitting area equal to the bottom area of ​​the LED chip, thereby improving the utilization rate of the active layer and solving the technical problem of low active layer utilization in flip-chip LEDs in related technologies. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0017] Figure 1 is a schematic diagram of an LED chip according to an embodiment of the present invention;

[0018] Figure 2 is a flowchart of a method for preparing an LED chip according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of the LED chip fabrication process provided by an optional embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of the working principle of the LED chip provided in an optional embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Example 1

[0024] According to an embodiment of the present invention, an embodiment of a light-emitting diode (LED) chip is provided.

[0025] First, it should be noted that in related technologies, flip-chip LEDs are typically deposited on a substrate by epitaxially layering n-GaN, an active layer, and p-GaN. Here, n-GaN is n-type gallium nitride, that is, gallium nitride GaN is doped with appropriate elements such as silicon (Si) to provide a higher electron concentration, and p-GaN is p-type gallium nitride, that is, gallium nitride GaN is doped with appropriate elements such as magnesium (Mg) to provide a higher hole concentration.

[0026] The bottom n-GaN is then exposed through etching to facilitate the subsequent deposition of n-type electrodes. Therefore, flip-chip LEDs require sacrificing the active layer area of ​​the etched portion, which reduces the utilization rate of the active layer of the entire LED chip.

[0027] It should also be noted that the LED chip in this application can be a flip-chip LED chip.

[0028] Figure 1 is a schematic diagram of an LED chip according to an embodiment of the present invention. In Figure 1: 1, substrate; 2, protective layer; 3, active layer; 4, transmission unit; 5, p-type transmission layer; 6, n-type transmission layer; 7, first conductive layer; 8, second conductive layer; 9, first electrode; 10, second electrode. As shown in Figure 1, the LED chip includes a substrate 1, a protective layer 2, an active layer 3, and a transmission unit 4 arranged sequentially from bottom to top. The transmission unit 4 includes a p-type transmission unit, which includes a p-type transmission layer 5 and a first conductive layer 7 located on the side of the p-type transmission layer away from the active layer; and an n-type transmission unit, which includes an n-type transmission layer 6 and a second conductive layer 8 located on the side of the n-type transmission layer away from the active layer. The p-type transmission layer 5 is electrically connected to the first electrode 9 through the corresponding first conductive layer 7, and the n-type transmission layer 6 is electrically connected to the second electrode 10 through the corresponding second conductive layer 8.

[0029] As an optional embodiment, an LED chip is provided, comprising: a substrate, a protective layer, an active layer, and a transmission unit arranged sequentially from bottom to top. The transmission unit includes a p-type transmission unit and an n-type transmission unit. The p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer. The p-type transmission layer is electrically connected to a first electrode through the first conductive layer. The n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer. The n-type transmission layer is electrically connected to a second electrode through the second conductive layer.

[0030] In this embodiment, an LED chip is provided, comprising, from bottom to top, a substrate, a protective layer, an active layer, and transmission units. The transmission units include p-type transmission units and n-type transmission units. The p-type transmission units are electrically connected to a first electrode through a corresponding first conductive layer, and the n-type transmission units are electrically connected to a second electrode through a corresponding second conductive layer. Since both the p-type and n-type transmission units are located on the active layer, and the first electrode can be electrically connected to the p-type transmission layer through the first conductive layer in the p-type transmission unit, and the second electrode can be electrically connected to the n-type transmission layer through the second conductive layer in the n-type transmission unit, the electrodes can be constructed without etching the active layer. This LED chip achieves the goal of having a light-emitting area equal to the bottom area of ​​the LED chip, thereby improving the utilization rate of the active layer and solving the technical problem of low active layer utilization in flip-chip LEDs in related technologies. (Note: The last sentence about low active layer utilization in flip-chip LEDs is unrelated and appears to be a separate, incomplete thought.)

[0031] It should be noted that the substrate material can be sapphire (Al₂O₃), silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs). The p-type transport layer material can be p-GaN, i.e., gallium nitride (GaN) doped with elements such as magnesium (Mg) to provide a higher hole concentration. The n-type transport layer material can be n-GaN, i.e., gallium nitride (GaN) doped with elements such as silicon (Si) to provide a higher electron concentration. The first conductive layer material can be a transparent conductive electrode indium tin oxide (ITO), fluorine-doped tin dioxide (SnO₂) conductive glass (FTO), or aluminum-doped zinc oxide (ZnO) conductive glass (AZO). Other conductive materials can also be used, such as silver nanowires, silver (Ag), aluminum (Al), and other highly reflective metals. The second conductive layer material can also be a transparent conductive electrode indium tin oxide (ITO), fluorine-doped tin dioxide (SnO₂) conductive glass (FTO), or aluminum-doped zinc oxide (ZnO) conductive glass (AZO). Other conductive materials can also be used, such as silver nanowires, silver (Ag), aluminum (Al), and other highly reflective metals. The materials of the first conductive layer and the second conductive layer can be the same. The material of the first electrode can be a metal, the material of the second electrode can be a metal, and the materials of the first electrode and the second electrode can be the same. Both the p-type transport layer and the n-type transport layer use common gallium nitride (GaN)-based transport layer materials for LED chips, and the deposition parameters are also conventional chip deposition parameters. It should be noted that the p-type transport layer and the n-type transport layer can be deposited in the same way, which is beneficial to the uniform deposition of the conductive layer on top of the transport layer.

[0032] As an optional embodiment, the protective layer includes a buffer layer and an insulating layer, wherein the buffer layer is located between the insulating layer and the substrate, and the insulating layer is used to block carriers transported in the active layer from entering the buffer layer, and the buffer layer is used to ensure that the lattice of the substrate matches the lattice of the epitaxial structure, the epitaxial structure including the protective layer, the active layer, and the transport unit.

[0033] In this embodiment, the buffer layer can be made of group III-V semiconductor materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and gallium arsenide (GaAs), or other high-temperature resistant inorganic compound materials with matching lattice constants. The buffer layer ensures lattice matching between the substrate and the epitaxial structure. Group III-V semiconductor materials are compounds composed of group IIIA and group VA elements. Group IIIA elements include boron, aluminum, gallium, indium, and thallium, while group VA elements include nitrogen, phosphorus, arsenic, antimony, and bismuth. The insulating layer can be made of group III-V gallium nitride (GaN)-based or gallium arsenide (GaAs)-based wide-bandgap semiconductors, or insulating materials. The insulating layer can be widened by doping or stress engineering to broaden the bandgap of the raw material, making the valence and conduction bands of the insulating layer sufficiently deep, resulting in a significant difference in band structure between the insulating layer and the active layer. This ensures that the insulating layer effectively blocks charge carriers, including electrons and holes. It is also important to note that the lattice of the insulating layer material must satisfy the requirements for good epitaxial growth of the upper active layer. When the protective layer includes a buffer layer, the lattice of the LED chip substrate matches the lattice of the epitaxial layer, ensuring better LED chip operation. When the protective layer includes an insulating layer, charge carriers only move in the active layer above the insulating layer and do not enter the insulating layer or the area below it. This structure ensures full utilization of charge carriers.

[0034] As an optional embodiment, there are multiple p-type transmission units and multiple n-type transmission units, wherein the multiple p-type transmission units and the multiple n-type transmission units are alternately arranged.

[0035] In this embodiment, with multiple p-type and n-type transmission units, and multiple p-type and n-type transmission units alternately arranged, the distribution of holes flowing through the p-type transmission units into the active layer and electrons flowing through the n-type transmission units into the active layer in the active layer is more uniform. Therefore, the positions where electrons and holes combine to form photons in the active layer are also more uniform, resulting in more uniform light emission from the active layer, that is, more uniform light emission from the LED chip.

[0036] As an optional embodiment, in a plurality of alternately arranged p-type transmission units and a plurality of n-type transmission units, two adjacent p-type transmission units share an n-type transmission unit in between them, and two adjacent n-type transmission units share a p-type transmission unit in between them.

[0037] In this embodiment, two adjacent p-type transmission units can share the middle n-type transmission unit. That is, electrons passing through the middle n-type transmission unit can combine with holes passing through the left p-type transmission unit to generate photons, and electrons passing through the middle n-type transmission unit can also combine with holes passing through the right p-type transmission unit to generate photons. Two adjacent n-type transmission units share the middle p-type transmission unit; that is, holes passing through the middle p-type transmission unit can combine with electrons passing through the left n-type transmission unit to generate photons, and holes passing through the middle p-type transmission unit can combine with electrons passing through the right n-type transmission unit to generate photons. Due to this property, each p-type transmission unit and each n-type transmission unit can be fully utilized, resulting in more uniform light emission from the active layer, i.e., more uniform light emission from the LED chip.

[0038] As an optional embodiment, the first electrode is used to inject holes and the second electrode is used to inject electrons.

[0039] In this embodiment, due to the performance difference between the p-type and n-type transmission units, the first electrode electrically connected to the p-type transmission unit is used to inject holes, and the second electrode electrically connected to the n-type transmission unit is used to inject electrons. With this structure, it can be ensured that holes and electrons are injected into the LED chip at the same time, so that the LED chip can work normally.

[0040] As an optional embodiment, the active layer is a quantum well active layer.

[0041] In this embodiment, the quantum well is a potential well on a microscale comparable to the de Broglie wavelength of an electron. It is a potential well for electrons or holes with a significant quantum confinement effect, formed by alternating layers of two different semiconductor materials. Because the active layer of a quantum well has advantages such as low frequency, low threshold current, narrow spectral linewidth, high output power, fast modulation speed, and wide temperature adaptability, the LED chip performs better when the active layer is a quantum well active layer.

[0042] As an optional embodiment, the protective layer includes a buffer layer, the dielectric constant of which is determined based on the doping elements of the buffer layer.

[0043] In this embodiment, since the buffer layer is located on the light-emitting surface of the LED chip, the optical dielectric constant of the buffer layer can be adjusted by doping it with different elements, thereby regulating the light coupling efficiency. Furthermore, buffer layers with different periodic structures (e.g., photonic crystal structures) can be grown to further adjust the optical coupling. For example, using a porous GaN buffer layer is beneficial for light coupling efficiency and concentrated light emission. The dielectric constant of the buffer layer is determined based on the doping elements; that is, the dielectric constant can be adjusted by doping with different elements to better suit actual needs, making the LED chip more suitable for practical requirements.

[0044] Example 2

[0045] According to an embodiment of the present invention, an embodiment of a method for fabricating an LED chip is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0046] Figure 2 is a flowchart of a method for preparing an LED chip according to an embodiment of the present invention. As shown in Figure 2, the method includes the following steps:

[0047] Step S202: Deposit a protective layer on the substrate;

[0048] In the technical solution provided by step S202 of the present invention, the protective layer can improve the performance of the LED chip.

[0049] Step S204: Deposit an active layer on the protective layer;

[0050] In the technical solution provided by step S204 of the present invention, electrons and holes combine in the active layer to obtain photons, thereby enabling the LED chip to emit light normally. The active layer is an essential part for the LED chip to emit light.

[0051] Step S206: Fabricate a transmission unit on the active layer, wherein the transmission unit includes a p-type transmission unit and an n-type transmission unit. The p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer. The n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer.

[0052] In the technical solution provided in step S206 of the present invention, holes can enter the active layer through p-type transport units, and electrons can enter the active layer through n-type transport units. By fabricating transport units, the LED chip can be ensured to work better.

[0053] Step S208: A first electrode is prepared on the first conductive layer, and a second conductive layer is prepared on the n-type transmission unit, and a second electrode is prepared on the second conductive layer to obtain an LED chip.

[0054] In the technical solution provided in step S208 of the present invention, the first electrode is used to inject holes, the second electrode is used to inject electrons, the first conductive layer can ensure more uniform hole injection, and the second conductive layer can ensure more uniform electron injection. The LED chip obtained in this way has better performance.

[0055] Through steps S202 to S208, a protective layer is first deposited on the substrate, then an active layer is deposited on the protective layer, and finally, transmission units are fabricated on the active layer. The transmission units include p-type and n-type transmission units. Each p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer. Each n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer. A first electrode is then fabricated on the first conductive layer, and a second electrode is fabricated on the second conductive layer, resulting in an LED chip. Because the first conductive layer ensures more uniform hole injection and the second conductive layer ensures more uniform electron injection, the LED chip emits light more uniformly. Since the electrodes can be constructed without etching the active layer, the utilization rate of the active layer in the LED chip is high, achieving the goal that the light-emitting area of ​​the LED chip is equal to the bottom area of ​​the LED chip. This achieves the technical effect of improving the utilization rate of the active layer of the LED chip, thereby solving the technical problem of low active layer utilization in flip-chip LEDs in related technologies.

[0056] As an optional embodiment, depositing a protective layer on a substrate includes: depositing a buffer layer on the substrate when the protective layer includes a buffer layer and an insulating layer; and depositing an insulating layer on the buffer layer.

[0057] In this embodiment, the insulating layer is used to prevent charge carriers transported in the active layer from entering the buffer layer, and the buffer layer is used to ensure that the lattice of the substrate matches the lattice of the epitaxial structure. By sequentially depositing the buffer layer and the active layer on the substrate, better performance of the LED chip can be ensured.

[0058] As an optional embodiment, fabricating a transmission unit on an active layer includes: depositing a p-type semiconductor layer on the active layer; depositing a first mask layer on the p-type semiconductor layer, wherein the first mask layer comprises an oxide layer; etching the first mask layer and the p-type semiconductor layer to form a first groove, wherein the first groove extends downward to the upper surface of the active layer, and obtaining a second mask layer and a p-type semiconductor intermediate layer; depositing a first n-type semiconductor layer on the second mask layer, and depositing a second n-type semiconductor layer on the exposed surface of the first groove on the active layer, wherein the second n-type semiconductor layer is connected to the p-type semiconductor intermediate layer; removing the second mask layer and the first n-type semiconductor layer; depositing a conductive layer on the second n-type semiconductor layer and the p-type semiconductor intermediate layer to obtain a transmission unit layer, wherein the transmission unit layer includes a second n-type semiconductor layer, a p-type semiconductor intermediate layer, and a conductive layer; dicing the transmission unit layer at a position corresponding to the connection between the second n-type semiconductor layer and the p-type semiconductor intermediate layer to separate the second n-type semiconductor layer from the p-type semiconductor intermediate layer, thereby obtaining a p-type transmission unit and an n-type transmission unit.

[0059] In this embodiment, the P-type semiconductor can be p-GaN, and the N-type semiconductor can be n-GaN. The material of the first mask layer can be high-temperature resistant aluminum oxide (Al2O3), or other high-temperature resistant and easily etchable oxide materials. After depositing the p-type semiconductor layer on the active layer, etching the first mask layer and the p-type semiconductor layer forms a first groove, which extends downward to the upper surface of the active layer. This means that only the selected area is etched, without affecting other areas, thus obtaining the desired second mask layer and p-type semiconductor intermediate layer. Depositing the N-type semiconductor at the top can be understood as depositing a first n-type semiconductor layer on the second mask layer. A second n-type semiconductor layer is deposited on the exposed surface of the first groove on the active layer, resulting in a second n-type semiconductor layer and a first n-type semiconductor layer. The second n-type semiconductor layer is connected to the p-type semiconductor intermediate layer. The second mask layer and the first n-type semiconductor layer are removed, and a conductive layer is deposited on the second n-type semiconductor layer and the p-type semiconductor interlayer to obtain a transmission unit layer. The transmission unit layer includes the second n-type semiconductor layer, the p-type semiconductor interlayer, and the conductive layer, with no gap between the p-type semiconductor interlayer and the second n-type semiconductor layer. Cuttings are made at the locations corresponding to the junctions of the second n-type semiconductor layer and the p-type semiconductor interlayer to separate them, resulting in p-type and n-type transmission units. This method allows for the rapid acquisition of high-quality transmission units at a lower cost.

[0060] Based on the above embodiments and optional embodiments, an optional implementation method is provided, which is described in detail below.

[0061] In related technologies, there is a problem of low utilization of the active layer of flip-chip LEDs.

[0062] In view of this, an optional embodiment of the present invention provides an LED chip with a high utilization rate of the active layer.

[0063] Figure 3 is a schematic diagram of the LED chip fabrication process provided by an optional embodiment of the present invention. In Figure 3, the structure corresponding to S1 from bottom to top is a substrate and a buffer layer; the structure corresponding to S2 from bottom to top is a substrate, a buffer layer, and an insulating layer; the structure corresponding to S3 from bottom to top is a substrate, a buffer layer, an insulating layer, and an active layer; the structure corresponding to S4 from bottom to top is a substrate, a buffer layer, an insulating layer, an active layer, and a p-type semiconductor layer; the structure corresponding to S5 from bottom to top is a substrate, a buffer layer, an insulating layer, an active layer, a p-type semiconductor layer, and a first mask layer; the structure corresponding to S6 from bottom to top is a substrate, a buffer layer, an insulating layer, an active layer, a p-type semiconductor intermediate layer, and a second mask layer; and the structure corresponding to S7 from bottom to top is... The structure from bottom to top in S8 consists of a substrate, a buffer layer, an insulating layer, an active layer, a layer including a p-type semiconductor layer and a p-type semiconductor interlayer, a second mask layer, and a first n-type semiconductor layer. The structure corresponding to S8 from bottom to top consists of a substrate, a buffer layer, an insulating layer, an active layer, and a layer including a p-type semiconductor layer and a p-type semiconductor interlayer. The structure corresponding to S9 from bottom to top consists of a substrate, a buffer layer, an insulating layer, an active layer, and a transmission unit layer. The structure corresponding to S10 from bottom to top consists of a substrate, a buffer layer, an insulating layer, an active layer, and a transmission unit. The structure corresponding to S11 from bottom to top consists of a substrate, a buffer layer, an insulating layer, an active layer, a transmission unit, and a transmission unit after electrode deposition, as shown in Figure 3. The process of fabricating this LED chip is as follows:

[0064] Take a common blue light chip as an example.

[0065] S1. A buffer layer is deposited on a conventional sapphire substrate. The purpose of the buffer layer is to alleviate the lattice stress generated by the subsequent growth of GaN-based materials. At the same time, the light-emitting coupling efficiency can be improved by selecting a buffer layer with a reasonable periodic structure and refractive index.

[0066] S2, then a blocking layer (equivalent to the insulating layer mentioned above) is deposited on the buffer layer to block charge carriers. The blocking layer is generally a wide bandgap semiconductor material based on GaN. At the same time, the valence band and conduction band depths of the blocking layer should be far away from the quantum well energy level, so as to block electrons and holes.

[0067] S3, deposit a quantum well active layer on the barrier layer. The quantum well layer (equivalent to the quantum well active layer mentioned above) can be a single layer or a conventional multilayer.

[0068] S4 and S5, then p-GaN (equivalent to the p-type semiconductor layer mentioned above) and Al2O3 mask (equivalent to the first mask layer mentioned above) are deposited sequentially on the quantum well active layer. The Al2O3 mask can withstand a high temperature of 2000 degrees and can maintain a stable masking effect during the subsequent high-temperature deposition process.

[0069] S6. The Al2O3 mask is etched by laser mask grooving, and a concave pattern is obtained by etching p-GaN (equivalent to etching the first mask layer and p-type semiconductor layer above to obtain the second mask layer and p-type semiconductor intermediate layer).

[0070] S7, then an n-GaN layer (equivalent to the second n-type semiconductor layer and the first n-type semiconductor layer mentioned above) is deposited on the etched chip surface;

[0071] S8, the remaining Al2O3 mask is then etched using a solution method. This process also removes the n-GaN deposited on the Al2O3 mask (equivalent to removing the second mask layer and the first n-type semiconductor layer mentioned above), leaving a layer of basically flat p-GaN (equivalent to the p-type semiconductor intermediate layer mentioned above) and n-GaN (equivalent to the second n-type semiconductor layer mentioned above) alternating layers.

[0072] S9, re-deposit an ITO conductive layer (equivalent to depositing a conductive layer on the intermediate layer between the second n-type semiconductor layer and the p-type semiconductor layer as mentioned above) to improve current injection efficiency and uniformity;

[0073] S10, then the p-GaN and n-GaN transport layers are isolated by laser grooving or etching to obtain p-type transport units and n-type transport units (equivalent to cutting the transport unit layer at the position corresponding to the connection between the second n-type semiconductor layer and the p-type semiconductor intermediate layer to separate the second n-type semiconductor layer and the p-type semiconductor intermediate layer, thus obtaining p-type transport units and n-type transport units).

[0074] S11, a first electrode is prepared on the first conductive layer, and a second electrode is prepared on the second conductive layer to obtain an LED chip, thus completing the preparation of the LED chip.

[0075] The specific steps and principles of this application will be further explained below with reference to specific embodiments:

[0076] The first step is to polish and clean the sapphire substrate (equivalent to the substrate mentioned above), and then deposit a 3μm undoped GaN layer on it as a buffer layer to ensure that the GaN lattice stress on its surface is reduced to a low level. Then, doped AlGaN is epitaxially grown on the GaN buffer layer as an insulating barrier layer (equivalent to the insulating layer mentioned above), with a thickness of 100nm, which plays a role in blocking injected electrons and holes, and at the same time provides a suitable epitaxial substrate for the quantum well structure.

[0077] The second step involves depositing a quantum well structure Al0.5Ga0.5N(5nm) / Al0.42Ga0.58N(2nm) / Al0.5Ga0.5N(5nm) on the insulating barrier layer as the active light-emitting layer of the chip (equivalent to the active layer mentioned above). Subsequently, a 400nm p-type AlGaN + a 10nm p-type heavily doped AlGaN (equivalent to the p-type semiconductor mentioned above) is deposited on the active layer as the p-type semiconductor layer.

[0078] The third step involves depositing a 300nm uniform and dense Al2O3 layer as a mask layer on the p-type semiconductor layer (equivalent to the first mask layer mentioned above). Then, the mask is grooved using laser etching. In this example, the LED chip contains only one n-type transport layer and two p-type transport layers; therefore, only the central region of the first mask layer and the p-type semiconductor layer needs to be etched using laser scribers. If a more uniform chip current injection is desired, multi-line laser grooving combined with interdigitated electrodes can be used, i.e., designing multiple n-type transport layers and multiple p-type transport layers. The exposed p-type transport layers are then etched until all p-type transport layers on the quantum well active layer are completely etched away.

[0079] The fourth step involves depositing a 410nm n-type Al0.64Ga0.36N (equivalent to the N-type semiconductor mentioned above) on the patterned chip as an n-type semiconductor layer (equivalent to the first and second n-type semiconductor layers mentioned above). The deposition parameters need to be adjusted to obtain a layer thickness comparable to the p-type semiconductor intermediate layer. Subsequently, the remaining Al2O3 mask layer is etched using hydrochloric acid immersion to remove the n-type transport layer deposited on the Al2O3 (equivalent to the first n-type conductor layer mentioned above), resulting in a patterned transport layer (equivalent to one of the second n-type semiconductor layer and the p-type semiconductor intermediate layer mentioned above).

[0080] The fifth step involves depositing a 150nm ITO conductive layer (equivalent to the conductive layer mentioned above) on the surface of the transport layer to ensure uniform current injection. Subsequently, laser grooving is used to separate the transport layers (equivalent to cutting the transport unit layer at the junction of the second n-type semiconductor layer and the p-type semiconductor interlayer, separating the p-type semiconductor interlayer and the second n-type semiconductor layer), ensuring that the injection of positive charge carriers only passes through the active layer and recombines within it for luminescence. Finally, metal electrodes (equivalent to the first and second electrodes mentioned above) are deposited onto the corresponding transport units to complete the fabrication of the LED chip, which can emit blue or green light.

[0081] It should be noted that in steps two through four above, the intrinsic GaN layer can also be deposited first, and then p-type and n-type doping of the GaN layer can be achieved by performing corresponding ion implantation methods, thereby realizing the p-GaN and n-GaN interleaved structure, that is, another way to obtain the transport layer mentioned above.

[0082] It should also be noted that in the fifth step above, the ITO conductive layer can be replaced with a highly reflective Ag conductive layer, so that the downward-emitted light is reflected upward and thus achieves higher light extraction efficiency.

[0083] It should also be noted that the material of the buffer layer can be replaced with AlGaN to enable the LED chip to emit purple light, and the material of the buffer layer can be replaced with GaAs to enable the LED chip to emit red light. Thus, by selecting different materials as buffer layers, LED chips with different emission colors can be fabricated.

[0084] Figure 4 is a schematic diagram of the working principle of the LED chip provided by an optional embodiment of the present invention. In Figure 4, the insulating barrier layer is equivalent to the insulating layer mentioned above, the sapphire substrate is equivalent to the substrate mentioned above, the electrode through which holes pass is the first electrode, the electrode through which electrons pass is the second electrode, the conductive layer through which holes pass is the first conductive layer, the conductive layer through which electrons pass is the second conductive layer, the broadband barrier layer is equivalent to the insulating layer mentioned above, which can restrict the movement of charge carriers to the quantum well active layer only, and the buffer layer can adjust the lattice stress responsible for GaN material growth and adjust the optical coupling. As shown in Figure 4, holes are injected from the first electrode and electrons are injected from the second electrode. Holes passing through the p-type transport layer on the left and electrons passing through the n-type transport layer in the middle can combine to form photons in the quantum well active layer. The photons pass through the buffer layer and emit light from the substrate, realizing the light emission of the LED chip.

[0085] The above optional implementation methods can achieve at least the following beneficial effects:

[0086] (1) The active layer has a high utilization rate and the LED chip has a large light-emitting area;

[0087] (2) The LED chip emits light uniformly;

[0088] (3) LED chips have good luminous efficiency, which can overcome the efficiency limitations of LED chips in related technologies;

[0089] (4) The dielectric constant of the buffer layer can be changed by doping with different elements, thereby adjusting the efficiency of optical coupling.

[0090] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0091] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0092] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0093] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The apparatus embodiments described above are merely illustrative.

[0095] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A light-emitting diode (LED) chip, characterized in that, include: The system comprises, from bottom to top, a substrate, a protective layer, an active layer, and transmission units. Each transmission unit includes p-type and n-type transmission units. A p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer. The p-type transmission layer is electrically connected to a first electrode through the first conductive layer. Each n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer. The n-type transmission layer is electrically connected to a second electrode through the second conductive layer. Multiple p-type and n-type transmission units are arranged alternately. In the alternately arranged p-type and n-type transmission units, adjacent p-type transmission units share an n-type transmission unit in between, and adjacent n-type units share a p-type transmission unit in between.

2. The LED chip according to claim 1, characterized in that, The protective layer includes a buffer layer and an insulating layer. The buffer layer is located between the insulating layer and the substrate. The insulating layer is used to block charge carriers transported in the active layer from entering the buffer layer. The buffer layer is used to ensure that the lattice of the substrate matches the lattice of the epitaxial structure. The epitaxial structure includes the protective layer, the active layer, and the transport unit.

3. The LED chip according to claim 1, characterized in that, The first electrode is used to inject holes, and the second electrode is used to inject electrons.

4. The LED chip according to claim 1, characterized in that, The active layer is a quantum well active layer.

5. The LED chip according to any one of claims 1 to 4, characterized in that, The protective layer includes a buffer layer, and the dielectric constant of the buffer layer is determined based on the doping elements of the buffer layer.

6. A method for preparing the LED chip according to claim 1, characterized in that, include: A protective layer is deposited on a substrate; an active layer is deposited on the protective layer; a transmission unit is fabricated on the active layer, wherein the transmission unit includes a p-type transmission unit and an n-type transmission unit, the p-type transmission unit includes a p-type transmission layer and a first conductive layer located on the side of the p-type transmission layer away from the active layer, and the n-type transmission unit includes an n-type transmission layer and a second conductive layer located on the side of the n-type transmission layer away from the active layer; a first electrode is fabricated on the first conductive layer, and a second electrode is fabricated on the second conductive layer to obtain an LED chip.

7. The method according to claim 6, characterized in that, The method of depositing a protective layer on a substrate includes: depositing the buffer layer on the substrate when the protective layer includes a buffer layer and an insulating layer; and depositing the insulating layer on the buffer layer.

8. The method according to claim 6, characterized in that, The fabrication of a transmission unit on the active layer includes: depositing a p-type semiconductor layer on the active layer; depositing a first mask layer on the p-type semiconductor layer; etching the first mask layer and the p-type semiconductor layer to form a first groove, wherein the first groove extends downward to the upper surface of the active layer, and a second mask layer and a p-type semiconductor intermediate layer are obtained; depositing a first n-type semiconductor layer on the second mask layer; depositing a second n-type semiconductor layer on the exposed surface of the first groove on the active layer, wherein the second n-type semiconductor layer is connected to the p-type semiconductor intermediate layer; removing the second mask layer and the first n-type semiconductor layer; depositing a conductive layer on the second n-type semiconductor layer and the p-type semiconductor intermediate layer to obtain a transmission unit layer, wherein the transmission unit layer includes the second n-type semiconductor layer, the p-type semiconductor intermediate layer, and the conductive layer; cutting the transmission unit layer at a position corresponding to the connection between the second n-type semiconductor layer and the p-type semiconductor intermediate layer to separate the second n-type semiconductor layer from the p-type semiconductor intermediate layer, thereby obtaining the p-type transmission unit and the n-type transmission unit.

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