A radiation-hardened latch circuit and module using source isolation hardening and polarity hardening

Abstract

The application relates to the technical field of integrated circuit design, in particular to an anti-radiation Latch circuit using source isolation reinforcement and polarity reinforcement and a module packaged based on the anti-radiation Latch circuit. The storage nodes X1, X2, X5 and X6 are surrounded by NMOS transistors to form polarity reinforcement, so that X1, X2, X5 and X6 effectively avoid flip. The application uses source isolation technology, so that only '1-0' and '0-0' voltage pulses are generated on the X0, X3, X4 and X7 nodes, the number of sensitive nodes of the circuit can be effectively reduced, and the stability of the circuit is improved. The application constructs a C unit, the structure of which is simple and has good anti-radiation capability, and the C unit can cooperate to ensure the correct output of Q when multiple nodes are bombarded. The anti-radiation Latch circuit has complete anti-TNU, DNU and SNU capability, and has low delay, low power consumption and small area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and more particularly, to an anti-radiation latch circuit (which can be referred to as a TNURH latch unit) using source isolation and polarity reinforcement, and a module packaged based on the anti-radiation latch circuit. BACKGROUND

[0002] With the rapid development of metal-oxide-semiconductor (CMOS) technology, modern integrated circuits are increasingly vulnerable to reliability problems caused by soft errors. Soft errors are a kind of transient errors, mainly caused by neutron, proton, heavy ion, alpha particle, electron, etc.

[0003] In nanometer CMOS technology, a single particle impact can change the logic state of a single node in a storage cell, resulting in single-node upset (SNU). However, in highly integrated nanometer CMOS technology, due to charge sharing, a high-energy particle impact can simultaneously change the logic state of adjacent double nodes or even triple nodes, resulting in multi-node upset (MNU), including double-node upset (DNU) and triple-node upset (TNU). Obviously, radiation hardening for SNU alone is not enough to meet the requirements of safety-critical aerospace applications that require high reliability.

[0004] In order to improve the ability of the unit to resist multi-node upset, the prior art mainly includes the following schemes:

[0005] 1) as shown in the structure unit based on DICE structure (referred to as RH latch unit), a total of 6 internal nodes, and a polarity reinforcement technology is used for part of the nodes, which has the ability to resist double-node upset, and a fast data channel is used to reduce transmission delay, but the power consumption of the circuit is large. Figure 1

[0006] 2) as shown in the double-node upset tolerant latch (referred to as HRDNUT unit) and as shown in the triple-node upset tolerant latch (referred to as TNU-latch unit) that can simultaneously resist triple-node upset. Among them, HRDNUT uses transistor stacking technology to reduce power consumption, and the recovery function of the unit after particle bombardment is obviously superior to previous designs under the working condition of the latch unit, and the power consumption of the circuit is small, but the delay of the unit is large; TNU-latch also uses transistor stacking technology, because after an error occurs, no node remains in a high impedance state, so there is no need for additional output circuit to save data, but the unit uses a large number of transistors to ensure the performance of the latch unit against single event triple-node upset, so the area overhead is large, and the delay of the unit is also relatively large. Figure 2 Figure 3 ​​​

[0007] 3) such as Figure 4 The radiation-hardened polarity latch (RHPDL cell) shown here uses all NMOS transistors or all PMOS transistors to surround the internal storage nodes, which reduces the number of sensitive nodes, improves circuit stability, and enables the circuit to resist dual-node flipping. It uses a fast data channel and has low transmission delay, but the power consumption is relatively high. Summary of the Invention

[0008] Therefore, it is necessary to provide a radiation-hardened latch circuit and module that utilizes source isolation hardening and polarity hardening to address the problem that existing latches cannot achieve a good match in terms of node flip-flop resistance, power consumption, area overhead, and latency.

[0009] This invention is achieved using the following technical solution:

[0010] In a first aspect, the present invention provides a radiation-hardened latch circuit that utilizes source isolation hardening and polarity hardening, comprising a pull-up diode section, a pull-down diode section, an inverter I, an inverter II, a transmission diode section, a C-cell section, and a transmission gate.

[0011] The pull-up section includes 12 PMOS transistors P1-P12 and 4 NMOS transistors N1-N4, used to pull up memory nodes X0, X1, X2, X3, X4, X5, X6, and X7. The pull-down section includes 7 NMOS transistors N5-N12, used to pull down memory nodes X0, X1, X2, X3, X4, X5, X6, and X7. X1, X2, X5, and X6 are all surrounded by NMOS transistors, forming polarity hardening. P1 and P9, P4 and P10, P5 and P11, and P8 and P12 form source isolation hardening.

[0012] Inverter 1 includes one NMOS transistor N20 and one PMOS transistor P20, used to invert the clock signal CLK into the clock signal NCK. Inverter 2 includes one NMOS transistor N21 and one PMOS transistor P21, used to invert the input signal D into the input signal DN. The transmission section includes seven NMOS transistors N23 to N30, all connected to the clock signal CLK. Specifically, X0, X2, X4, and X6 are connected to D via N23, N25, N27, and N29 respectively, and X1, X3, X5, and X7 are connected to DN via N24, N26, N28, and N30 respectively.

[0013] The C unit part includes C unit one, C unit two and C unit three.The C unit one includes two PMOS transistors P13-P14 and two NMOS transistors N13-N14, and is used for outputting an intermediate signal n1 according to X3 and X5.The C unit two includes two PMOS transistors P15-P16 and two NMOS transistors N15-N16, and is used for outputting an intermediate signal n2 according to X7 and X1.The C unit three includes three PMOS transistors P17-P19 and three NMOS transistors N17-N19, and is used for outputting an output signal Q according to n1, n2, CLK and NCK.

[0014] The transmission gate includes one NMOS transistor N22 and one PMOS transistor P22, and is used for being opened or closed according to CLK and NCK.When CLK=1, the transmission gate is opened, the anti-radiation latch circuit is in a transparent mode, and D is directly output to Q through the transmission gate.When CLK=0, the transmission gate is closed, the anti-radiation latch circuit is in a holding mode, and D and DN are stored in X0, X1, X2, X3, X4, X5, X6 and X7, and are output to Q through the C unit part.

[0015] The anti-radiation latch circuit is implemented by using the source isolation reinforcement and the polarity reinforcement, and the implementation of the anti-radiation latch circuit is implemented according to the method or process of the embodiment of the present disclosure.

[0016] In the second aspect, the present application discloses an anti-radiation latch module which is packaged by using the anti-radiation latch circuit disclosed in the first aspect.

[0017] The anti-radiation latch module is implemented according to the method or process of the embodiment of the present disclosure.

[0018] Compared with the prior art, the present application has the following beneficial effects:

[0019] 1.The storage nodes X1, X2, X5 and X6 of the present application are surrounded by NMOS transistors, forming polarity reinforcement, so that even if the sensitive nodes NMOS are bombarded by space particles, only "1-0" and "0-0" negative pulses are generated on X1, X2, X5 and X6, and the pulses cannot affect the state of other transistors due to the existence of gate capacitance, which makes X1, X2, X5 and X6 effectively avoid flipping.

[0020] 2.The source isolation technology is used in the present application, so that only "1-0" and "0-0" voltage pulses are generated on X0, X3, X4 and X7 nodes, which can effectively reduce the number of sensitive nodes of the circuit and improve the stability of the circuit; if other non-critical nodes are bombarded by particles, the entire circuit is less likely to be affected.

[0021] 3, The application constructs C unit, which has simple structure and good anti-radiation ability; when input is same, it is equivalent to inverter, and output is inverse of input; when input is different, output keeps last value, which can ensure correct output of Q when multiple nodes are bombarded. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 The circuit structure diagram of the RH latch unit mentioned in the background art of the present application;

[0024] Figure 2 The circuit structure diagram of the HRDNUT unit mentioned in the background art of the present application;

[0025] Figure 3 The circuit structure diagram of the TNU-latch unit mentioned in the background art of the present application;

[0026] Figure 4 The circuit structure diagram of the RHPDL unit mentioned in the background art of the present application;

[0027] Figure 5 The circuit structure diagram of the TNURH latch unit provided in the embodiment 1 of the present application;

[0028] Figure 6 The anti-single-node bombardment timing waveform diagram of the TNURH latch unit of Figure 5

[0029] The anti-double-node bombardment timing waveform diagram of the TNURH latch unit of Figure 7 Figure 5 The anti-triple-node bombardment timing waveform diagram of the TNURH latch unit of

[0030] Figure 8 Figure 5 The anti-triple-node bombardment timing waveform diagram of the TNURH latch unit of

[0031] Figure 9 The delay time comparison diagram of the TNURH latch unit of Figure 5

[0032] The delay time comparison diagram of the TNURH latch unit of Figure 10 Figure 5 ​​​Fig. 2 is a comparison chart of static power consumption of the TNURH latch unit and other four kinds of latches. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0034] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Embodiment 1

[0037] Referring to Figure 5 Fig. 1 is a circuit structure diagram of a TNURH latch unit provided for Embodiment 1. Generally, the TNURH latch unit includes 30 NMOS transistors and 22 PMOS transistors. The 30 NMOS transistors are sequentially denoted as N1-N30, and the 22 PMOS transistors are sequentially denoted as P1-P22.

[0038] The input signal D is connected to the source of N24, the source of N26, the source of N28, the source of N30, the drain of N22, the drain of P22, the gate of P21, and the gate of N21. The input signal DN is the inverse signal of D, and is connected to the source of N23, the source of N25, the source of N27, the source of N29, the drain of P21, and the drain of N21. The clock signal CLK is connected to the gate of N23-N30, the gate of P19, the gate of P20, the gate of N20, and the gate of N22. The clock signal NCK is the inverse signal of CLK, and is connected to the gate of N17, the gate of P22, the drain of P20, and the drain of N20. The output signal Q is connected to the source of N22, the source of P22, the drain of P19, and the drain of N17.

[0039] The drains of N23-N30 are connected to the drains of N5-N12, respectively. The sources of P1-P8, P13, P15, P17, P20, and P21 are connected to VDD, and the sources of N5-N12, N14, N16, N19, N20, and N21 are connected to ground GND.

[0040] The drain of P1 is connected to the source of P9, and the gate of P1 is connected to the gate of N1, the gate of P3, the drain of P10, and the drain of N8. The drain of P2 is connected to the drain of N1, and the gate of P2 is connected to the gate of P4, the gate of N8, the source of N2, the drain of N7, the gate of P13, and the gate of N13. The drain of P3 is connected to the drain of N2. The drain of P4 is connected to the source of P10. The gate of P9 is connected to the gate of N5, the gate of N7, the source of N1, the drain of N6, the gate of P16, and the gate of N16. The gate of N2 is connected to the gate of P10, the gate of N6, the drain of P9, and the drain of N5.

[0041] The drain of P5 is connected to the source of P11. The gate of P5 is connected to the gate of N3, the gate of P7, the drain of P12, the drain of N12, the gate of P15, and the gate of N15. The drain of P6 is connected to the drain of N3. The gate of P6 is connected to the gate of P8, the gate of N12, the source of N4, and the drain of N11. The drain of P7 is connected to the drain of N4, and the drain of P8 is connected to the source of P12. The gate of P11 is connected to the gate of N9, the gate of N11, the source of N3, the drain of N10, the gate of P14, and the gate of N14. The gate of N4 is connected to the gate of P12, the gate of N10, the drain of P11, and the drain of N9.

[0042] The drain of P13 is connected with the source of P14. The source of N13 is connected with the drain of N14. The drain of P14 is connected with the drain of N13, the gate of P17, the gate of N18. The drain of P15 is connected with the source of P16. The source of N15 is connected with the drain of N16, the drain of P16 is connected with the drain of N15, the gate of P18, the gate of N19.

[0043] In terms of function, the TNURH latch unit includes a pull-up tube part, a pull-down tube part, an inverter one, an inverter two, a transmission tube part, a C unit part, and a transmission gate.

[0044] Among them, 12 PMOS transistors P1-P12 and 4 NMOS transistors N1-N4 are used as pull-up tubes to form a pull-up tube part, and pull-up storage nodes X0, X1, X2, X3, X4, X5, X6, X7 are formed. 7 NMOS transistors N5-N12 are used as pull-down tubes to form a pull-down tube part, and pull-down storage nodes X0, X1, X2, X3, X4, X5, X6, X7 are formed.

[0045] Specifically, the sources of P1, P2, P3, P4, P5, P6, P7, and P8 are connected to VDD; the sources of N5, N6, N7, N8, N9, N10, N11, and N12 are connected to ground GND.

[0046] X0 is connected to the gate of N2, the gate of N6, the gate of P10, the drain of P9, and the drain of N5;

[0047] X1 is connected to the gate of P9, the gate of N5, the drain of N1, and the drain of N6;

[0048] X2 is connected to the gate of P2, the gate of P4, the gate of N8, the drain of N2, and the drain of N7;

[0049] X3 is connected to the gate of P1, the gate of P3, the gate of N1, the gate of N7, the drain of P10, and the drain of N8;

[0050] X4 is connected to the gate of N4, the gate of P12, the gate of N10, the drain of P11, and the drain of N9;

[0051] X5 is connected to the gate of P11, the gate of N9, the drain of N3, and the drain of N10;

[0052] X6 is connected to the gate of P6, the gate of P8, the gate of N12, the drain of N4, and the drain of N11;

[0053] X7 is connected to the gate of P5, the gate of P7, the gate of N3, the gate of N11, the drain of P12, and the drain of N12.

[0054] X1, X2, X5, X6 are surrounded by NMOS transistors, forming a polar reinforcement, more specifically referred to as N-type polar reinforcement structure. According to the principle of polar reinforcement, the space particle bombards the sensitive node NMOS tube, only generates "1-0" and "0-0" voltage pulse on X1, X2, X5, X6, that is, only negative pulse will be generated, and the pulse cannot affect the state of other transistors due to the existence of gate capacitance, which makes X1, X2, X5, X6 effectively avoid flip.

[0055] P1 and P9 are stacked, that is, the uppermost PMOS transistor is isolated from the PMOS transistor below by using shallow trench isolation technology, forming source isolation reinforcement. P4 and P10, P5 and P11, P8 and P12 also form source isolation reinforcement in the same way. Only "1-0" and "0-0" voltage pulses will be generated on X0, X3, X4, X7, that is, only negative pulses will be generated, and the pulse cannot affect the state of other transistors due to the existence of gate capacitance, which makes X0, X3, X4, X7 effectively avoid flip.

[0056] 1 NMOS transistor N20 and 1 PMOS transistor P20 constitute an inverter one, which is used to invert the clock signal CLK into the clock signal NCK. 1 NMOS transistor N21 and 1 PMOS transistor P21 constitute an inverter two, which is used to invert the input signal D into the input signal DN.

[0057] Specifically, the source of P20 is connected to VDD, the gate is connected to CLK, and the drain is connected to NCK; the source of N20 is connected to ground GND, the gate is connected to the gate of P20, and the drain is connected to the drain of P20. The source of P21 is connected to VDD, the gate is connected to D, and the drain is connected to DN; the source of N21 is connected to ground GND, the gate is connected to the gate of P21, and the drain is connected to the drain of P21.

[0058] 7 NMOS transistors N23-N30 constitute a transmission tube part. N23-N30 are all connected to the clock signal CLK. X0, X2, X4, X6 are connected to D through N23, N25, N27, N29 respectively, and X1, X3, X5, X7 are connected to DN through N24, N26, N28, N30 respectively.

[0059] Specifically, the gates of N23, N24, N25, N26, N27, N28, N29, N30 are connected to CLK; the drain of N23 is connected to X0, and the source is connected to DN; the drain of N24 is connected to X1, and the source is connected to D; the drain of N25 is connected to X2, and the source is connected to DN; the drain of N26 is connected to X3, and the source is connected to D; the drain of N27 is connected to X4, and the source is connected to DN; the drain of N28 is connected to X5, and the source is connected to D; the drain of N29 is connected to X6, and the source is connected to DN; the drain of N30 is connected to X7, and the source is connected to D.

[0060] The C unit part includes three C units. Among them, 2 PMOS transistors P13-P14, 2 NMOS transistors N13-N14 constitute C unit one (referred to as CE1), for outputting intermediate signal n1 according to X3, X5. 2 PMOS transistors P15-P16, 2 NMOS transistors N15-N16 constitute C unit two (referred to as CE2), for outputting intermediate signal n2 according to X7, X1. 3 PMOS transistors P17-P19, 3 NMOS transistors N17-N19 constitute C unit three (referred to as CE3), for outputting output signal Q (also referred to as output node) according to n1, n2, CLK, NCK.

[0061] When the input values of the C unit are the same, the CE acts as an inverter. However, when the input values of the C unit change, its output can temporarily maintain the previous value (enter a high impedance state). This means that if the change in the value of the C unit input is caused by an error, the C unit can intercept this error. It should be noted that CE3 is controlled by CLK, NCK.

[0062] Specifically, the source of P13 is connected to VDD, and the gate is connected to X3; the source of P14 is connected to the drain of P13, the gate is connected to X5, and the drain is connected to n1; the drain of N13 is connected to the drain of P14, and the gate is connected to X3; the source of N14 is connected to ground GND, the gate is connected to X5, and the drain is connected to the source of N13.

[0063] The source of P15 is connected to VDD, and the gate is connected to X7; the source of P16 is connected to the drain of P15, the gate is connected to X1, and the drain is connected to n2; the drain of N15 is connected to the drain of P16, and the gate is connected to X7; the source of N16 is connected to ground GND, the gate is connected to X1, and the drain is connected to the source of N15.

[0064] The source of P17 is connected to VDD, and the gate is connected to n1; the source of P18 is connected to the drain of P17, and the gate is connected to n2; the source of P19 is connected to the drain of P18, and the gate is connected to CLK; the drain of N17 is connected to the drain of P19, and the gate is connected to NCK; the drain of N18 is connected to the source of N17, and the gate is connected to n1; the source of N19 is connected to ground GND, the gate is connected to n2, and the drain is connected to the source of N18.

[0065] 1 NMOS transistor N22, 1 PMOS transistor P22 constitute a transmission gate, for opening or closing according to CLK, NCK:

[0066] Specifically, the gate of N22 is connected to CLK, the drain is connected to D, and the source is connected to Q; the gate of P22 is connected to NCK, the drain is connected to the source of N22, and the source is connected to the drain of N22.

[0067] When CLK = 1, the transmission gate is opened, the anti-radiation latch circuit is in transparent mode, and D is directly output to Q through the transmission gate. Therefore, P19 and N17 are closed at this time. Taking D = 1 as an example, when X1 = X3 = X5 = X7 = 1 and X0 = X2 = X4 = X6 = 0, P9, P1, P3, P11, P5, and P7 are opened, and N5, N1, N7, N9, N3, and N11 are closed. Therefore, the feedback loop is quickly established, and the internal storage nodes can be latched to keep the storage values unchanged unless the input D drops to the bottom (i.e., 0).

[0068] When CLK = 0, the transmission gate is closed, and the anti-radiation latch circuit is in hold mode. D and DN are stored in X0, X1, X2, X3, X4, X5, X6, and X7, and are output to Q through the C unit. N23 to N30 are closed, and the transmission gate is no longer written with values. Therefore, the internal nodes keep the previous storage values unchanged, and the path from D to Q is interrupted. The C unit is enabled, and the corresponding storage values are output to Q through the C unit. Therefore, the latched value on Q will be retained until the next transparent mode occurs.

[0069] The bombardment occurs in the hold mode (CLK = 0, NCK = 1, and P19 and N20 in CE3 are opened at this time). In general, when the storage nodes are bombarded, the TNURH latch unit either restores the storage nodes or, even if part of the storage nodes cannot be restored, performs fault tolerance through the action of the C unit (mainly CE1 and CE2 perform fault tolerance) to ensure the correct output of Q.

[0070] In this embodiment 1, the gate length of all MOS transistors is 65 nm, the gate width of all PMOS transistors is 140 nm, and the gate width of N5, N8, N9, N12, N14, and N16 is 280 nm. The gate width of other NMOS transistors is 140 nm. It should be noted that when X1 = 1 or X2 = 1, the use of stacked transistors to lower the voltage of node X1 or X2 will cause threshold loss. In order to reduce the leakage current, the size of N5 and N8 is increased to twice the minimum size (140 nm) to offset the threshold loss, that is, to provide stronger pull-down driving capability.

[0071] Taking the storage data X1 = X3 = X5 = X7 = 1 and X0 = X2 = X4 = X6 = 0 as an example, P9, P1, P3, P11, P5, and P7 are opened, and N5, N1, N7, N9, N3, and N11 are closed.

[0072] (1) As Figure 6As shown, X0, X1, X2, X3, X4, X5, X6, X7 are bombarded separately, and all can realize recovery, thus ensuring the correct output of Q. It is illustrated that the TNURH latch unit has the ability to resist SNU.

[0073] Taking X1 as an example, X1 occurs "1" to "0" flip, P9 is opened, and N5 is closed; because P1 is closed, X0 remains 0, and X2, X3, X4, X5, X6, X7 are not affected by the X1 node and remain their own values unchanged, so P2, N1 are still opened, N6 is still closed, and X1 will be pulled back to 1 by P2, N1, so that the values of all nodes remain correct. The rest is similar and will not be repeated.

[0074] (2) As shown in Figure 7 Any two of X0, X1, X2, X3, X4, X5, X6, X7 are bombarded:

[0075] Since the left and right of the transmission tube are the same, only three cases need to be considered,

[0076] Case 1: Each of the transmission tube has one storage node bombarded, and both can be recovered by other nodes, so it will not affect the correct output of Q.

[0077] Taking <X1, X5> as an example, X1, X5 occurs "1" to "0" flip, P9, P11 is opened, N5, N9 is closed; because P1, P5 is closed, X0, X4 remains 0, and X2, X3, X4, X6, X7 are not affected by the X1 node and remain their own values unchanged, so P2, N1, P6, N3 are still opened, N6, N10 are still closed, X1 will be pulled back to 1 by P2, N1, and X5 will be pulled back to 1 by P6, N3, so that the values of all nodes remain correct. The rest is similar and will not be repeated.

[0078] Case 2: Both bombarded nodes occur on the left side of the transmission tube or on the right side of the transmission tube, although it will cause some nodes to flip, but it will not affect the storage value of the other part of the node. And because CE1, CE2 intercepts the error and covers the error value, CE1 and CE2 output n1, n2 are still correct, so Q can maintain the correct output.

[0079] Take <X1, X3> being hit as an example, X1 and X3 are flipped from "1" to "0", P1, P3 and P9 are opened, N1, N5 and N7 are closed, X0 will be pulled up to 1 by P1 and P9, X0 becoming 1 will make N2 and N6 open, P10 close, X2 will be pulled up to 1 by P3 and N2, X2 becoming 1 will make P2 and P4 close and N8 open, finally X1 and X3 cannot be pulled back to 1 by the pull-up tube, resulting in the storage values of X0, X1, X2 and X3 being flipped and unable to be recovered, but X4, X5, X6 and X7 are not affected and keep their correct storage values.

[0080] Since the C unit is equivalent to an inverter when the inputs are the same, the output is the inverse of the input; when the inputs are different, the output remains the same as the previous value. Specifically, the input X3 of CE1 and the input X1 of CE2 have both been flipped, but because X5 and X7 are correct storage values, the inputs of CE1 and CE2 are not the same, so the outputs of CE1 and CE2 remain the same as the previous value, that is, n1 and n2 remain unchanged, so Q also guarantees correct output. The remaining cases are similar and will not be repeated.

[0081] Of course, there is a special case 3: one node in the transmission tube part is hit, the output node Q is hit, and the hit node can be restored to correct by the adjustment of other nodes in the transmission tube part, and all the internal storage node values are correct, so Q output can be kept correct.

[0082] Take <X1, Q> being hit as an example, X1 and Q are flipped from "1" to "0", which is equivalent to a single-node flip of X1 inside. As can be seen from the above analysis, a single-node flip of X1 inside can be recovered, and all the internal storage node values can remain correct, so the inputs of the C unit part are all correct, and therefore the final output Q can also be guaranteed to be correct. The remaining cases are similar and will not be repeated.

[0083] The cases in Figure 7 are summarized in Table 1:

[0084] Table 1: Cases after double-node hit

[0085]

[0086]

[0087] Although Table 1 is not exhaustive, it can already demonstrate that the TNURH latch unit has the ability to resist DNU.

[0088] (3) As in Figure 8 Figure 8 ​​Any three of X0, X1, X2, X3, X4, X5, X6, X7 are bombarded.

[0089] Consider three cases:

[0090] Case 1: Three nodes in the transmission tube are bombarded, although it will cause some nodes to flip, but it will not affect the storage value of another part of the node, and after the error interception of the C unit, the output Q can be guaranteed to be correct.

[0091] Taking the case that <X1, X3, X5> is bombarded as an example, X1, X3, X5 occur "1" to "0" flip, P1, P3, P9, P11 are opened, N1, N5, N7, N9 are closed, X0 will be pulled up to 1 by P1, P9. X0 becomes 1 will make N2, N6 open, P10 closed, X2 will be pulled up to 1 by P3, N2. X2 becomes 1 will make P2, P4 closed, N8 opened, finally X1, X3 cannot be pulled back to 1 through the pull-up tube, resulting in the storage values of X0, X1, X2, X3 four nodes are all flipped and cannot be recovered. But X4, X6, X7 are not affected and maintain the original correct storage value, so X5 point will be pulled back to 1 by P6, N3, so X4, X5, X6, X7 can maintain the correct value.

[0092] The input X3 of CE1 and the input X1 of CE2 have both flipped, but because X5, X7 maintain the correct storage value, so that the inputs of CE1 and CE2 are not the same, so the outputs of CE1, CE2 remain the same as the last value, and n1, n2 also remain unchanged, so Q is guaranteed to output correctly. The rest of the cases are similar and will not be repeated.

[0093] Case 2: Two nodes inside the transmission tube (one on the left and one on the right of the transmission tube) are bombarded and the output node Q is bombarded. Because of the adjustment function inside the transmission tube, the values of the internal storage nodes can all be kept correct, so the output Q can also be kept correct.

[0094] Taking the case that <X1, X5, Q> is bombarded as an example, X1, X5, Q occur "1" to "0" flip, P9, P11 are opened, N5, N9 are closed. Because P1, P5 are closed, X0, X4 remain 0, and X2, X3, X4, X6, X7 are not affected by X1 node and also maintain their own values unchanged, so P2, N1, P6, N3 are still opened, N6, N10 are still closed, X1 point will be pulled back to 1 by P2, N1, X5 point will be pulled back to 1 by P6, N3, so finally all the values of the internal storage nodes are correct. Then the inputs of the C unit are all correct, so the final output Q can also be guaranteed to be correct. The rest of the cases are similar and will not be repeated.

[0095] Scenario 3: Two nodes inside the transmission tube (both occurring on the same side of the transmission tube) are bombarded and the output node Q is bombarded. Although this will cause some nodes to flip, it will not affect the stored values ​​of the other nodes. After error interception by the C unit, the output Q can be guaranteed to be correct.

[0096] by<X1,X3,Q> Taking an attack as an example, X1, X3, and Q undergo a flip from "1" to "0". P1, P3, and P9 turn on, while N1, N5, and N7 turn off. X0 is pulled up to 1 by P1 and P9. X0 becoming 1 causes N2 and N6 to turn on, P10 to turn off, and X2 is pulled up to 1 by P3 and N2. X2 becoming 1 causes P2 and P4 to turn off, and N8 to turn on. Ultimately, X1 and X3 cannot be pulled back to 1 by the pull-up tubes, resulting in the stored values ​​of all four nodes X0, X1, X2, and X3 being flipped and unrecoverable. However, X4, X5, X6, and X7 remain unaffected and retain their correct stored values.

[0097] Both inputs X3 to CE1 and X1 to CE2 are flipped. However, since X5 and X7 retain their correct stored values, the inputs to CE1 and CE2 are different. Therefore, the outputs of CE1 and CE2 remain unchanged from their previous values. Consequently, n1 and n2 also remain unchanged, ensuring that the output Q is correctly output. Other cases are similar and will not be elaborated further.

[0098] right Figure 8 The following is a summary of the situation, as detailed in Table 2:

[0099] Table 2 shows the situation after nodes 2 and 3 were bombarded.

[0100]

[0101] Although Table 2 does not exhaustively list all cases, it is sufficient to demonstrate that the TNU H latch unit has the ability to resist TNU.

[0102] In addition, the inventors also conducted simulation comparisons of the TNURH latch unit with four types of latches proposed in the background technology.

[0103] First, refer to Table 3, which is a comparison table of anti-tumble capabilities.

[0104] Table 3 Comparison of Anti-Tilting Capacity

[0105]

[0106] Clearly, only TNU-latch and TNURH latch have full TNU / DNU / SNU protection. However, TNU-latch requires 80 MOSFETs to build, while TNURH latch only requires 52 MOSFETs, significantly reducing area overhead.

[0107] Then, referring to Figure 9 , the delay of the TNURH latch unit is the same as that of the RH latch, RHPDL, and slightly less than that of the HRDNUT, and significantly less than that of the TNU-latch. It is shown that the TNURH latch unit has the advantage of low delay while having complete anti-TNU / DNU / SNU capability.

[0108] Referring again to Figure 10 , the power consumption of the TNURH latch unit is the lowest among the five units. It is shown that the TNURH latch unit has the advantage of low power consumption while having complete anti-TNU / DNU / SNU capability.

[0109] Embodiment 2

[0110] This embodiment 2 discloses an anti-radiation Latch module, which is packaged by the anti-radiation Latch circuit of embodiment 1. The mode of packaging into a module is more conducive to the popularization and application of the anti-radiation Latch circuit.

[0111] The pins of the anti-radiation Latch module include five pins: a first pin, a second pin, a third pin, a fourth pin, and a fifth pin.

[0112] The first pin is used for connecting VDD. Specifically, the first pin is connected to the source electrodes of P1, P2, P3, P4, P5, P6, P7, P8, P13, P15, P17, P20, and P21.

[0113] The second pin is used for grounding GND. Specifically, the second pin is connected to the source electrodes of N5, N6, N7, N8, N9, N10, N11, N12, N14, N16, N19, N20, and N21.

[0114] The third pin is used for inputting a clock signal CLK. Specifically, the third pin is connected to the gate electrodes of P19, P20, N20, N22, N23, N24, N25, N26, N27, N28, N29, and N30.

[0115] The fourth pin is used for inputting an input signal D. Specifically, the fourth pin is connected to the gate electrodes of P21 and N21; the fourth pin is connected to the drain electrodes of N22 and P22; and the fourth pin is connected to the source electrodes of N24, N26, N28, and N30.

[0116] The fifth pin is used for outputting an output signal Q. Specifically, the fifth pin is connected to the source electrodes of N22 and P22; and the fifth pin is connected to the drain electrodes of P19 and N17.

[0117] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0118] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the present application patent shall be subject to the appended claims.

Claims

1. A radiation-hardened Latch circuit using source isolation hardening and polarity hardening, characterized by, Comprise: The pull-up tube part includes 12 PMOS tubes P1~P12, 4 NMOS tubes N1~N4, and is used for pulling up storage nodes X0, X1, X2, X3, X4, X5, X6, X7; The pull-down tube part includes 7 NMOS tubes N5~N12, and is used for pulling down the storage nodes X0, X1, X2, X3, X4, X5, X6, X7; Wherein, X1, X2, X5, X6 are surrounded by NMOS transistors, forming a polarity reinforcement; P1 and P9, P4 and P10, P5 and P11, P8 and P12 form a source isolation reinforcement; The inverter one includes 1 NMOS transistor N20 and 1 PMOS transistor P20, and is used for inverting the clock signal CLK into the clock signal NCK; The inverter two includes 1 NMOS transistor N21 and 1 PMOS transistor P21, and is used for inverting the input signal D into the input signal DN; The transmission tube part includes 7 NMOS transistors N23~N30, and is all connected with the clock signal CLK; wherein, X0, X2, X4, X6 are connected with D through N23, N25, N27, N29, and X1, X3, X5, X7 are connected with DN through N24, N26, N28, N30; The C unit part includes C unit one, C unit two and C unit three; the C unit one includes 2 PMOS transistors P13~P14 and 2 NMOS transistors N13~N14, and is used for outputting the intermediate signal n1 according to X3, X5; the C unit two includes 2 PMOS transistors P15~P16 and 2 NMOS transistors N15~N16, and is used for outputting the intermediate signal n2 according to X7, X1; the C unit three includes 3 PMOS transistors P17~P19 and 3 NMOS transistors N17~N19, and is used for outputting the output signal Q according to n1, n2, CLK, NCK; and The transmission gate includes 1 NMOS transistor N22 and 1 PMOS transistor P22, and is used for opening or closing according to CLK, NCK; when the CLK=1, the transmission gate is opened, the anti-radiation latch circuit is in the transparent mode, D directly outputs Q through the transmission gate; when the CLK=0, the transmission gate is closed, the anti-radiation latch circuit is in the holding mode, D, DN are stored in X0, X1, X2, X3, X4, X5, X6, X7, and Q is outputted through the C unit part.

2. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 1, wherein, The sources of P1, P2, P3, P4, P5, P6, P7, P8 are connected with VDD; the sources of N5, N6, N7, N8, N9, N10, N11, N12 are grounded GND; X0 is connected with the gate of N2, the gate of N6, the gate of P10, the drain of P9, the drain of N5; X1 is connected with the gate of P9, the gate of N5, the drain of N1, the drain of N6; X2 is connected with the gate of P2, the gate of P4, the gate of N8, the drain of N2, the drain of N7; X3 is connected with the gate of P1, the gate of P3, the gate of N1, the gate of N7, the drain of P10, the drain of N8; X4 connects the gate of N4, the gate of P12, the gate of N10, the drain of P11, the drain of N9; X5 connects the gate of P11, the gate of N9, the drain of N3, the drain of N10; X6 connects the gate of P6, the gate of P8, the gate of N12, the drain of N4, the drain of N11; X7 connects the gate of P5, the gate of P7, the gate of N3, the gate of N11, the drain of P12, the drain of N12.

3. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 2, wherein, The source of P20 is connected to VDD, the gate is connected to CLK, and the drain is connected to NCK; The source of N20 is connected to ground GND, the gate is connected to the gate of P20, and the drain is connected to the drain of P20.

4. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 3, wherein, The source of P21 is connected to VDD, the gate is connected to D, and the drain is connected to DN; The source of N21 is connected to ground GND, the gate is connected to the gate of P21, and the drain is connected to the drain of P21.

5. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 4, wherein, The gates of N23, N24, N25, N26, N27, N28, N29, and N30 are connected to CLK; the drain of N23 is connected to X0, and the source is connected to DN; the drain of N24 is connected to X1, and the source is connected to D; the drain of N25 is connected to X2, and the source is connected to DN; the drain of N26 is connected to X3, and the source is connected to D; the drain of N27 is connected to X4, and the source is connected to DN; the drain of N28 is connected to X5, and the source is connected to D; the drain of N29 is connected to X6, and the source is connected to DN; the drain of N30 is connected to X7, and the source is connected to D.

6. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 4, wherein, The source of P13 is connected to VDD, and the gate is connected to X3; the source of P14 is connected to the drain of P13, the gate is connected to X5, and the drain is connected to n1; the drain of N13 is connected to the drain of P14, and the gate is connected to X3; the source of N14 is connected to ground GND, the gate is connected to X5, and the drain is connected to the source of N13; The source of P15 is connected to VDD, and the gate is connected to X7; the source of P16 is connected to the drain of P15, the gate is connected to X1, and the drain is connected to n2; the drain of N15 is connected to the drain of P16, and the gate is connected to X7; the source of N16 is connected to ground GND, the gate is connected to X1, and the drain is connected to the source of N15; The source of P17 is connected to VDD, and the gate is connected to n1; the source of P18 is connected to the drain of P17, and the gate is connected to n2; the source of P19 is connected to the drain of P18, the gate is connected to CLK, and the drain is connected to Q; the drain of N17 is connected to the drain of P19, and the gate is connected to NCK; the drain of N18 is connected to the source of N17, and the gate is connected to n1; the source of N19 is connected to ground GND, the gate is connected to n2, and the drain is connected to the source of N18.

7. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 6, wherein, The gate of N22 is connected to CLK, the drain is connected to D, and the source is connected to Q; The gate of P22 is connected to NCK, the drain is connected to the source of N22, and the source is connected to the drain of N22.

8. The radiation-hardened Latch circuit with source-isolation hardening and polarity hardening of claim 1, wherein, The gate length of all MOS transistors is 65 nm, the gate width of all PMOS transistors is 140 nm, the gate width of N5, N8, N9, N12, N14, and N16 is 280 nm, and the gate width of other NMOS transistors is 140 nm.

9. A radiation hardened Latch module characterized by, The anti-radiation Latch circuit package is adopted.

10. The radiation resistant Latch module of claim 9, wherein, The pins of the anti-radiation Latch module include: A first pin for connecting VDD; a second pin for ground GND; a third pin for inputting a clock signal CLK; a fourth pin for inputting an input signal D; and a fifth pin for outputting an output signal Q.

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