An impedance conversion sampling circuit for intrinsically safe AI modules

Abstract

The present invention relates to an impedance conversion sampling circuit for an intrinsically safe AI module. The circuit comprises a HART device, the front end of which is connected to a power supply via a current-limiting resistor R1, and the back end of which is connected to ground via a matching resistor R2 and a sampling resistor R6 connected in series. An impedance conversion circuit is connected in parallel across the ends of matching resistor R2. The impedance conversion sampling circuit for an intrinsically safe AI module, as proposed in an embodiment of the present invention, reduces DC impedance without affecting the amplitude of the HART signal, thereby increasing the load capacity of the AI ​​module.

Description

Technical Field

[0001] The present invention relates to the technical field of sampling of an intrinsically safe AI module, and in particular to an impedance conversion sampling circuit applied to the intrinsically safe AI module. Background Art

[0002] Currently, in DCS applications, a large number of multi-channel AI (analog input) modules are deployed to collect current signals from smart instruments in industrial sites. In addition to providing the normal 4-20mA current signal, smart instruments also provide HART (Highway Addressable Remote Transducer) signals.

[0003] HART is an open communication protocol for addressable remote sensor high-speed channels. It is a communication protocol used between field intelligent instruments and control room equipment. HART devices provide communication with relatively low bandwidth and moderate response time. After more than 30 years of development, HART technology has become very mature at home and abroad, and has become the industrial standard for global intelligent instruments. Field intelligent equipment and instruments can be managed conveniently and quickly through the HART protocol. The HART protocol uses an FSK frequency shift keying signal based on the Bell202 standard, and superimposes an audio digital signal with an amplitude of 0.5mA on a low-frequency 4-20mA analog signal for two-way digital communication. Since the digital FSK signal is phase-continuous and has an average value of 0, it does not affect the size of the analog signal transmitted to the control system. For example Figure 1 As shown, the logic "1" of the HART signal is represented by a frequency of 1200 Hz, and the logic "0" is represented by a frequency of 2200 Hz. The information transmission rate is 1200 baud.

[0004] According to the HART protocol physical layer requirements, HART signals require a 250-ohm matching resistor. Because the intrinsically safe AI module has a 300-ohm current-limiting resistor, it is extremely sensitive to increased impedance. According to traditional circuit design methods, adding a 250-ohm matching resistor would significantly affect the module's load capacity.

[0005] Conventional AI sampling modules such as Figure 2As shown, Rb is the sampling resistor of the intrinsically safe AI module, typically 100 ohms. Rc is the current-limiting resistor of the intrinsically safe AI, typically 300 ohms. According to the HART protocol physical layer requirements, Ra + Rb = 250 ohms. Taking 20mA as an example, the DC voltage drop across Ra and Rb is 5V, and the DC voltage drop across the current-limiting resistor Rc is 6V. The AI ​​module's load capacity for HART devices is 13V @ 20mA, and the equivalent impedance of the HART device is 650 ohms. Therefore, due to the HART protocol, traditional circuit designs place requirements on the equivalent impedance of HART sampling devices, requiring it to be less than 650 ohms.

[0006] The present invention discloses an impedance conversion sampling circuit applied to an intrinsically safe AI module, aiming to enhance the load capacity of the intrinsically safe AI module while meeting the HART physical layer requirements. Summary of the Invention

[0007] (1) Technical issues to be resolved

[0008] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides an impedance conversion sampling circuit applied to an intrinsically safe AI module, which solves the technical problem that adding a 250-ohm matching resistor to the intrinsically safe AI module will significantly affect the load capacity of the intrinsically safe AI module.

[0009] (2) Technical solution

[0010] In order to achieve the above objectives, the main technical solutions adopted by the present invention include:

[0011] An embodiment of the present invention provides an impedance conversion sampling circuit for an intrinsically safe AI module, including a HART device. The front end of the HART device is connected to a power supply via a current-limiting resistor R1, and the back end of the HART device is grounded via a matching resistor R2 and a sampling resistor R6 connected in series. An impedance conversion circuit is connected in parallel to both ends of the matching resistor R2.

[0012] The impedance conversion sampling circuit for an intrinsically safe AI module proposed in an embodiment of the present invention reduces DC impedance without affecting the amplitude of the HART signal, thereby increasing the load capacity of the AI ​​module.

[0013] Optionally, the impedance conversion circuit includes:

[0014] The bases of the first transistor Q1 and the second transistor Q2 are connected, and the collectors of the first transistor Q1 and the second transistor Q2 are connected in parallel to the first end of the matching resistor R2; the emitters of the first transistor Q1 and the second transistor Q2 are connected in parallel to the second end of the matching resistor R2.

[0015] Optionally, both the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0016] Optionally, the bases of the first transistor Q1 and the second transistor Q2 are connected in series with the first capacitor C1 and then connected to the second end of the matching resistor R2.

[0017] Optionally, a fourth resistor R4 is connected in series between the emitter of the first transistor Q1 and the second end of the matching resistor R2 , and a fifth resistor R5 is connected in series between the emitter of the second transistor Q2 and the second end of the matching resistor R5 .

[0018] Optionally, the bases of the first transistor Q1 and the second transistor Q2 are connected in series with a third resistor R3 and then connected to the first end of the matching resistor R2.

[0019] Optionally, in the second scenario, the impedance conversion circuit includes:

[0020] The bases of the first transistor Q1 and the second transistor Q2 are connected, and the emitters of the first transistor Q1 and the second transistor Q2 are connected in parallel to the first end of the matching resistor R2; the collectors of the first transistor Q1 and the second transistor Q2 are connected in parallel to the second end of the matching resistor R2.

[0021] Optionally, both the first transistor Q1 and the second transistor Q2 are PNP transistors.

[0022] Optionally, the bases of the first transistor Q1 and the second transistor Q2 are connected in series with the first capacitor C1 and then connected to the second end of the matching resistor R2; the bases of the first transistor Q1 and the second transistor Q2 are connected in series with the third resistor R3 and then connected to the second end of the matching resistor R2.

[0023] Optionally, a fourth resistor R4 is connected in series between the collector of the first transistor Q1 and the second end of the matching resistor R2 , and a fifth resistor R5 is connected in series between the collector of the second transistor Q2 and the second end of the matching resistor R5 .

[0024] (3) Beneficial effects

[0025] The present invention provides the following beneficial effects: The impedance conversion sampling circuit for an intrinsically safe AI module employs a parallel impedance conversion circuit across a matching resistor R2, thereby reducing DC impedance without affecting the amplitude of the HART signal. This increases the load capacity of the AI ​​module while meeting the HART physical layer requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of HART signal in the prior art;

[0027] Figure 2 Schematic diagram of the hardware topology of a conventional AI sampling module in the prior art;

[0028] Figure 3Schematic diagram of the hardware topology of the AI ​​sampling module according to the first preferred embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a 20mA+1.2k HART simulation signal according to a preferred embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of a 20mA+2.2k HART simulation signal according to a preferred embodiment of the present invention;

[0031] Figure 6 Schematic diagram of the hardware topology of the AI ​​sampling module according to the second preferred embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation methods in conjunction with the accompanying drawings.

[0033] The impedance conversion sampling circuit for an intrinsically safe AI module, proposed in an embodiment of the present invention, connects an impedance conversion circuit in parallel across matching resistor R2. This reduces DC impedance without affecting the amplitude of the HART signal, thereby increasing the AI ​​module's load capacity.

[0034] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0035] The AI ​​referred to in the following embodiments of the present invention is analog input.

[0036] Example 1

[0037] See also Figure 1 The impedance conversion sampling circuit applied to the intrinsically safe AI module of this embodiment includes a HART device. The front end of the HART device is connected to the power supply through a current-limiting resistor R1, and the back end of the HART device is grounded through a matching resistor R2 and a sampling resistor R6 connected in series. The impedance conversion circuit is connected in parallel at both ends of the matching resistor R2.

[0038] The impedance conversion sampling circuit applied to the intrinsically safe AI module according to the embodiment of the present invention reduces the DC impedance without affecting the amplitude of the HART signal, thereby increasing the load capacity of the AI ​​module.

[0039] In this embodiment, the impedance conversion circuit includes: a first transistor Q1 and a second transistor Q2 with their bases connected, the collectors of the first transistor Q1 and the second transistor Q2 being connected in parallel to the first end of the matching resistor R2; and the emitters of the first transistor Q1 and the second transistor Q2 being connected in parallel to the second end of the matching resistor R2. The first transistor Q1 and the second transistor Q2 are both NPN transistors. The bases of the first transistor Q1 and the second transistor Q2 are connected in series with a first capacitor C1 and then connected to the second end of the matching resistor R2. A fourth resistor R4 is connected in series between the emitter of the first transistor Q1 and the second end of the matching resistor R2, and a fifth resistor R5 is connected in series between the emitter of the second transistor Q2 and the second end of the matching resistor R5. The bases of the first transistor Q1 and the second transistor Q2 are connected in series with a third resistor R3 and then connected to the first end of the matching resistor R2.

[0040] When this embodiment works:

[0041] When the meter outputs a 4-20mA DC signal, the base voltage of the first and second transistors Q1 and Q2, which are connected back-to-back, is always higher than the emitter voltage, causing Q1 and Q2 to conduct. Taking 20mA and a 100-ohm sampling resistor R6 as an example, the voltage VR6 across sampling resistor R6 is approximately 0.2V. The voltage across matching resistor R2 is equal to the transistor's VBE voltage plus the voltage across R5 (R5's resistance can be set relatively small, so the voltage across it is negligible). The voltage VR2 across R2 is equal to the transistor's VBE voltage, approximately 0.6V, resulting in an overall voltage drop of 0.8V, approximately 2.2V less than when using pure resistance.

[0042] When the HART signal passes through, due to the presence of C1 and R5, the charge and discharge time is set to be greater than the HART frequency, and the back-to-back first transistor Q1 and second transistor Q2 cannot be turned on. At this time, the AC impedance can be set to 150Ω, plus the sampling resistor of 100Ω, to meet the HART physical layer requirements.

[0043] like Figure 4 and Figure 5 As shown in the figure, when the instrument current is 20mA and the ±0.5mA HART signal is superimposed, the voltage simulation waveform across R2+R6 shows a DC voltage of approximately 3V and an AC voltage of approximately 0.25V. Therefore, it can be concluded that the DC impedance of the AI ​​sampling module with the added impedance conversion circuit is approximately 150 ohms and the AC equivalent impedance is 250 ohms. In this embodiment, the following settings can be made: R1 = 300Ω, R2 = R4 = 180Ω, R3 = 1kΩ, R5 = 12Ω, R6 = 100Ω, and C1 = 10uF.

[0044] Compared with traditional intrinsically safe AI sampling modules, taking 20mA as an example, the AI ​​module's load capacity for HART devices is 15V@20mA, and the maximum equivalent impedance of the HART device can be 750 ohms, which increases the load capacity by 15.38%.

[0045] Example 2

[0046] See also Figure 6 This embodiment is a replacement example in which all the transistors in the first embodiment are PNP transistors, and the impedance conversion circuit is configured as follows:

[0047] The bases of the first transistor Q1 and the second transistor Q2 are connected, and the emitters of the first transistor Q1 and the second transistor Q2 are connected in parallel to the first end of the matching resistor R2; the collectors of the first transistor Q1 and the second transistor Q2 are connected in parallel to the second end of the matching resistor R2. The first transistor Q1 and the second transistor Q2 are both PNP transistors.

[0048] During implementation, the bases of the first transistor Q1 and the second transistor Q2 are connected in series with the first capacitor C1 and then connected to the second end of the matching resistor R2. The bases of the first transistor Q1 and the second transistor Q2 are connected in series with the third resistor R3 and then connected to the second end of the matching resistor R2. A fourth resistor R4 is connected in series between the collector of the first transistor Q1 and the second end of the matching resistor R2, and a fifth resistor R5 is connected in series between the collector of the second transistor Q2 and the second end of the matching resistor R5.

[0049] The resistance values ​​of this embodiment can be set with reference to those of the first embodiment, and can achieve substantially the same effect as that of the first embodiment. In practice, the first transistor Q1 and the second transistor Q2 can also be set as a combination of an NPN transistor and a PNP transistor, and substantially the same effect as that of the first embodiment can be achieved by appropriately adjusting the resistance values ​​of R3, R4, and R5 and the capacitance value of C1, which will not be further described here.

[0050] In summary, the impedance conversion sampling circuit applied to the intrinsically safe AI module of the present invention can enhance the load capacity of the intrinsically safe AI module, while having a simple hardware circuit design and low cost.

[0051] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0052] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0053] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0054] In the description of this specification, the terms "one embodiment", "some embodiments", "embodiments", "examples", "specific examples" or "some examples" refer to the specific features, structures, materials or characteristics described in conjunction with the embodiment or example and included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0055] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may alter, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. An impedance conversion sampling circuit for an intrinsically safe AI module, characterized by: The invention comprises a HART device, wherein the front end of the HART device is connected to a power supply via a current limiting resistor (R1), and the rear end of the HART device is grounded via a matching resistor (R2) and a sampling resistor (R6) connected in series; an impedance conversion circuit is connected in parallel to both ends of the matching resistor (R2); wherein the impedance conversion circuit comprises: A first triode (Q1) and a second triode (Q2) having bases connected to each other, collectors of the first triode (Q1) and the second triode (Q2) being connected in parallel to a first end of the matching resistor (R2); emitters of the first triode (Q1) and the second triode (Q2) being connected in parallel to a second end of the matching resistor (R2); A fourth resistor (R4) is connected in series between the emitter of the first transistor (Q1) and the second end of the matching resistor (R2), and a fifth resistor (R5) is connected in series between the emitter of the second transistor (Q2) and the second end of the matching resistor (R5).

2. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 1, wherein: The first transistor (Q1) and the second transistor (Q2) are both NPN transistors.

3. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 2, wherein: The bases of the first transistor (Q1) and the second transistor (Q2) are connected in series with a first capacitor (C1) and then connected to the second end of the matching resistor (R2).

4. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 3, wherein: The bases of the first transistor (Q1) and the second transistor (Q2) are connected in series with a third resistor (R3) and then connected to the first end of the matching resistor (R2).

5. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 1, wherein: The impedance conversion circuit comprises: A first transistor (Q1) and a second transistor (Q2) are connected to each other at their bases, the emitters of the first transistor (Q1) and the second transistor (Q2) are connected in parallel to the first end of the matching resistor (R2), and the collectors of the first transistor (Q1) and the second transistor (Q2) are connected in parallel to the second end of the matching resistor (R2).

6. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 5, characterized in that: The first transistor (Q1) and the second transistor (Q2) are both PNP transistors.

7. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 6, wherein: The bases of the first transistor (Q1) and the second transistor (Q2) are connected in series with a first capacitor (C1) and then connected to the second end of the matching resistor (R2); the bases of the first transistor (Q1) and the second transistor (Q2) are connected in series with a third resistor (R3) and then connected to the second end of the matching resistor (R2).

8. The impedance conversion sampling circuit device for an intrinsically safe AI module according to claim 2, wherein: A fourth resistor (R4) is connected in series between the collector of the first transistor (Q1) and the second end of the matching resistor (R2), and a fifth resistor (R5) is connected in series between the collector of the second transistor (Q2) and the second end of the matching resistor (R5).

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