Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of word lines, a dielectric layer, and a plurality of bit lines. The substrate comprises active structures and shallow trench isolations. The word lines are embedded in the substrate and staggered with the active structures and the shallow trench isolations, respectively. The dielectric layer is arranged on the substrate and covers the top surfaces of the word lines. The bit lines extend on the substrate in a first direction. The bit lines comprise at least one first bit line which simultaneously overlaps the active structures and the shallow trench isolations and has a bottom surface physically contacting only the dielectric layer, and a plurality of second bit lines which are arranged below a plurality of bit line plugs penetrating through the dielectric layer and directly contacting the active structures. The first bit line is arranged as a dummy bit line to maintain the same overall light flux when the photolithography manufacturing process is performed, and to improve the manufacturing yield of the semiconductor device.

Description

Semiconductor devices and their fabrication methods Technical Field

[0001] This invention relates to a semiconductor device and a method for fabricating the same, particularly a semiconductor device comprising an active structure and a shallow trench isolation method for fabricating the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, it has gradually replaced DRAM with only planar gate structures as the current mainstream development trend. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array to store information. Each memory cell can be composed of a transistor assembly and a capacitor assembly connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] One objective of this invention is to provide a semiconductor device and its fabrication method, which simultaneously forms bit lines and dummy bit lines without adding extra operational steps. This allows for maintaining the same overall luminous flux during photolithography, thereby improving the fabrication yield of the semiconductor device. Consequently, a semiconductor device with better component reliability can be formed, effectively mitigating structural defects that may arise due to continuously increasing component density.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, multiple word lines, a dielectric layer, and multiple bit lines. The substrate includes an active structure and a shallow trench isolation layer. The word lines are embedded in the substrate and intersect with the active structure and the shallow trench isolation layer, respectively. The dielectric layer is disposed on the substrate, covering the top surface of the word lines. The bit lines extend on the substrate in a first direction, wherein at least one first bit line simultaneously overlaps the active structure and the shallow trench isolation layer, the bottom surface of the first bit line only physically contacts the dielectric layer and is not electrically connected to the active structure, and multiple second bit lines are disposed on one side of the first bit line, with multiple bit line plugs disposed below them that pass through the dielectric layer and directly contact the active structure.

[0005] To achieve the above objectives, another embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps. First, a substrate is provided, the substrate including an active structure and a shallow trench isolation, and a plurality of word lines are formed in the substrate, the word lines intersecting with the active structure and the shallow trench isolation respectively. Next, a dielectric layer is formed on the substrate, covering the top surface of the word lines. Then, a plurality of bit lines extending in a first direction are formed on the substrate, wherein the bit lines include at least one first bit line and a plurality of second bit lines disposed on one side of the first bit line, the first bit line simultaneously overlapping the active structure and the shallow trench isolation, and the bottom surface of the first bit line only physically contacts the dielectric layer and is not electrically connected to the active structure, and a plurality of bit line plugs passing through the dielectric layer and directly contacting the active structure are disposed below each second bit line. Attached Figure Description

[0006] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figures 1 to 3 are schematic diagrams of a semiconductor device according to a first embodiment of the present invention, wherein:

[0008] Figure 1 is a top view of the semiconductor device in the first embodiment;

[0009] Figure 2 is a cross-sectional view of Figure 1 along the tangent line A-A'; and

[0010] Figure 3 is a cross-sectional view of Figure 1 along the tangent line B-B'.

[0011] Figures 4 to 7 are schematic diagrams of a semiconductor device according to a second embodiment of the present invention, wherein:

[0012] Figure 4 is a top view of the semiconductor device in the second embodiment;

[0013] Figure 5 is a cross-sectional view of Figure 4 along the tangent line A-A';

[0014] Figure 6 is a cross-sectional view of Figure 4 along the tangent B-B'; and

[0015] Figure 7 is a cross-sectional view of Figure 4 along the tangent C-C'.

[0016] Figures 8 and 9 illustrate schematic diagrams of a semiconductor device according to a third embodiment of the present invention, wherein:

[0017] Figure 8 is a top view of the semiconductor device in the third embodiment; and

[0018] Figure 9 is a cross-sectional view of Figure 8 along the tangent line D-D'.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 100, 300, 500 semiconductor devices

[0021] 110 substrate

[0022] 120 Shallow Ditch Isolation

[0023] 130 Active Structure

[0024] 131 First Active Segment

[0025] 133 Second active segment

[0026] 135 Third active segment

[0027] 135a First side

[0028] 135b Second side

[0029] 140 gate structure

[0030] 141 Ditch

[0031] 142 Dielectric layer

[0032] 143 Gate dielectric layer

[0033] 144 gate

[0034] 145 cap layer

[0035] 150 dielectric layer

[0036] 160, 360 bit lines

[0037] 160a, 360a bit line plugs

[0038] 161, 361, First line

[0039] 162 Semiconductor Layer

[0040] 163, 363 Second line

[0041] 164 Barrier Layer

[0042] 166 conductive layer

[0043] 168 cap layer

[0044] 180 and 580 spacer wall structures

[0045] 181, 581 First spacer wall

[0046] 183, 583 Second spacer

[0047] 185, 585 Third spacer

[0048] 365, 565 Third Line

[0049] 560a bit line plug

[0050] 570 storage node plugs

[0051] D1 First Direction

[0052] D2 Second Direction

[0053] D3 third direction

[0054] P1 First Spacing

[0055] P2 Second Spacing

[0056] P31 First Spacing

[0057] P32 Second Spacing

[0058] S1 Interval Distance

[0059] W1 First line width

[0060] W2 Second Line Width

[0061] W31 First Line Width

[0062] W32 Second Line Width

[0063] W33 Third line width Detailed Implementation

[0064] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0065] Please refer to Figures 1 to 3, which exemplarily illustrate a schematic diagram of a semiconductor device 100 in the first embodiment of the present invention. Figure 1 is a top view of the semiconductor device 100, while Figures 2 and 3 are cross-sectional views of the semiconductor device 100 along different tangents. The semiconductor device 100 includes, for example, a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. At least one shallow trench isolation (STI) 120 is provided within the substrate 110 to define an active structure 130 on the substrate 110. That is, the shallow trench isolation 120 surrounds the active structure 130 and is disposed on the outside of the active structure 130.

[0066] As shown in Figure 1, the active structure 130 includes a plurality of first active segments 131, a plurality of second active segments 133, and a third active segment 135. The first active segments 131 and second active segments 133 extend parallel to each other and spaced apart along a first direction D1, and are arranged in a staggered manner. Each first active segment 131 has the same first length L1 along the first direction D1, while each second active segment 133 has a length different from the first length L1 along the first direction D1, for example, greater than or less than the first length L1, as shown in Figure 1. Thus, the first active segments 131 and second active segments 133 can be arranged in a specific configuration, such as the array arrangement shown in Figure 1, but are not limited to this. The third active segment 135 surrounds the outside of the first active segments 131 and second active segments 133. For example, the third active segment 135 includes at least one first side 135a extending along a second direction D2 (e.g., the x direction) and at least one second side 135b extending along a third direction D3 (e.g., the y direction), such that the third active segment 135 can be presented as a rectangular frame (not shown) that surrounds the outside of the first active segment 131 and the second active segment 133.

[0067] It should be noted that, referring to Figure 1, the third active segment 135 does not contact any of the first active segments 131, but directly contacts all the second active segments 133 and is integrally formed. Thus, each of the second active segments 133 can be considered as an extension of the third active segment 135 along the first direction D1, so as to uniformly bear the stress influence from the active structure 130 and the shallow trench isolation 120. Therefore, the active structure 130 obtains a more stable structure, avoiding structural collapse or damage. Those skilled in the art will understand that the specific number of the first side 135a and / or the second side 135b of the third active segment 135 can be adjusted according to actual needs, or other sides may be included, so that the third active segment 135 can also present other shapes as a whole, not limited to the aforementioned rectangular frame shape.

[0068] In one embodiment, referring to Figures 1 and 2, the active structure 130 can be formed by, but is not limited to, the following fabrication process. First, a bulk silicon substrate (not shown) is provided. A mask layer (not shown) is formed on the bulk substrate. The mask layer includes a pattern that can be used to define the active structure 130. The bulk substrate is partially covered by the mask layer and an etching process is performed. The bulk substrate is partially removed to form the active structure 130 and at least one shallow trench (not shown) surrounding the active structure 130. An insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, is then filled into the shallow trench to form a substrate 110. The substrate 110 has a shallow trench isolation 120 with its top surface flush with the surface of the substrate 110 and the active structure 130. Furthermore, in another embodiment, the formation of the first active segment 131 and the second active segment 133 can also be achieved using a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, but is not limited thereto. It should also be noted that, in one embodiment, the first active segment 131 is preferably disposed in a region of relatively high component density in the semiconductor device 100, such as a cell region (not shown), while the second active segment 133 and the third active segment 135 are disposed in a region of relatively low component density in the semiconductor device 100, such as a peripheral region (not shown), but are not limited thereto.

[0069] Furthermore, referring to Figures 1 and 2, the semiconductor device 100 also includes a plurality of buried gate structures 140 embedded in the substrate 110. The gate structures 140 extend parallel to each other in the third direction D3 and are interleaved with the active structure 130 and the shallow trench isolation 120. Specifically, as shown in Figures 2 and 3, each gate structure 140 includes a dielectric layer 142, a gate dielectric layer 143, a gate 144, and a capping layer 145 stacked sequentially from bottom to top. The surface of the capping layer 145 of each gate structure 140 can be flush with the top surface of the substrate 110, so that the gate structure 140 can serve as a plurality of buried word lines (WL) of the semiconductor device 100 to receive or transmit voltage signals from subsequently formed memory cells (not shown). In one embodiment, the gate structure 140 is fabricated in a manner including but not limited to the following steps: First, a plurality of trenches 141 are formed in the substrate 110. Then, a dielectric layer 142 covering the entire surface of the trench 141, a gate dielectric material layer (not shown), and a gate layer (not shown) filling the trench 141 are formed sequentially in each trench 141. After the gate layer and gate dielectric material layer of the etch-back portion are formed, a gate dielectric layer 143 covering the lower half surface of each trench 141 and a gate 144 filling the lower half of each trench 141 are formed. Finally, a capping layer 145 filling the upper half of the trench 141 is formed.

[0070] On the other hand, referring to Figures 1 and 2, the semiconductor device 100 also includes a dielectric layer 150 and multiple bit lines (BLs) 160 disposed on a substrate 110. The dielectric layer 150 directly covers the top surface of each word line (i.e., the gate structure 140), while the bit lines 160 are disposed on the dielectric layer 150, extending parallel to each other in the second direction D2, and intersecting with the active structure 130, the shallow trench isolation 120, and the word lines. The sidewalls of the bit lines 160 are provided with spacer structures 180. The spacer structures 180 may selectively have a single-layer structure or a composite layer structure as shown in Figure 2. The composite layer structure includes, for example, a first spacer 181 (e.g., containing silicon nitride), a second spacer 183 (e.g., containing silicon oxide), and a third spacer 185 (e.g., containing silicon nitride) stacked sequentially from the inside to the outside on the sidewalls of each bit line 160, but is not limited thereto. In one embodiment, the dielectric layer 150 has, for example, a composite layer structure, such as an oxide-nitride-oxide (ONO, not shown) structure, but is not limited thereto.

[0071] It should be noted that, referring to Figures 1 and 2, bit line 160 includes at least one first bit line 161 and multiple second bit lines 163, with the first bit line 161 disposed on one side of all the second bit lines 163. The first bit line 161 has a relatively large first linewidth W1 in the third direction D3, so as to simultaneously overlap the third active segment 135 (including the first side 135a and the second side 135b), a portion of the second active segment 133, and a portion of the first active segment 131, while the second bit lines 163 have a relatively small second linewidth W2 and only overlap the second side 135b, the portion of the second active segment 133 connected to the second side 135b, and a portion of the first active segment 131, as shown in Figure 1. Wherein, the first line width W1 of the first line 161 is less than the first spacing P1 between the first line 161 and the adjacent second line 163 (the distance shown in the figure), and the first line width W1 of the first line 161 is greater than the distance between the first line 161 and the adjacent second line 163, or the second spacing P2 between any two adjacent second lines 163.

[0072] For example, as shown in Figures 1 to 3, each bit line 160 includes, in order from bottom to top, a semiconductor layer (e.g., containing polysilicon) 162, a barrier layer (e.g., containing titanium and / or titanium nitride) 164, a conductive layer (e.g., containing low-resistivity metals such as tungsten, aluminum, or copper) 166, and a capping layer (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride) 168 stacked on the dielectric layer 150. The first bit line 161 is entirely located on the dielectric layer 150, such that the bottom surface of the first bit line 161 only physically contacts the top surface of the dielectric layer 150, without contacting the active structure 130. Below each second bit line 163, multiple bit line contacts (BLCs) 160a are further disposed, allowing each bit line contact 160a to pass through the dielectric layer 150 and directly contact each first active segment 131. Thus, each second bit line 163 can be electrically connected to a transistor assembly (not shown) subsequently formed in the substrate 110 via a bit line plug 160a, while no plug is provided below the first bit line 161 and no contact is made with any first active segment 131, serving as a dummy bit line.

[0073] In one embodiment, referring to FIG2, the fabrication of bit line plugs 160a and bit lines 160 includes, but is not limited to, the following steps. First, another mask layer (not shown) is formed on the dielectric layer 150. An etching process is performed through the other mask layer to remove a portion of the dielectric layer 150 and a portion of the substrate 110 below it, thereby forming a plurality of bit line plug holes (not shown), which are respectively located between two adjacent gate structures 140. Then, after removing another mask layer, a semiconductor material layer (not shown) is formed to fill the bit line plug holes. Next, a barrier material layer (not shown), a conductive material layer (not shown), and a cover material layer (not shown) are sequentially formed on the semiconductor material layer. After photolithography, the portion of the semiconductor material layer filling the bit line plug holes forms bit line plugs 160a, and the patterned stacked layers form bit lines 160. The bit lines that overlap and directly contact each bit line plug 160a are the second bit lines 163, and the bit lines that do not overlap any bit line plugs 160a are the first bit lines 161. This operation allows for the simultaneous fabrication of the first bit line 161 (dummy bit line) and the second bit line 163 (normal bit line), and the bit line plugs 160a can be integrally formed with the second bit line 163, but this is not a limitation.

[0074] Thus, referring to FIG1, the fabrication of the semiconductor device 100 in the first embodiment of the present invention is completed. According to this embodiment, the semiconductor device 100 simultaneously includes a first bit line 161 with a relatively large linewidth (i.e., a first linewidth W1) and a second bit line 163 with a relatively small linewidth (i.e., a second linewidth W2). By using the first bit line 161, which does not contact the active structure 130, as a dummy bit line, all bit lines 160 can maintain the same overall luminous flux during the photolithography process. In this way, the formed semiconductor device 100 has optimized structural reliability and performance. Furthermore, the first bit line 161 has a relatively large first linewidth W1 and a first spacing P1, which can improve the process tolerance or process window of peripheral components. Simultaneously, it can avoid the negative impact of micro-load effects or etching defects caused by differences in component density during the fabrication process on the overall structure of the semiconductor device, which is beneficial for improving structural defects that may arise due to continuously increasing component density and improving component performance. On the other hand, in this embodiment, the dummy bit line (i.e., the first bit line 161) and the normal bit line (i.e., the second bit line 163) are formed simultaneously through the same manufacturing process. In this way, a semiconductor device 100 with better performance and component reliability can be formed without adding extra operation steps.

[0075] However, those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication process of this invention may have other forms or be achieved by other means, and are not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device and its fabrication process of this invention. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, without repeating the similarities. Furthermore, the same components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0076] Please refer to Figures 4 to 7, which illustrate schematic diagrams of the semiconductor device 300 in the second embodiment of the present invention. Figure 4 is a top view of the semiconductor device 300, while Figures 5, 6, and 7 are cross-sectional views of the semiconductor device 300 along different tangents. The structure of the semiconductor device 300 in this embodiment is generally the same as that of the semiconductor device 100 in the first embodiment described above, and the similarities will not be repeated. The main difference between the semiconductor device 300 in this embodiment and the semiconductor device 100 in the first embodiment is that, in this embodiment, the bit line 360 ​​further includes at least one third bit line 365. The third bit line 365 is located between the first bit line 361 and multiple second bit lines 363 in the third direction D3, as shown in Figure 4.

[0077] It should be noted that, referring to Figure 4, in this embodiment, the first bit line 361 also has a relatively large first linewidth W31 in the third direction D3, so as to overlap simultaneously with the third active segment 135 (including the first side 135a and the second side 135b) and a portion of the second active segment 133. The second bit line 363 has a relatively small second linewidth W32, and only overlaps with the second side 135b, the portion of the second active segment 133 connected to the second side 135b, and a portion of the first active segment 131. The third bit line 365 has a third linewidth W33 that is larger than the second linewidth W32 and smaller than the first linewidth W31, and also overlaps with the second side 135b, the portion of the second active segment 133 connected to the second side 135b, and a portion of the first active segment 131. Among them, the interval S1 between the third bit line 365 and the first bit line 361 is greater than the second line width W32, and there is a first gap P31 between the first bit line 361 and the third bit line 365, and there is a second gap P32 between any two adjacent second bit lines 363, while the first gap P31 is smaller than the second gap P32 between adjacent second bit lines 363, as shown in Figure 4.

[0078] For example, as shown in Figures 5 to 7, each bit line 360 ​​includes, in order from bottom to top, a semiconductor layer (e.g., containing polysilicon) 162, a barrier layer (e.g., containing titanium and / or titanium nitride) 164, a conductive layer (e.g., containing low-resistivity metals such as tungsten, aluminum, or copper) 166, and a capping layer (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride) 168 stacked on the dielectric layer 150. The first bit line 361 and the third bit line 365 are entirely located on the dielectric layer 150, such that the bottom surfaces of the first bit line 361 and the third bit line 365 only physically contact the top surface of the dielectric layer 150, and do not contact the active structure 130 at all. Therefore, they can simultaneously serve as dummy bit lines of the semiconductor device 300. Each second bit line 363 passes through the dielectric layer 150 via multiple bit line plugs 360a disposed below and directly contacts the corresponding first active segment 131 to electrically connect to the transistor assembly (not shown) subsequently formed in the substrate 110. Those skilled in the art will understand that the fabrication method of each component in this embodiment is generally the same as that in the previous embodiments, and will not be described again here.

[0079] Therefore, referring to Figures 4 and 5, the fabrication of the semiconductor device 300 in the second embodiment of the present invention is completed. According to this embodiment, the semiconductor device 300 simultaneously includes a first bit line 361 and a third bit line 365 with relatively large linewidths (i.e., a first linewidth W31 and a third linewidth W33) as dummy bit lines, ensuring that all bit lines 360 maintain the same overall luminous flux during the photolithography process. Thus, the formed semiconductor device 300 also possesses optimized structural reliability and performance. Furthermore, since the third linewidth W33 of the third bit line 365 and the spacing S1 between the third bit line 365 and the first bit line 361 are both greater than the second linewidth W32 of the second bit line 363, the fabrication margin or fabrication window of peripheral components is increased. Simultaneously, it avoids the negative impact of micro-load effects or etching defects caused by differences in component density during the fabrication process on the overall structure of the semiconductor device, which is beneficial for improving structural defects that may arise due to continuously increasing component density and improving component performance. Furthermore, the dummy bit lines (including the first bit line 361 and the third bit line 365) in this embodiment are also formed synchronously with the ordinary bit lines (i.e. the second bit line 363) through the same manufacturing process. Therefore, a semiconductor device 300 with better performance and component reliability can be formed without adding extra operation steps.

[0080] For example, please refer to Figures 8 and 9, which illustrate schematic diagrams of the semiconductor device 500 in the third embodiment of the present invention. Figure 8 is a top view of the semiconductor device 500, and Figure 9 is a cross-sectional view of the semiconductor device 500. The structure of the semiconductor device 500 in this embodiment is generally the same as that of the semiconductor device 300 in the aforementioned second embodiment, and the similarities will not be described again. The main difference between the semiconductor device 500 in this embodiment and the semiconductor device 300 in the aforementioned second embodiment is that a plurality of bit line plugs 560a are additionally provided below the third bit line 565, and at least one bit line plug 560a directly contacts the memory node plug 570.

[0081] Exemplary, as shown in Figures 8 and 9, the semiconductor device 500 of this embodiment further includes a plurality of memory node plugs 570, which are disposed on the substrate 110 at intervals and alternately arranged with each second bit line 363 and third bit line 565 on the third direction D3. Each memory node plug 570 further penetrates the dielectric layer 150 and directly contacts each first active segment 131 and shallow trench isolation 120 in the substrate 110. In one embodiment, the memory node plugs 570 include, for example, a low-resistivity metal material such as aluminum, titanium, copper or tungsten, and may include the same material as the bit line plugs 360a and 560a, but are not limited thereto. In addition, each memory node plug 570 and each second bit line 363 and third bit line 565 are insulated from each other through a spacer structure 580 (not shown in Figure 8). The spacer wall structure 580 may selectively have a single-layer structure or a composite layer structure as shown in FIG9. The composite layer structure includes, for example, a first spacer wall 581 (e.g., containing silicon nitride), a second spacer wall 583 (e.g., containing silicon oxide), and a third spacer wall 585 (e.g., containing silicon nitride) stacked sequentially on the sidewalls of the second bit line 363 and the third bit line 565, but is not limited thereto.

[0082] In one embodiment, referring to Figures 8 and 9, the memory node plug 570 can be formed using, but is not limited to, the following fabrication process. First, a second mask layer (not shown) is formed on the bit line 360. An etching process is then performed through this second mask layer to remove a portion of the dielectric layer 150, forming multiple plug holes (not shown) to expose the substrate 110 on both sides of each of the underlying first active segments 131. Then, multiple plugs are formed on the substrate 110 to directly contact the exposed substrate 110 as the memory node plug 570. In another embodiment, the memory node plug 570 can also be formed using a self-aligned double patterning process or a self-aligned reverse patterning process.

[0083] It should be noted that, referring to Figure 8, in this embodiment, because the third bit line 565 has a relatively large third line width W33, the bit line plug 560a disposed below the third bit line 565 has a correspondingly large extension range, even partially extending to the location of the memory node plug 570. Thus, at least one bit line plug 560a will directly contact the memory node plug 570 and form a short circuit by directly conducting with the memory node plug 570. Therefore, in this embodiment, the third bit line 565 is still a dummy bit line and will not electrically connect to the transistor components (not shown) subsequently formed in the substrate 110.

[0084] Thus, referring to Figures 8 and 9, the fabrication of the semiconductor device 500 in the third embodiment of the present invention is completed. According to this embodiment, the semiconductor device 500 includes a first bit line 361 and a third bit line 565 with relatively large linewidths (i.e., a first linewidth W31 and a third linewidth W33). The first bit line 361 is entirely located on the dielectric layer 150, while the third bit line 565 is provided with multiple bit line plugs 560a and directly connected to some of the memory node plugs 570, making the first bit line 361 and the third bit line 565 simultaneously function as dummy bit lines. In this way, all bit lines 360 maintain the same overall light flux during the photolithography process, and the resulting semiconductor device 500 has an optimized component in terms of both structural reliability and performance. Furthermore, the dummy bit lines (including the first bit line 361 and the third bit line 565) in this embodiment are also formed synchronously with the ordinary bit lines (i.e. the second bit line 363) through the same manufacturing process, so that a semiconductor device 500 with better component reliability can be formed without adding extra operation steps.

[0085] Overall, the semiconductor device fabrication method of the present invention simultaneously forms bit lines and dummy bit lines without adding extra operational steps, thereby maintaining the same luminous flux in each region during the photolithography process. The dummy bit lines, for example, are entirely located on the dielectric layer, completely not in contact with the active structure, or are directly short-circuited with the memory node plug, thus allowing integration into the general bit line fabrication process and avoiding increased process complexity. This improves the semiconductor device fabrication yield. Consequently, the resulting semiconductor device exhibits optimized component reliability and achieves superior performance.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate, including active structure and shallow trench isolation; Multiple word lines extend in a third direction, are embedded in the substrate, and are respectively isolated from and intersected with the active structure and the shallow trench; a dielectric layer is disposed on the substrate and covers the top surface of the word lines; The system also includes multiple bit lines extending on the substrate in a second direction perpendicular to the third direction. Each bit line includes at least one first bit line and multiple second bit lines disposed on one side of the first bit line. The first bit line overlaps the active structure and is isolated from the shallow trench. The bottom surface of the first bit line only physically contacts the dielectric layer and is not electrically connected to the active structure. Multiple bit line plugs passing through the dielectric layer and directly contacting the active structure are disposed below each second bit line. The system further includes multiple memory node plugs disposed on the substrate and alternately arranged with each bit line. It also includes at least one third bit line located between the first bit line and the second bit line, wherein at least one bit line plug directly contacting the memory node plug is disposed below the third bit line.

2. The semiconductor device according to claim 1, characterized in that, The first bit line has a first line width, and each of the second bit lines has a second line width, wherein the first line width is greater than the second line width.

3. The semiconductor device according to claim 2, characterized in that, The first line width is greater than the spacing between each of the second bit lines.

4. The semiconductor device according to claim 1, characterized in that, The active structure includes a plurality of first active segments, a plurality of second active segments, and a third active segment. The first active segments and the second active segments extend parallel to each other and separated in a first direction. All the second active segments directly contact the third active segment. The first bit lines overlap but do not directly contact the third active segment and the second active segments.

5. The semiconductor device according to claim 4, characterized in that, The bottom surface of the third bit line only physically contacts the dielectric layer and is not electrically connected to the active structure.

6. The semiconductor device according to claim 5, characterized in that, The third bit line overlaps with but does not directly contact the third active segment and the second active segment.

7. The semiconductor device according to claim 5, characterized in that, The first line width of the first bit line is greater than the third line width of the third bit line, and the third line width of the third bit line is greater than the second line width of the second bit line.

8. The semiconductor device according to claim 5, characterized in that, The spacing between the first bit line and the third bit line is greater than the second line width of the second bit line.

9. The semiconductor device according to claim 5, characterized in that, There is a first spacing between the first bit line and the third bit line, and there is a second spacing between each of the second bit lines, wherein the first spacing is smaller than the second spacing.

10. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including an active structure isolated from a shallow trench; Multiple word lines are formed within the substrate, the word lines extend along a third direction, and the word lines are isolated from and intersected with the active structure and the shallow trench, respectively; A dielectric layer is formed on the substrate to cover the top surface of the word line; The method further includes: forming multiple bit lines extending in a second direction on the substrate, the second direction being perpendicular to the third direction; wherein the bit lines include at least one first bit line and multiple second bit lines disposed on one side of the first bit line; the first bit line simultaneously overlaps the active structure and is isolated from the shallow trench; the bottom surface of the first bit line only physically contacts the dielectric layer and is not electrically connected to the active structure; and multiple bit line plugs passing through the dielectric layer and directly contacting the active structure are disposed below each second bit line; the method also includes: forming multiple memory node plugs on the substrate, the memory node plugs being alternately arranged with each bit line; and forming at least one third bit line between the first bit line and the second bit line, wherein at least one bit line plug directly contacting the memory node plug is formed below the third bit line.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The active structure includes a plurality of first active segments, a plurality of second active segments, and a third active segment. The first active segments and the second active segments extend in a first direction in parallel and separated from each other. All the second active segments directly contact the third active segment. The first bit lines overlap but do not directly contact the third active segment and the second active segments.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The bottom surface of the third bit line only physically contacts the dielectric layer and is not electrically connected to the active structure.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The first line width of the first bit line is greater than the third line width of the third bit line, and the third line width of the third bit line is greater than the second line width of the second bit line.

14. The method for fabricating a semiconductor device according to claim 12, characterized in that, The distance between the first bit line and the third bit line is greater than the second line width of the second bit line.

15. The method for fabricating a semiconductor device according to claim 12, characterized in that, There is a first spacing between the first bit line and the third bit line, and there is a second spacing between each of the second bit lines, wherein the first spacing is smaller than the second spacing.

16. The method for fabricating a semiconductor device according to claim 12, characterized in that, The third bit line overlaps the third active segment and the second active segment simultaneously.

17. The method for fabricating a semiconductor device according to claim 10, characterized in that, The first bit line has a first line width, and each of the second bit lines has a second line width. The first line width is greater than the second line width, and the first line width is greater than the spacing between the second bit lines.

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