Semiconductor element with composite interconnects

Abstract

A semiconductor element is disclosed. The semiconductor element includes a package structure including a first side and a second side opposite to the first side; a interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of intermediate interconnectors located between the first side of the package structure and the first chip and between the first side of the package structure and the second chip. The plurality of intermediate interconnectors respectively include an intermediate outer layer located between the first side of the package structure and the interposer structure; an intermediate inner layer surrounded by the intermediate outer layer; and a cavity enclosed by the interposer structure, the package structure and the intermediate inner layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 560,608 (i.e., priority date "December 23, 2021"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a composite intermediate interconnect. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems have arisen during this shrinking process, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, efficiency, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device including a package structure comprising a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of intermediate interconnects located between the first side of the package structure and the first chip and between the first side of the package structure and the second chip. The plurality of intermediate interconnects topographically aligned with the first chip includes a first density. The plurality of intermediate interconnects topographically aligned with the second chip includes a second density different from the first density.

[0006] Another aspect of this disclosure provides a semiconductor device including a package structure comprising a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of bottom interconnects located on the second side of the package structure, each including: a bottom outer layer located on the second side of the package structure; and a hole surrounded by the bottom outer layer.

[0007] Another aspect of this disclosure provides a semiconductor device including a package structure having a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of bottom interconnects located on the second side of the package structure, each including: a bottom outer layer located on the second side of the package structure; a bottom inner layer surrounded by the bottom outer layer; and a cavity surrounded by the bottom inner layer.

[0008] Due to the semiconductor device design disclosed herein, varying densities of intermediate interconnects allow for greater design flexibility. Furthermore, the cavities in the intermediate and bottom interconnects can neutralize and reduce potential damaging stresses during the fabrication or handling of the semiconductor device. Consequently, the yield and reliability of the semiconductor device can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] When referring to the embodiments and the claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of this disclosure.

[0012] Figure 2 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3 yes Figure 2 A close-up cross-sectional view.

[0014] Figure 4 and Figure 5 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 6 yes Figure 5 A close-up cross-sectional view.

[0016] Figure 7 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8 yes Figure 7 A close-up cross-sectional view.

[0018] Figures 9 to 14 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 15 yes Figure 14 A close-up cross-sectional view.

[0020] Figure 16 It is along Figure 15 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0021] Figure 17 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 18 yes Figure 17 A close-up cross-sectional view.

[0023] Figure 19 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 20 yes Figure 19 A close-up cross-sectional view.

[0025] Figure 21 It is along Figure 20 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0026] Figure 22 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 23 yes Figure 22 A close-up cross-sectional view.

[0028] Figure 24 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element of this disclosure.

[0029] Figure 25 It is along Figure 24 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0030] Figure 26This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element of this disclosure.

[0031] Figure 27 It is along Figure 26 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0032] Figure 28 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element of this disclosure.

[0033] Figure 29 It is along Figure 28 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0034] Figure 30 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element of this disclosure.

[0035] Figure 31 It is along Figure 30 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0036] Figure 32 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element 1F of the present disclosure.

[0037] Figure 33 It is along Figure 32 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0038] The reference numerals in the attached figures are explained as follows:

[0039] 1A: Semiconductor components

[0040] 1B: Semiconductor components

[0041] 1C: Semiconductor components

[0042] 1D: Semiconductor components

[0043] 1E: Semiconductor components

[0044] 1F: Semiconductor components

[0045] 1F: Semiconductor components

[0046] 10: Preparation method

[0047] 100: Intermediate Layer Structure

[0048] 101: Intermediate Layer Base

[0049] 101L: lower part

[0050] 101U: Upper part

[0051] 103: Intermediate layer / insulating layer

[0052] 105: Intermediate layer wiring pattern

[0053] 107: Through-hole through the intermediate layer

[0054] 109: Intermediate Layer Base Pad

[0055] 111: Intermediate layer top pad

[0056] 210: The First Chip

[0057] 211: First basement

[0058] 213: First dielectric layer

[0059] 215: First component

[0060] 217: First conductive pad

[0061] 220: Second chip

[0062] 221: Second basement

[0063] 223: Second dielectric layer

[0064] 225: Second component

[0065] 227: Second conductive pad

[0066] 230: Third chip

[0067] 231: Third base

[0068] 233: Third dielectric layer

[0069] 235: Third component

[0070] 237: Third conductive pad

[0071] 300: Package structure

[0072] 300FS: First side

[0073] 300SS: Second side

[0074] 301: Packaging substrate

[0075] 303: Top encapsulation insulating layer

[0076] 305: Bottom encapsulation insulating layer

[0077] 307: Top Encapsulation Conductive Pad

[0078] 309: Bottom encapsulation conductive pad

[0079] 311: Through-hole for encapsulation

[0080] 313: Isolation layer

[0081] 400: Infrastructure

[0082] 401: Base Conductive Pad

[0083] 501: Top Interconnector

[0084] 501E: Top Outer Layer

[0085] 503: Lower adhesive pad

[0086] 505: Upper adhesive pad

[0087] 507: Third lower ring pad

[0088] 509: Third upper ring pad

[0089] 511: Third cavity

[0090] 601: Intermediate Interconnector

[0091] 601E: Middle Outer Layer

[0092] 601I: Middle Inner Layer

[0093] 603: First lower ring pad

[0094] 605: First upper ring pad

[0095] 607: First anti-corrosion layer

[0096] 609: Second anti-corrosion layer

[0097] 611: First cavity

[0098] 613: First round pad

[0099] 615: First upper circular pad

[0100] 701: Bottom interconnect

[0101] 701E: Bottom Outer Layer

[0102] 701I: Bottom Inner Layer

[0103] 703: Second lower ring pad

[0104] 705: Second upper ring pad

[0105] 711: Second cavity

[0106] 713: Second round pad

[0107] 715: Second upper circular pad

[0108] 801: Top and bottom filler layers

[0109] 803: Top molding layer

[0110] 805: Intermediate filler layer

[0111] 807: Intermediate forming layer

[0112] 809: Bottom Fill Layer

[0113] 901: Adhesion layer

[0114] 903: Auxiliary substrate

[0115] A1: Dashed line

[0116] A2: Dashed line

[0117] AL: Adhesion layer

[0118] A-A': line

[0119] B-B': Line

[0120] BL: Barrier Layer

[0121] C-C': Line

[0122] D1: Horizontal distance

[0123] D2: Horizontal distance

[0124] D3: Distance

[0125] D4: Distance

[0126] FL: Fill layer

[0127] IL: Isolation Layer

[0128] S11: Steps

[0129] S13: Steps

[0130] S15: Steps

[0131] S17: Steps

[0132] S19: Steps

[0133] S21: Steps

[0134] SL: Seed layer

[0135] X: Direction

[0136] Y: direction

[0137] Z: Direction Detailed Implementation

[0138] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of elements and arrangements are described below. Of course, this is merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, thus allowing the first and second features to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0139] Furthermore, spatial relative terms, such as “below,” “under,” “below,” “above,” and “up,” are used here for ease of description to describe the relationship between one element or feature and another element(s) shown in the figure. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientations described in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0140] It should be understood that when an element or layer is said to be "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to another element or layer, or there may be intermediate elements or layers.

[0141] It should be understood that although various elements may be described herein using terms such as first, second, etc., these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0142] Unless the context otherwise requires, when referring to orientation, layout, location, shape, size, quantity, or other measures, the terms such as “identical,” “equal,” “planar,” or “coplanar” used herein do not necessarily mean exactly identical orientation, layout, location, shape, size, quantity, or other measures, but rather that they include substantially identical orientation, layout, location, shape, size, quantity, or other measures within the range of acceptable variations that may occur, such as due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” can be exactly identical, equal, or planar, or they can be identical, equal, or planar within the range of acceptable variations that may occur, such as due to manufacturing processes.

[0143] In this disclosure, semiconductor devices generally refer to devices that function by utilizing the properties of semiconductors. Optoelectronic devices, light-emitting display devices, semiconductor circuits, and electronic devices are all included in the scope of semiconductor devices.

[0144] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in direction Z, and "below" (or "down") corresponds to the opposite direction of the arrow in direction Z.

[0145] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of this disclosure. Figure 2 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 3 yes Figure 2 A close-up cross-sectional view.

[0146] Reference Figures 1 to 3 In step S11, an intermediary layer structure 100 can be provided.

[0147] Reference Figure 2 and Figure 3 In some embodiments, the interposer structure 100 may be provided at the wafer level. The interposer structure 100 provided at the wafer level may then be sawn into chips to form an interposer chip. Alternatively, in this embodiment, the interposer structure 100 may be provided at the chip level.

[0148] Reference Figure 2 The interposer structure 100 may include an interposer substrate 101, an interposer insulating layer 103, an interposer wiring pattern 105, and a plurality of through-interposer vias 107.

[0149] In some embodiments, the interposer substrate 101 may be formed of a semiconductor, such as silicon (which may be crystalline silicon), germanium, silicon-germanium, gallium arsenide, glass, ceramic, or a semiconductor on an insulator structure (e.g., silicon on an insulator, which may be amorphous, polycrystalline, or crystalline silicon formed on glass). The interposer substrate 101 may be formed of an undoped material. Alternatively, the interposer substrate 101 may be formed of a rigid material having a Young's modulus of 100 GPa or higher. The interposer substrate 101 may have a smooth and / or flat surface. For example, the root mean square (RMS) surface roughness of the interposer substrate 101 may be 1.5 nanometers or less.

[0150] In some embodiments, the interposer substrate 101 may include a lower portion 101L and an upper portion 101U formed on the lower portion 101L. The upper portion 101U may include a through-interposer via 107 buried in the upper portion 101U. The through-interposer via 107 may not extend into the lower portion 101L. The lower portion 101L may be removed in a subsequent semiconductor process, for example, in a thinning process. With the removal of the lower portion 101L, the through-interposer via 107 may extend into the upper portion 101U.

[0151] Reference Figure 2 An interposer insulating layer 103 can be formed on an interposer substrate 101. An interposer wiring pattern 105 can be formed in the interposer insulating layer 103. The interposer wiring pattern 105 can be electrically connected to the through-hole 107 (e.g., vias in the interposer). Figure 3 (As shown). In some embodiments, the interposer insulating layer 103 may include oxides, nitrides, or oxynitrides, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. In some embodiments, the interposer wiring pattern 105 may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the interposer wiring pattern 105 may be a single wiring pattern. In some embodiments, partial or complete through-interposer vias 107 may be formed to penetrate the interposer insulating layer 103, thus exposing the top surface (not shown) of the interposer insulating layer 103.

[0152] Reference Figure 2 and Figure 3 The interposer structure 100 may include a plurality of interposer bottom pads 109 and a plurality of interposer top pads 111. It should be noted that, for clarity, only a portion of the interposer bottom pads 109 and a portion of the interposer top pads 111 are shown. The interposer bottom pads 109 may be disposed within the interposer insulating layer 103, substantially coplanar with the bottom surface of the interposer insulating layer 103, and electrically connected to the interposer wiring pattern 105. The interposer top pads 111 may be disposed within the interposer insulating layer 103, substantially coplanar with the top surface of the interposer insulating layer 103, and electrically connected to the interposer wiring pattern 105.

[0153] In some embodiments, the interposer pads 111 may be arranged more densely than the through-holes 107. For example, the horizontal distance D1 between the interposer pads 111 may be smaller than the horizontal distance D2 between the through-holes 107. In this case, the interposer wiring pattern 105 may serve as a rewiring pattern.

[0154] In some embodiments, the interlayer bottom pad 109 and the interlayer top pad 111 may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0155] For the sake of brevity, clarity, and ease of description, only one through-intermediate via 107 is described. In some embodiments, the through-intermediate via 107 may include a fill layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and an isolation layer IL.

[0156] In some embodiments, a filler layer FL may be formed to be embedded in the upper portion 101U of the interposer substrate 101. The filler layer FL may be formed of, for example, doped polysilicon, tungsten, copper, carbon nanotubes, or solder alloy.

[0157] In some embodiments, an isolation layer IL may be formed between the filler layer FL and the interposer substrate 101. The isolation layer IL may have a U-shaped cross-sectional profile. In some embodiments, the isolation layer IL may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The thickness of the isolation layer IL may be between about 50 nanometers and about 200 nanometers. In some embodiments, the isolation layer IL may be formed of, for example, p-xylene, epoxy resin, or poly(p-xylene). The thickness of the isolation layer IL may be between about 1 micrometer and about 5 micrometers. The isolation layer IL ensures that the filler layer FL is electrically isolated within the interposer substrate 101.

[0158] In some embodiments, the seed layer SL may have a U-shaped cross-sectional profile. The seed layer SL may be formed between the fill layer FL and the insulating layer IL. In some embodiments, the seed layer SL may have a thickness between about 10 nanometers and about 40 nanometers. In some embodiments, the seed layer SL may include, for example, at least one element selected from the group consisting of aluminum, gold, beryllium, bismuth, cobalt, copper, hafnium, indium, manganese, molybdenum, nickel, lead, palladium, platinum, rhodium, rhenium, argon, tantalum, tellurium, titanium, tungsten, zinc, and zirconium. During the formation of the fill layer FL, the seed layer SL may reduce the resistivity at the opening.

[0159] In some embodiments, the adhesive layer AL may have a U-shaped cross-sectional profile. The adhesive layer AL may be formed between the seed layer SL and the release layer IL. The seed layer SL may be formed of, for example, titanium, tantalum, titanium-tungsten, or manganese nitride. The seed layer SL can improve the adhesion between the seed layer SL and the release layer BL.

[0160] In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be located between the adhesive layer AL and the insulating layer IL. The barrier layer BL may be formed of, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer. The barrier layer BL may inhibit the diffusion of conductive material from the filler layer FL into the interposer substrate 101.

[0161] In some embodiments, the filler layer FL, seed layer SL, adhesion layer AL, barrier layer BL, and isolation layer IL may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sputtering, metal-organic chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0162] In some embodiments, the interposer base pad 109 may be optional. That is, the interposer wiring pattern 105 may be directly configured on the through-hole 107 and electrically connected to the through-hole 107.

[0163] Figure 4 and Figure 5 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 6 yes Figure 5 A close-up cross-sectional view. Figure 7 This is a cross-sectional schematic diagram illustrating a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 8 yes Figure 7 A close-up cross-sectional view.

[0164] Reference Figure 1 and Figures 4 to 8 In step S13, a first chip 210, a second chip 220, and a third chip 230 can be provided, and the first chip 210, the second chip 220, and the third chip 230 can be bonded to the interposer structure 100.

[0165] Reference Figure 4 The first chip 210 may include a first substrate 211, a first dielectric layer 213, a plurality of first element components 215, and a plurality of first conductive features.

[0166] In some embodiments, the first substrate 211 may be a bulk semiconductor substrate. The bulk semiconductor substrate may be composed of, for example, elemental semiconductors such as silicon or germanium, or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors.

[0167] In some embodiments, a plurality of first element components 215 may be formed on a first substrate 211. Some portions of the first element components 215 may be formed in the first substrate 211. The first element components 215 may be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, etc., or combinations thereof.

[0168] In some embodiments, a first dielectric layer 213 may be formed on a first substrate 211. The first dielectric layer 213 may be a stacked structure. The first dielectric layer 213 may include a plurality of insulating sublayers. The thickness of each insulating sublayer may be between about 0.5 micrometers and about 3.0 micrometers. The insulating sublayers may be formed of, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, a low-k dielectric material, or combinations thereof. The insulating sublayers may be formed of different materials, but are not limited thereto.

[0169] The dielectric constant of a low-k dielectric material can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of a low-k dielectric material can be less than 2.0. The insulating sublayer can be formed by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar processes. Planarization can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0170] In some embodiments, a first conductive feature may be formed in a first dielectric layer 213. The first conductive feature may include a first conductive line (not shown), a first conductive via (not shown), and a first conductive pad 217. The first conductive lines may be spaced apart from each other and may be horizontally arranged in the first dielectric layer 213 along the Z-direction. In this embodiment, the topmost first conductive line may be designated as the first conductive pad 217. The top surface of the first conductive pad 217 and the top surface of the first dielectric layer 213 may be substantially coplanar. The first conductive via may connect adjacent first conductive lines, adjacent first element components 215 and first conductive lines, and adjacent first conductive pads 217 and first conductive lines along the Z-direction. In some embodiments, the first conductive feature may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The first conductive feature may be formed during the formation of the first dielectric layer 213.

[0171] In some embodiments, the first element component 215 and the first conductive feature may jointly configure the functional unit of the first chip 210. In the description of this disclosure, a functional unit generally refers to a function-related circuit that has been divided into a separate unit. In some embodiments, the functional unit of the first chip 210 may include, for example, highly complex circuitry such as a processor core, memory controller, or accelerator unit. In some embodiments, the functional unit of the first chip 210 may include control circuitry and high-speed circuitry associated with the second chip 220, which will be described later. In some embodiments, the first chip 210 may be configured as a logic chip.

[0172] Reference Figure 4 The second chip 220 may include a second substrate 221, a second dielectric layer 223, a plurality of second element components 225, and a plurality of second conductive features, including a second conductive pad 227. The second substrate 221, the second dielectric layer 223, the second element components 225, and the second conductive features may be formed respectively and correspondingly from structures / materials similar to the first substrate 211, the first dielectric layer 213, the first element components 215, and the first conductive features, the description of which will not be repeated here.

[0173] In some embodiments, the second conductive feature may include a memory cell (not shown) formed in the second dielectric layer 223. Each memory cell may include an insulator-conductor-insulator structure and may be electrically coupled to a corresponding second conductive pad 227 and a corresponding second element component 225, respectively. In some embodiments, the second element component 225 and the second conductive feature may jointly configure the functional units of the second chip 220. In some embodiments, the functional units of the second chip 220 may include storage circuitry, control circuitry, and high-speed circuitry. In some embodiments, the second chip 220 may be configured as a memory chip. In some embodiments, the second chip 220 may be configured as a logic chip.

[0174] In some embodiments, the functional units of the second chip 220 may include only core memory circuitry, such as input and output (I / O) and clock circuitry. The functional units of the second chip 220 may not include any control circuitry or high-speed circuitry. In this case, the second chip 220 may cooperate with the first chip 210, which includes control circuitry and / or high-speed circuitry.

[0175] Reference Figure 4The third chip 230 may include a third substrate 231, a third dielectric layer 233, a plurality of third element components 235, and a plurality of third conductive features including a third conductive pad 237. The third substrate 231, the third dielectric layer 233, the third element components 235, and the third conductive features may be formed from structures / materials similar to those of the first substrate 211, the first dielectric layer 213, the first element components 215, and the first conductive features, respectively and accordingly, the description of which will not be repeated here. In some embodiments, the third chip 230 may be configured to perform analog-related programs. In some embodiments, the third chip 230 may be configured as a logic chip or a memory chip.

[0176] Reference Figure 5 The first chip 210, the second chip 220, and the third chip 230 can be sequentially bonded to the interposer structure 100 via a flip-chip bonding process using multiple top interconnects 501. For the sake of brevity, clarity, and ease of description, only one top interconnect 501 will be described. In some embodiments, the top interconnect 501 may be a microbump and may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof.

[0177] Reference Figure 5 and Figure 6 A lower adhesive pad 503 may be formed on and electrically connected to a corresponding intermediate layer top pad 111. An upper adhesive pad 505 may be formed below and electrically connected to a corresponding first conductive pad 217. A top interconnect 501 may be formed between the lower adhesive pad 503 and the upper adhesive pad 505. In some embodiments, the top interconnect 501 may be a solder ball and may be adhered to the lower adhesive pad 503 and / or the upper adhesive pad 505 by using a thermocompression process and / or a reflow process.

[0178] Reference Figure 5 and Figure 6 The functional units of the first chip 210, the second chip 220, and the third chip 230 can be electrically coupled to the through-intermediate via 107 via the top interconnect 501 and the intermediate wiring pattern 105. Therefore, the first chip 210, the second chip 220, and the third chip 230 can cooperate with each other.

[0179] Reference Figure 7 and Figure 8The top filler layer 801 may fill the space between the first chip 210 and the interposer insulating layer 103, the second chip 220 and the interposer insulating layer 103, and the third chip 230 and the interposer insulating layer 103. The top filler layer 801 may surround the top interconnect 501. In some embodiments, the top filler layer 801 may also seal a portion of the lateral surfaces (e.g., sides) of the chips 210, 220, and 230.

[0180] In some embodiments, the top underfill layer 801 can be fabricated by curing an underfill material composed of a crosslinked organic resin and inorganic particles with a low coefficient of thermal expansion (CTE) (up to 75% by weight). In some embodiments, the underfill material before curing can be formulated with a liquid resin (such as epoxy resin), a hardener (such as an anhydride or amine), an elastomer (for toughening), a catalyst (for promoting crosslinking), and other additives (for flow modification and adhesion).

[0181] The top filler layer 801 can adhere tightly to chips 210, 220, and 230, top interconnect 501, and interposer structure 100, so that the top filler layer 801 can redistribute stress and strain from CTE mismatch and mechanical shock on chips 210, 220, and 230. Therefore, the initiation and propagation of cracks in top interconnect 501 can be prevented or significantly reduced. Furthermore, the top filler layer 801 can provide protection for top interconnect 501 to improve the mechanical integrity of the configuration of interposer structure 100 and chips 210, 220, and 230. Additionally, the top filler layer 801 can provide partial protection against moisture ingress and other forms of contamination.

[0182] Reference Figure 7 and Figure 8 A top molding layer 803 can be formed to cover the top surfaces of chips 210, 220, and 230, as well as the interposer insulating layer 103. The top molding layer 803 can be fabricated using a molding compound, such as polybenzoxazole, polyimide, benzocyclobutene, epoxy resin laminate, or ammonium difluoride. The top molding layer 803 can be formed by compression molding, transfer molding, liquid encapsulation molding, or other methods. For example, the molding compound can be dispensed in liquid form. Subsequently, a curing process is performed to cure the molding compound. The formation of the molding compound can overflow from chips 210, 220, and 230, causing the molding compound to cover chips 210, 220, and 230.

[0183] Figures 9 to 14 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 15 yes Figure 14 A close-up cross-sectional view. Figure 16 It is along Figure 15 Cross-sectional views taken along lines A-A', B-B', and C-C'. Figure 17 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 18 yes Figure 17 A close-up cross-sectional view.

[0184] Reference Figure 1 and Figures 9 to 12 In step S15, the interposer structure 100 may be thinned to expose a plurality of through-interposer vias 107 in the interposer structure 100.

[0185] Reference Figure 9 A planarization process, such as mechanical polishing, chemical mechanical polishing, or other etching techniques, can be employed to remove excess portions of the top molding layer 803 and provide a substantially flat surface. Chips 210, 220, and 230 can be exposed after the planarization process.

[0186] Reference Figure 10 The auxiliary substrate 903 can be attached to the top molding layer 803 and chips 210, 220, 230 with the aid of the attachment layer 901. In some embodiments, attachment may include forming the attachment layer 901 on the top surface of chips 210, 220, 230, and attaching the auxiliary substrate 903 to the attachment layer 901. The auxiliary substrate 903 may have a dimension extending above chips 210, 220, 230.

[0187] In some embodiments, the auxiliary substrate 903 may be formed of a rigid material, including metals, glass, ceramics, etc. The adhesion layer 901 may be an adhesive tape or an adhesive. In some embodiments, the adhesion layer 901 may be a chip adhesion film, silver paste, or the like. In some embodiments, the adhesion layer 901 may further include gold, silver, aluminum oxide, or boron nitride particles.

[0188] Reference Figure 11 The lower portion 101L of the interposer substrate 101 can be removed to expose the through-interposer via 107 on the bottom surface of the interposer substrate 101. This removal can be performed by wafer grinding, mechanical grinding, polishing, or similar methods, or by chemical removal, such as wet etching. In this operation, the auxiliary substrate 903 can have sufficient thickness so that the interposer structure 100 does not deform, and the interposer structure 100 can serve as a carrier substrate for movement to subsequent process equipment.

[0189] Reference Figure 12 The auxiliary substrate 903 attached to chips 210, 220, and 230 can be removed. At this time, the attachment layer 901 can also be removed.

[0190] Reference Figure 1 and Figure 13 In step S17, a packaging structure 300 can be provided.

[0191] Reference Figure 13 The package structure 300 may include a package substrate 301, a top package insulating layer 303, a bottom package insulating layer 305, a plurality of top package conductive pads 307, a plurality of bottom package conductive pads 309, and a plurality of through-package vias 311.

[0192] Reference Figure 13 The encapsulation substrate 301 may be a laminate, but is not limited thereto. In some embodiments, the encapsulation substrate 301 may include an epoxy resin substrate material or BT resin (bismaleimide triazine). In some embodiments, the encapsulation substrate 301 may be a printed circuit board.

[0193] Reference Figure 13 The top encapsulation insulating layer 303 can be formed on the encapsulation substrate 301, and the bottom encapsulation insulating layer 305 can be formed under the encapsulation substrate 301. The top encapsulation insulating layer 303 and the bottom encapsulation insulating layer 305 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto deposited film, solder resist film, etc., or combinations thereof.

[0194] Reference Figure 14 A top encapsulation conductive pad 307 can be formed in a top encapsulation insulating layer 303. The top surface of the top encapsulation conductive pad 307 and the top surface of the top encapsulation insulating layer 303 can be substantially coplanar. A bottom encapsulation conductive pad 309 can be formed in a bottom encapsulation insulating layer 305. The top surface of the top encapsulation insulating layer 303 can be referred to as the first side 300FS. The bottom surface of the bottom encapsulation conductive pad 309 and the bottom surface of the bottom encapsulation insulating layer 305 can be substantially coplanar. The bottom surface of the bottom encapsulation insulating layer 305 can be referred to as the second side 300SS.

[0195] In some embodiments, the pad density of the top package conductive pad 307 (defined by the number of pads divided by the surface area of ​​the package insulating layer) may be greater than the pad density of the bottom package conductive pad 309. That is, the distance D3 between adjacent top package conductive pads 307 may be less than the distance D4 between adjacent bottom package conductive pads 309.

[0196] In some embodiments, the top encapsulation conductive pad 307 and the bottom encapsulation conductive pad 309 may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0197] For the sake of brevity, clarity, and ease of description, only one through-hole 311 will be described.

[0198] Reference Figure 13 A through-hole 311 can be formed, penetrating the top encapsulation insulating layer 303, the encapsulation substrate 301, and the bottom encapsulation insulating layer 305. The through-hole 311 can be electrically connected to the top encapsulation conductive pad 307 and the bottom encapsulation conductive pad 309, respectively. The through-hole 311 can be formed of, for example, copper or other suitable conductive materials. In some embodiments, an insulating layer 313 can cover the sidewalls of the through-hole 311 (e.g., ...). Figure 15 (As shown). The insulating layer 313 may be formed of, for example, silicon oxide or other suitable insulating materials.

[0199] Reference Figure 1 and Figures 14 to 16 In step S19, the interposer structure 100 and the package structure 300 can be bonded together by a plurality of intermediate interconnects 601.

[0200] Reference Figure 14 Intermediate interconnect 601 may be formed between the first side 300FS of package structure 300 and the interposer structure 100. Intermediate interconnect 601 may be electrically connected to the through-interposer via 107 and the top package conductive pad 307, respectively. In some embodiments, intermediate interconnect 601 may comprise lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, intermediate interconnect 601 may be solder balls. Solder balls may be initially formed by vapor deposition, electroplating, printing, solder transfer, or ball placement to form a layer of tin with a thickness of approximately 10 micrometers to 100 micrometers. Once a tin layer is formed on the first side 300FS of package structure 300, a repeated hot-flow process may be performed to shape the tin layer into the desired shape and form solder balls.

[0201] In the description of this disclosure, it is assumed that an XYZ coordinate system is used, where X and Y refer to the dimensions (directions) in a plane parallel to the main surface of the structure, and Z refers to the dimension (direction) perpendicular to the plane. When two features have substantially the same X and Y coordinates, these features are topographically aligned.

[0202] In some embodiments, the first chip 210 and the second chip 220 may have the same surface area (not shown) in a top view. The number of intermediate interconnects 601 graphically aligned with the first chip 210 (circled in dashed lines and labeled A1) may be greater than the number of intermediate interconnects 601 graphically aligned with the second chip 220 (circled in dashed lines and labeled A2). In other words, a first density of intermediate interconnects 601 graphically aligned with (or directly disposed under) the first chip 210 may be greater than a second density of intermediate interconnects 601 graphically aligned with (or directly disposed under) the second chip 220.

[0203] For the sake of brevity, clarity and ease of description, only one intermediate interconnect 601 will be described.

[0204] Reference Figures 14 to 16 In some embodiments, a first lower annular pad 603 may be formed on the top encapsulation conductive pad 307. A first upper annular pad 605 may be formed under the through-intermediate via 107. In some embodiments, the first lower annular pad 603 and the first upper annular pad 605 may be formed of, for example, copper or other suitable metals or metal alloys.

[0205] Intermediate interconnect 601 may include an intermediate outer layer 601E and a first cavity 611. The intermediate outer layer 601E may be formed between a first lower annular pad 603 and a first upper annular pad 605. The intermediate outer layer 601E, the first lower annular pad 603, and the first upper annular pad 605 may each have an annular cross-sectional profile. The space enclosed by the top encapsulation conductive pad 307, the first lower annular pad 603, the intermediate outer layer 601E, the first upper annular pad 605, and the through-hole 107 may be referred to as the first cavity 611.

[0206] In some embodiments, a first "seed" point is established at the non-conductive / non-wetting center of the annular pad at the top encapsulation conductive pad 307 for the accumulation of vaporized flux by using a first lower annular pad 603. As the vapor expands during the solder heating and liquefaction process, a first internal cavity (not shown) is formed, which is contained by the surface tension and viscosity of the molten solder. By including a second seed point in the first upper annular pad 605 on the through-hole 107, a second internal cavity (not shown) begins to engage with the first internal cavity, creating the resulting first cavity 611. The surface tension characteristics force the liquefied structure to form an external convex shape, which, upon cooling, solidifies into a barrel shape of the intermediate outer layer 601E, as the outer shell solidifies before the internal vaporized flux contracts.

[0207] In some embodiments, a relative volume of the first cavity 611 may be between 1% and 90% of the total volume of the intermediate interconnect 601. The volume of the first cavity 611 may be controlled by controlling the temperature and time during solder heating. The composition of the solder should balance the properties of the solder and solder alloy with the properties of the flux vapor. An exemplary solder compound may consist of any component of general soldering materials, such as solder, silver, and tin, and fluxes such as rosin, resin, activator, catalyst, and high-temperature boiling solvent.

[0208] Potentially damaging stresses during the manufacture or operation of semiconductor element 1A can be neutralized, reduced, or eliminated by the intermediate interconnect 601, which includes the first cavity 611. Therefore, the yield and reliability of semiconductor element 1A can be improved.

[0209] Reference Figure 17 and Figure 18 A first resist layer 607 may be formed on a first side 300FS of the encapsulation structure 300 and surround a first lower annular pad 603. The first resist layer 607 may also cover a portion of the outer surface of the intermediate outer layer 601E. A second resist layer 609 may be formed on the bottom surface of the interposer substrate 101 and surround a first upper annular pad 605. The second resist layer 609 may also cover a portion of the outer surface of the intermediate outer layer 601E. The first resist layer 107 and the second resist layer 609 may respectively comprise polybenzoxazole, polyimide, benzocyclobutene, epoxy resin laminate, or ammonium difluoride.

[0210] Reference Figure 17 and Figure 18 An intermediate filler layer 805 may be filled between the interposer structure 100 and the package structure 300. The intermediate filler layer 805 may surround the intermediate interconnect 601. In some embodiments, the intermediate filler layer 805 may also seal a portion of the lateral surface (e.g., side) of the interposer structure 100.

[0211] In some embodiments, the intermediate filler layer 805 may be formed by curing an underfill material composed of a crosslinked organic resin and low CTE inorganic particles (up to 75% by weight). In some embodiments, the underfill material prior to curing may be formulated with a liquid resin (such as epoxy resin), a curing agent (such as an anhydride or amine), an elastomer (for toughening), a catalyst (for promoting crosslinking), and other additives (for flow modification and adhesion).

[0212] The intermediate filler layer 805 can adhere tightly to the interposer structure 100 and the package structure 300 so that it can redistribute stress and strain from CTE mismatch and mechanical shock on the interposer structure 100. Therefore, the initiation and growth of cracks in the intermediate interconnect 601 can be prevented or significantly reduced. Furthermore, the intermediate filler layer 805 can provide protection for the intermediate interconnect 601 to improve the mechanical integrity of the configuration of the interposer structure 100 and the package structure 300. Additionally, the intermediate filler layer 805 can provide partial protection against moisture ingress and other forms of contamination.

[0213] Reference Figure 17 and Figure 18 The intermediate molding layer 807 can be formed to completely cover the interlayer structure 100. The intermediate molding layer 807 can be manufactured using a molding compound, such as polybenzoxazole, polyimide, benzocyclobutene, epoxy resin laminate, or ammonium difluoride. The intermediate molding layer 807 can be formed by compression molding, transfer molding, liquid encapsulation molding, or other methods. For example, the molding compound can be dispensed in liquid form. Subsequently, a curing process is performed to cure the molding compound. The formation of the molding compound can overflow the interlayer structure 100, causing the molding compound to cover the interlayer structure 100.

[0214] Figure 19 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 20 yes Figure 19 A close-up cross-sectional view. Figure 21 It is along Figure 20 Cross-sectional views taken along lines A-A', B-B', and C-C'. Figure 22 This is a cross-sectional schematic diagram illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 23 yes Figure 22 A close-up cross-sectional view.

[0215] Reference Figure 1 and Figures 19 to 23 In step S21, the package structure 300 and the base structure 400 can be bonded together by multiple bottom interconnects 701.

[0216] Reference Figure 19 and Figure 20A base structure 400 may be provided. The base structure 400 may comprise an epoxy-based material or BT resin. In some embodiments, the base structure 400 may be a laminate, but is not limited thereto. In some embodiments, the base structure 400 may be a printed circuit board. It should be noted that, for clarity, the wiring pattern of the base structure 400 is not shown. The wiring pattern of the base structure 400 may be electrically coupled to the bottom package conductive pad 309 via the bottom interconnect 701.

[0217] Reference Figures 19 to 21 Bottom interconnect 701 can be formed between the second side 300SS of package structure 300 and the base structure 400. Bottom interconnect 701 can be electrically connected to the bottom package conductive pad 309 and the base conductive pad 401 of the base structure 400, respectively and accordingly. In some embodiments, bottom interconnect 701 may include lead, tin, indium, bismuth, antimony, silver, gold, copper, nickel, or alloys thereof. In some embodiments, bottom interconnect 701 may be a solder ball. The solder ball can be initially formed by vapor deposition, electroplating, printing, solder transfer, or ball placement to form a layer of tin with a thickness of approximately 10 micrometers to 100 micrometers. Once the tin layer is formed on the second side 300SS of package structure 300, a reflow hot flow process can be performed to shape the tin layer into the desired shape and form the solder ball.

[0218] For the sake of brevity, clarity and ease of description, only one bottom interconnect 701 will be described.

[0219] Reference Figures 19 to 21 In some embodiments, a second lower annular pad 703 may be formed on the base conductive pad 401. A second upper annular pad 705 may be formed under the bottom encapsulation conductive pad 309. In some embodiments, the second lower annular pad 703 and the second upper annular pad 705 may be formed of, for example, copper or other suitable metals or metal alloys.

[0220] The bottom interconnect 701 may include a bottom outer layer 701E and a second cavity 711. The bottom outer layer 701E may be formed between a second lower annular pad 703 and a second upper annular pad 705. The bottom outer layer 701E, the second lower annular pad 703, and the second upper annular pad 705 may each have an annular cross-sectional profile. The space enclosed by the bottom encapsulation conductive pad 309, the second lower annular pad 703, the bottom outer layer 701E, the second upper annular pad 705, and the base conductive pad 401 may be referred to as the second cavity 711.

[0221] In some embodiments, a first "seed" point is established at the non-conductive / non-wetting center of the annular pad for the accumulation of vaporized flux by using a second lower annular pad 703 on the base conductive pad 401. As the vapor expands during the solder heating and liquefaction process, a first internal cavity (not shown) is formed, which is contained by the surface tension and viscosity of the molten solder. By including a second seed point in the second upper annular pad 705 on the bottom encapsulation conductive pad 309, a second internal cavity (not shown) begins to engage with the first internal cavity, creating the resulting second cavity 711. The surface tension characteristics force the formation of an external convexity on the liquefied structure, which, upon cooling, solidifies into a barrel shape of the bottom outer layer 701E, as the outer shell solidifies before the vaporized flux inside contracts.

[0222] In some embodiments, a relative volume of the second cavity 711 may be between 1% and 90% of the total volume of the bottom interconnect 701. The volume of the second cavity 711 may be controlled by controlling the temperature and time during solder heating. The composition of the solder should balance the properties of the solder and solder alloy with the properties of the flux vapor. An exemplary solder compound may consist of any component of general soldering materials, such as solder, silver, and tin, and fluxes such as rosin, resin, activator, catalyst, and high-temperature boiling solvent.

[0223] During the manufacture or operation of semiconductor element 1A, potentially damaging stresses can be neutralized, reduced, or eliminated by the bottom interconnect 701, which includes the second cavity 711. Therefore, the yield and reliability of semiconductor element 1A can be improved.

[0224] Reference Figure 22 and Figure 23 The bottom filler layer 809 may be filled between the package structure 300 and the base structure 400. The bottom filler layer 809 may surround the bottom interconnect 701. In some embodiments, the bottom interconnect 701 may also seal a portion of the lateral surface (e.g., side) of the package structure 300.

[0225] In some embodiments, the underfill layer 809 may be formed by curing an underfill material composed of a crosslinked organic resin and low CTE inorganic particles (up to 75% by weight). In some embodiments, the underfill material prior to curing may be formulated with a liquid resin (such as epoxy resin), a curing agent (such as an anhydride or amine), an elastomer (for toughening), a catalyst (for promoting crosslinking), and other additives (for flow modification and adhesion).

[0226] The underfill layer 809 can adhere tightly to the package structure 300 and the base structure 400 so that it can redistribute stress and strain from CTE mismatch and mechanical shock on the package structure 300. Therefore, the initiation and growth of cracks in the bottom interconnect 701 can be prevented or significantly reduced. Furthermore, the underfill layer 809 can provide protection for the bottom interconnect 701 to maintain the mechanical integrity of the modified configuration of the package structure 300 and the base structure 400. Additionally, the underfill layer 809 can provide partial protection against moisture ingress and other forms of contamination.

[0227] Figure 24 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element 1B of the present disclosure. Figure 25 It is along Figure 24 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0228] Reference Figure 24 Semiconductor element 1B can have the same characteristics as... Figure 18 Similar structures to those shown in the image. Figure 24 Zhongyu Figure 18 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0229] Reference Figure 24 and Figure 25 A first lower circular pad 613 may be formed on the top encapsulation conductive pad 307. A first upper circular pad 615 may be formed below the through-intermediate via 107. In some embodiments, the first lower circular pad 613 and the first upper circular pad 615 may be formed of, for example, copper or other suitable metal or metal alloy. An intermediate outer layer 601E may be formed between the first lower circular pad 613 and the first upper circular pad 615. The intermediate outer layer 601E may have an annular cross-sectional profile. The first lower circular pad 613 and the first upper circular pad 615 may each have a circular cross-sectional profile. The space enclosed by the top encapsulation conductive pad 307, the first lower circular pad 613, the intermediate outer layer 601E, the first upper circular pad 615, and the through-intermediate via 107 may be referred to as a first cavity 611.

[0230] Figure 26 This is a close-up cross-sectional schematic diagram of a semiconductor element 1C illustrating another embodiment of the present disclosure. Figure 27 It is along Figure 26 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0231] Reference Figure 26 Semiconductor element 1C can have the same characteristics as... Figure 23 A structure similar to the one shown. Figure 26 Zhongyu Figure 23Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0232] Reference Figure 26 and Figure 27 A second lower circular pad 713 may be formed on the base conductive pad 401. A second upper circular pad 715 may be formed below the bottom encapsulation conductive pad 309. In some embodiments, the second lower circular pad 713 and the second upper circular pad 715 may be formed of, for example, copper or other suitable metals or metal alloys. A bottom outer layer 701E may be formed between the second lower circular pad 713 and the second upper circular pad 715. The bottom outer layer 701E may have an annular cross-sectional profile. The second lower circular pad 713 and the second upper circular pad 715 may each have a circular cross-sectional profile. The space enclosed by the bottom encapsulation conductive pad 309, the second lower circular pad 713, the bottom outer layer 701E, the second upper circular pad 715, and the base conductive pad 401 may be referred to as a second cavity 711.

[0233] Figure 28 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the present disclosure of a semiconductor element 1D. Figure 29 It is along Figure 28 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0234] Reference Figure 28 Semiconductor element 1D can have the same characteristics as... Figure 24 A structure similar to the one shown. Figure 28 Zhongyu Figure 24 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0235] Reference Figure 28 and Figure 29 An inner intermediate layer 601I may be formed between the first lower circular pad 613 and the first upper circular pad 615, and on the inner surface of the outer intermediate layer 601E. The outer intermediate layer 601E and the inner intermediate layer 601I may each have an annular cross-sectional profile. The first lower circular pad 613 and the first upper circular pad 615 may each have a circular cross-sectional profile. The space enclosed by the top encapsulation conductive pad 307, the first lower circular pad 613, the inner intermediate layer 601I, the first upper circular pad 615, and the through-hole 107 may be referred to as the first cavity 611. In some embodiments, Figure 28 and Figure 29 The features described in the text can be applied to Figure 4 The embodiments described herein.

[0236] Figure 30 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element 1E of the present disclosure. Figure 31 It is along Figure 30 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0237] Reference Figure 30 Semiconductor element 1E can have the same characteristics as... Figure 26 A structure similar to the one shown. Figure 30 Zhongyu Figure 26 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0238] Reference Figure 30 and Figure 31 The bottom inner layer 701I can be formed between the second lower circular pad 713 and the second upper circular pad 715. The bottom outer layer 701E and the bottom inner layer 701I can each have an annular cross-sectional profile. The second lower circular pad 713 and the second upper circular pad 715 can each have a circular cross-sectional profile. The space enclosed by the bottom encapsulation conductive pad 309, the second lower circular pad 713, the bottom inner layer 701I, the second upper circular pad 715, and the base conductive pad 401 can be referred to as the second cavity 711.

[0239] Figure 32 This is a close-up cross-sectional schematic diagram illustrating another embodiment of the semiconductor element 1F of the present disclosure. Figure 33 It is along Figure 32 Cross-sectional views taken along lines A-A', B-B', and C-C'.

[0240] Reference Figure 32 Semiconductor element 1E can have the same characteristics as... Figure 18 Similar structures to those shown in the image. Figure 32 Zhongyu Figure 18 Identical or similar elements have been marked with similar reference symbols, and repeated descriptions have been omitted.

[0241] Reference Figure 32 and Figure 33 A third lower annular pad 507 may be formed on the top pad 111 of the intermediate layer. A third upper annular pad 509 may be formed under the first conductive pad 217. In some embodiments, the third lower annular pad 507 and the third upper annular pad 509 may be formed of, for example, copper or other suitable metals or metal alloys.

[0242] The top interconnect 501 may include a top outer layer 501E and a third cavity 511. The top outer layer 501E may be formed between a third lower annular pad 507 and a third upper annular pad 509. The top outer layer 501E, the third lower annular pad 507, and the third upper annular pad 509 may each have an annular cross-sectional profile. The space enclosed by the intermediate layer top pad 111, the third lower annular pad 507, the top outer layer 501E, the third upper annular pad 509, and the first conductive pad 217 may be referred to as the third cavity 511.

[0243] In some embodiments, a first "seeding" point is established at the annular non-conductive / non-wetting center for the accumulation of vaporized flux by using a third lower annular pad 507 on the top pad 111 of the intermediate layer. As the vapor expands during the heating and liquefaction of the solder, a first internal cavity (not shown) is formed, which is contained by the surface tension and viscosity of the molten solder. By including a second seed point on the third upper annular pad 509, a second internal cavity (not shown) begins to engage with the first internal cavity, creating the resulting third cavity 511. The surface tension characteristics force the liquefied structure to form an external convex shape, which, upon cooling, solidifies into a barrel shape of the top outer layer 501E, as the outer shell solidifies before the vaporized flux inside contracts.

[0244] In some embodiments, a relative volume of the third cavity 511 may be between 1% and 90% of the total volume of the top interconnect 501. The volume of the third cavity 511 may be controlled by controlling the temperature and time during solder heating. The composition of the solder should balance the properties of the solder and solder alloy with the properties of the flux vapor. An exemplary solder compound may consist of any component of general soldering materials, such as solder, silver, and tin, and fluxes such as rosin, resin, activator, catalyst, and high-temperature boiling solvent.

[0245] Potentially damaging stresses during the manufacture or operation of semiconductor element 1F can be neutralized, reduced, or eliminated by the top interconnect 501, which includes the third cavity 511. Therefore, the yield and reliability of semiconductor element 1F can be improved.

[0246] One aspect of this disclosure provides a semiconductor device including a package structure comprising a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of intermediate interconnects located between the first side of the package structure and the first chip and between the first side of the package structure and the second chip. The plurality of intermediate interconnects topographically aligned with the first chip includes a first density. The plurality of intermediate interconnects topographically aligned with the second chip includes a second density different from the first density.

[0247] Another aspect of this disclosure provides a semiconductor device including a package structure comprising a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of bottom interconnects located on the second side of the package structure, each including: a bottom outer layer located on the second side of the package structure; and a hole surrounded by the bottom outer layer.

[0248] Another aspect of this disclosure provides a semiconductor device including a package structure having a first side and a second side opposite to the first side; an interposer structure located above the first side of the package structure; a first chip located above the interposer structure; a second chip located above the interposer structure; and a plurality of bottom interconnects located on the second side of the package structure, each including: a bottom outer layer located on the second side of the package structure; a bottom inner layer surrounded by the bottom outer layer; and a cavity surrounded by the bottom inner layer.

[0249] Due to the semiconductor device design disclosed herein, varying densities of intermediate interconnects allow for greater design flexibility. Furthermore, the cavities in the intermediate and bottom interconnects can neutralize and reduce potential damaging stresses during the fabrication or handling of the semiconductor device. Consequently, the yield and reliability of the semiconductor device can be improved.

[0250] While this disclosure and its advantages have been detailed, it should be understood that other changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0251] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. A semiconductor element, comprising: An encapsulation structure includes a first side and a second side opposite to the first side; An intermediary layer structure is located above the first side of the encapsulation structure; A first chip is located above the interposer structure; A second chip is located above the interposer structure; as well as Multiple intermediate interconnects are located between the first side of the package structure and the first chip, and between the first side of the package structure and the second chip; The plurality of intermediate interconnects include: An intermediate outer layer is located between the first side of the encapsulation structure and the interlayer structure; An intermediate inner layer, surrounded by an intermediate outer layer; and A cavity, formed by the intermediary layer structure, the encapsulation structure, and the intermediate inner layer. The plurality of intermediate interconnects aligned with the first chip pattern include a first density, while the plurality of intermediate interconnects aligned with the second chip pattern include a second density different from the first density.

2. The semiconductor device of claim 1, wherein the first chip is configured as a logic chip and the second chip is configured as a memory chip.

3. The semiconductor element of claim 2, further comprising a base structure located below the second side of the package structure.

4. The semiconductor device of claim 3, wherein the interposer structure includes a plurality of through-interposer vias electrically connected to the plurality of intermediate interconnects.

5. The semiconductor device of claim 4, further comprising an intermediate fill layer located between the first side of the package structure and the interposer structure, and surrounding the plurality of intermediate interconnects.

6. The semiconductor element of claim 5 further includes a plurality of bottom interconnects located between the second side of the package structure and the base structure.

7. The semiconductor device of claim 6 further includes a plurality of through-package vias positioned along the package structure, wherein the plurality of intermediate interconnects and the plurality of bottom interconnects are electrically coupled through the plurality of through-package vias.

8. The semiconductor device of claim 7 further includes a bottom fill layer located between the package structure and the base structure, and surrounding the plurality of bottom interconnects.

9. The semiconductor element of claim 8, wherein the plurality of intermediate interconnects is a solder ball.

10. The semiconductor element of claim 1, further comprising a plurality of bottom interconnects located on the second side of the package structure, each comprising: A bottom outer layer is located on the second side of the packaging structure; A bottom inner layer, which is surrounded by the bottom outer layer; as well as A cavity, formed by the bottom inner layer.

11. The semiconductor device of claim 10, further comprising a plurality of through-package vias positioned along the package structure, wherein the plurality of intermediate interconnects and the plurality of bottom interconnects are electrically coupled through the plurality of through-package vias.

12. The semiconductor element of claim 11, further comprising a base structure positioned opposite the second side of the package structure and electrically connected to the plurality of bottom interconnects.

13. The semiconductor device of claim 12, further comprising an underfill layer located between the package structure and the base structure, and surrounding the plurality of under interconnects.

14. The semiconductor device of claim 13, further comprising an intermediate fill layer located between the first side of the package structure and the interposer structure, and surrounding the plurality of intermediate interconnects.

15. The semiconductor element of claim 14, wherein the first chip is configured as a logic chip and the second chip is configured as a memory chip.

16. The semiconductor device of claim 15, further comprising an upper circular pad and a lower circular pad; The upper circular pad is located between the bottom outer layer and the encapsulation structure; The lower circular pad is located between the bottom outer layer and the base structure.

Images