Micro-module test device and method based on standard interface definition

Abstract

The application relates to the field of microsystem technology, and discloses a micro-module test device and method based on a standard interface definition, which comprises a signal generating unit, an ADC conditioning circuit, a first ADC test device, an FPGA chip, a first DAC test device and a DAC conditioning circuit which are electrically connected in sequence, and further comprises an upper computer, a second ADC test device and a second DAC test device; the upper computer is electrically connected with the FPGA chip; the second ADC test device is electrically connected with the ADC conditioning circuit, the first ADC test device and the FPGA chip respectively; and the second DAC test device is electrically connected with the FPGA chip, the first DAC test device and the DAC conditioning circuit respectively. The application solves the problems of high test cost and lack of universality in the prior art.

Description

Technical Field

[0001] This invention relates to the field of microsystems technology, specifically a micromodule testing device and method based on standard interface definitions. Background Technology

[0002] ADC / DAC transceiver microsystems typically integrate multiple bare chips such as ADCs (analog-to-digital converters), DACs (digital-to-analog converters), and processors within a single package to achieve system-level functions such as analog-to-digital signal conversion and processing. Due to the testability limitations of these bare chips, the yield rate and testing costs of ADC / DAC transceiver microsystems are significant factors restricting their mass production applications. For example, in a typical application integrating six bare chips with a 90% yield rate, under a packaging process yield of 95%, the microsystem yield drops to approximately 50%, failing to meet mass production requirements. Therefore, it is essential to add appropriate process testing steps to the ADC / DAC micromodule to improve the product yield while controlling costs.

[0003] Currently, the industry's testing strategies / methods for ADC / DAC chips entering the mass production stage include:

[0004] 1) Wafer testing: Using test equipment and probe cards, low-speed electrical parameter testing and high-speed vector testing are performed on wafers to screen for defective chips. This testing method cannot cover all functions and data types, and the testing cost is relatively high.

[0005] 2) Micro-module testing: Currently, ADC / DAC micro-module testing devices are highly customized and lack versatility;

[0006] 3) Packaging test: After packaging the bare chip into a finished chip, the finished chip is subjected to final functional testing to screen for defective chips. This method cannot meet the testing requirements of bare chip / micro-module. Summary of the Invention

[0007] To overcome the shortcomings of existing technologies, this invention provides a micro-module testing device and method based on standard interface definitions, which solves the problems of high testing costs and lack of universality in existing technologies.

[0008] The technical solution adopted by the present invention to solve the above problems is:

[0009] A micro-module testing device based on a standard interface definition includes a signal generation unit, an ADC conditioning circuit, a first ADC testing device, an FPGA chip, a first DAC testing device, and a DAC conditioning circuit connected in sequence. It also includes a host computer, a second ADC testing device, and a second DAC testing device. The host computer is electrically connected to the FPGA chip. The second ADC testing device is electrically connected to the ADC conditioning circuit, the first ADC testing device, and the FPGA chip, respectively. The second DAC testing device is electrically connected to the FPGA chip, the first DAC testing device, and the DAC conditioning circuit, respectively.

[0010] As a preferred technical solution, the signal generation unit can generate two single-ended intermediate frequency signals with adjustable amplitude and frequency.

[0011] As a preferred technical solution, the host computer and the FPGA chip are electrically connected via a JTAG port.

[0012] As a preferred technical solution, the first DAC test device and the second DAC test device have a synchronization function, and the first ADC test device and the second ADC test device have a synchronization function.

[0013] As a preferred technical solution, it also includes a clock generation unit, which is electrically connected to the first ADC test device, the second ADC test device, the first DAC test device, the second DAC test device, and the FPGA chip, respectively.

[0014] As a preferred technical solution, the FPGA chip model is Vertex-7 FPGA.

[0015] As a preferred technical solution, the clock generation unit model is ADCLK946.

[0016] As a preferred technical solution, it also includes a spectrum analyzer, which is electrically connected to the output terminal of the signal generation unit and the output terminal of the DAC conditioning circuit, respectively.

[0017] As a preferred technical solution, the signal interfaces of the first ADC test device, the second ADC test device, the first DAC test device, and the second DAC test device all follow a unified standard interface definition. The signal interfaces of the first ADC test device, the second ADC test device, the first DAC test device, and the second DAC test device all include: analog channel signal interface, analog control signal interface, analog power signal interface, digital channel signal interface, digital control signal interface, digital power signal interface, and ground signal interface.

[0018] A micro-module testing method based on a standard interface definition is disclosed. The method employs a micro-module testing device based on a standard interface definition. A signal generation unit generates two single-ended intermediate frequency (IF) signals with adjustable amplitude and frequency. An ADC conditioning circuit is responsible for establishing the ADC peripheral circuit and converting single-ended to differential signals. A first and second ADC testing device are press-fitted to assemble the ADC micro-module. The ADC micro-module receives the differential conditioning signal and generates raw sampled data. The first and second ADC testing devices are based on a standard interface definition and are compatible with typical ADC micro-modules. An FPGA chip is responsible for configuring the ADC micro-module and organizing the raw data collected by the ADC micro-module, and uploading the organized ADC sampled data to a host computer for ADC dynamic performance analysis. The FPGA is also responsible for configuring the DAC micro-module and generating DAC transmit data. A first and second DAC testing device are press-fitted to assemble the DAC micro-module. The DAC micro-module transmits the data and converts it into a DA transmit signal. The first and second DAC testing devices are based on a standard interface definition and are compatible with typical DAC micro-modules. A DAC conditioning circuit is responsible for establishing the DAC peripheral circuit.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] The ADC / DAC micro-module testing device and method designed in this invention based on standard interface definition have general testing capabilities for typical ADC / DAC micro-modules, reducing the need for customized development of ADC / DAC micro-module testing devices, lowering testing costs, and improving testing efficiency. Attached Figure Description

[0021] Figure 1 A schematic diagram of the standard interface definition for a typical ADC / DAC micro-module test device;

[0022] Figure 2 for Figure 1 One of the magnified views of a section;

[0023] Figure 3 for Figure 1 The second enlarged view of a section;

[0024] Figure 4 This is a schematic diagram of the architecture of a micro-module testing device based on a standard interface definition according to the present invention;

[0025] Figure 5 This is a schematic diagram of an implementation example of a micro-module testing device based on a standard interface definition according to the present invention.

[0026] The labels and their corresponding names in the attached diagram are as follows: 1. Host computer, 2. Signal generation unit, 3. ADC conditioning circuit, 41. First ADC test device, 42. Second ADC test device, 5. FPGA chip, 61. First DAC test device, 62. Second DAC test device, 7. DAC conditioning circuit, 8. Spectrum analyzer, 9. Clock generation unit. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0028] Example 1

[0029] like Figures 1 to 5 As shown, the purpose of this invention is to design a set of testing devices and methods for typical ADC / DAC micro-modules based on standard interface definitions, thereby reducing the customization requirements of traditional ADC / DAC micro-module testing devices, improving the testing efficiency and yield of typical ADC / DAC micro-modules, and saving costs.

[0030] A test device and method for ADC / DAC micro-modules based on a standard interface definition is provided. The test device is a general-purpose ADC / DAC micro-module test device that can be adapted to typical ADC / DAC micro-modules with speeds of gigahertz level, including single-channel 16-bit and below, dual-channel 12-bit and below, and quad-channel 10-bit and below. This decouples the test device from typical ADC / DAC chips, improving the versatility and testing efficiency of the ADC / DAC micro-module test device.

[0031] The standard interface definition of the typical ADC / DAC micro-module test device is as follows: Figure 1As shown, it includes: analog channel signals (AT1P / N~AT8P / N), analog control signals (AC1P / N~AC16P / N), analog power signals (VA1&G1, VA2&G2), digital channel signals (DA0P / N~DA11P / N, DB0P / N~DB11P / N, DC0P / N~DC11P / N, DD0P / N~DD11P / N, DACP / N, DAOP / N, DBCP / N, DBOP / N, DCCP / N, DCOP / N, DDCP / N, DDOP / N), digital control signals (DC1P / N~DC16P / N), digital power signals (VD1&G1, VD2&G2), and ground signal (GND). Analog channel signals are located at the left, upper left, lower left, and right edges of the standard defined layout. Analog channel signals are isolated from other signals via ground or power signals. Analog channel signals are differential signals, with their P and N terminals closely adjacent. Analog control signals are located on the left and right sides of the outer ring of the standard defined layout. Analog control signals are differential signals, with their P and N terminals closely adjacent. Digital channel signals are located on the right, upper right, and lower right sides of the outer ring of the standard defined layout. Digital channel signals are differential signals, with their P and N terminals closely adjacent. Digital control signals are located on the upper, lower, and right sides of the outer ring of the standard defined layout. Digital control signals are differential signals, with their P and N terminals closely adjacent. Analog power signals are located on the left, upper left, lower left, upper, lower, and right sides of the inner ring of the standard defined layout. VA1 & G1 and VA2 & G2 are arranged alternately. The digital power signals are located in the upper right, lower right, and right sides of the inner circle of the standard defined layout, with VD1 & G1 and VD2 & G2 arranged alternately. The ground signal is tightly coupled to the power signals and to the analog channel signals, and is located in the center of the standard defined layout.

[0032] A test device and method for ADC / DAC micro-modules based on standard interface definitions, such as Figure 2As shown, the system includes: a signal generation unit 2, an ADC conditioning circuit 3, a first ADC testing device 41, a second ADC testing device 42, an FPGA chip 5, a clock generation unit 9, a first DAC testing device 61, a second DAC testing device 62, a DAC conditioning circuit 7, a signal receiving unit (spectrum analyzer 8), and a host computer 1. The signal generation unit 2 generates two single-ended intermediate frequency (IF) signals with adjustable amplitude and frequency. The ADC conditioning circuit 3 is responsible for establishing the ADC peripheral circuit and converting single-ended to differential signals. The first ADC testing device 41 and the second ADC testing device 42 can be press-fitted to ADC micro-modules. The ADC micro-modules receive differential conditioning signals and generate raw sampling data. The first ADC testing device 41 and the second ADC testing device 42 are based on the standard interface definition described in this invention and are compatible with typical ADC micro-modules. The first ADC testing device 41 and the second ADC testing device 42 have a synchronization function. The FPGA chip 5 is responsible for configuring the ADC micro-modules and organizing the raw data acquired by the ADC. The FPGA chip 5 uploads the processed ADC sampling data to the host computer 1 via the JTAG port for ADC dynamic performance analysis. The FPGA chip 5 is responsible for configuring the DAC micro-module and generating DAC transmission data. The first DAC test device 61 / second DAC test device 62 can be press-fitted to assemble the DAC micro-module. The DAC micro-module converts the transmission data into a DA transmission signal. The first DAC test device 61 / second DAC test device 62 are based on the standard interface definition described in this invention and are compatible with typical DAC micro-modules. The DAC conditioning circuit 7 is responsible for establishing the DAC peripheral circuit. The signal receiving unit is used to receive single-ended intermediate frequency signals and evaluate the DAC dynamic performance. The clock generation unit 9 is responsible for generating system clock, ADC sampling clock, DAC reference clock, and other signals.

[0033] The ADC / DAC micro-module testing device and method designed in this invention based on standard interface definition have general testing capabilities for typical ADC / DAC micro-modules, reducing the need for customized development of ADC / DAC micro-module testing devices, lowering testing costs, and improving testing efficiency.

[0034] Example 2

[0035] like Figures 1 to 5 As shown, as a further optimization of Embodiment 1, this embodiment also includes the following technical features based on Embodiment 1:

[0036] A standard interface definition suitable for ADC / DAC micro-module test devices, such as Figure 1As shown, it includes: analog channel signals (AT1P / N~AT8P / N), analog control signals (AC1P / N~AC16P / N), analog power signals (VA1&G1, VA2&G2), digital channel signals (DA0P / N~DA11P / N, DB0P / N~DB11P / N, DC0P / N~DC11P / N, DD0P / N~DD11P / N, DACP / N, DAOP / N, DBCP / N, DBOP / N, DCCP / N, DCOP / N, DDCP / N, DDOP / N), digital control signals (DC1P / N~DC16P / N), digital power signals (VD1&G1, VD2&G2), and ground signal (GND).

[0037] A test device and method for ADC / DAC micro-modules based on the above-mentioned standard interface definition, such as Figure 4 As shown, it includes: a signal generation unit 2, an ADC conditioning circuit 3, a first ADC testing device 41, a second ADC testing device 42, an FPGA chip 5, a clock generation unit 9, a first DAC testing device 61, a second DAC testing device 62, a DAC conditioning circuit 7, a signal receiving unit, and a host computer 1.

[0038] The specific implementation of the ADC / DAC micro-module test device and method based on the standard interface definition is as follows: Figure 5As shown, it includes a signal generation unit 2 composed of a signal source, an ADC conditioning circuit 3 composed of devices such as baluns or transformers, a first ADC test device 41 / second ADC test device 42 composed of high-performance socket fixtures, a clock generation unit 9 based on the ADCLK946 clock driver chip, a Vertex7 FPGA chip 5, a first DAC test device 61 and a second DAC test device 62 composed of high-performance socket fixtures, a DAC conditioning circuit 7 composed of devices such as baluns or transformers, a signal receiving unit composed of a spectrum analyzer 8, and a host computer 1. The ADC / DAC testing apparatus (first ADC testing apparatus 41, second ADC testing apparatus 42, first DAC testing apparatus 61, and second DAC testing apparatus 62) is based on the standard interface definition described in this invention and can adapt to typical ADC / DAC micro-modules with gigahertz speeds, including single-channel 16-bit and below, dual-channel 12-bit and below, and quad-channel 10-bit and below. In this example, the XX12D1600 is selected as the ADC micro-module under test. The ADC / DAC testing apparatus base adopts a coaxial probe bed structure with a probe bed area of ​​9mm*9mm, a probe spacing of 0.4mm, and a probe diameter of 0.3mm. The signal probes support a maximum signal transmission of 10Gbps, and the power probes support a maximum current density of 0.5A. This testing apparatus and method can complete the functional performance testing of typical ADC / DAC micro-modules, improving the versatility of ADC / DAC micro-module testing apparatuses and achieving cost reduction and efficiency improvement.

[0039] The signal source generates two intermediate frequency (IF) signals with a frequency range of 0–5 GHz and a power range of -75 dBm to 25 dBm. The ADC conditioning circuit 3 converts the two IF signals into differential IF signals via a balun and outputs them to the ADC testing device. The ADC testing device transmits the differential IF signal and power signal to the ADC micro-module in the fixture. Under the condition that the ADC micro-module is configured, it transmits the sampled data to the FPGA chip 5 through the ADC testing device. The FPGA chip 5 organizes the received raw data into a standard time domain signal and uploads it to the host computer 1 through the JTAG port. The host computer 1 performs further dynamic performance analysis on the received time domain signal. The FPGA chip 5 sends the configuration data and transmission data to the DAC testing device. After power supply and configuration, the DAC micro-module in the DAC testing device converts the transmission data into a DA transmit signal and transmits it to the spectrum analyzer through the DAC conditioning circuit 7. The spectrum analyzer analyzes the dynamic performance of the DAC micro-module.

[0040] As described above, the present invention can be implemented well.

[0041] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Based on the technical essence of the present invention, any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A micro-module testing device based on a standard interface definition, characterized in that, The system includes a signal generating unit (2), an ADC conditioning circuit (3), a first ADC testing device (41), an FPGA chip (5), a first DAC testing device (61), and a DAC conditioning circuit (7) connected in sequence. It also includes a host computer (1), a second ADC testing device (42), and a second DAC testing device (62). The host computer (1) is electrically connected to the FPGA chip (5). The second ADC testing device (42) is electrically connected to the ADC conditioning circuit (3), the first ADC testing device (41), and the FPGA chip (5), respectively. The second DAC testing device (62) is electrically connected to the FPGA chip (5), the first DAC testing device (61), and the DAC conditioning circuit (7), respectively. The first DAC testing device (61) and the second DAC testing device (62) have a synchronization function, and the first ADC testing device (41) and the second ADC testing device (42) have a synchronization function. The signal interfaces of the first ADC test device (41), the second ADC test device (42), the first DAC test device (61), and the second DAC test device (62) all follow a unified standard interface definition. In the standard interface definition, the analog channel signal is located at the left, upper left, lower left, and right edges of the standard definition layout. The analog channel signal is isolated from other signals by ground signals or power signals. The analog channel signal is a differential signal, and the P terminal and N terminal of the differential signal are closely adjacent. The analog control signals are located on the left and right sides of the outer ring of the standard defined layout. The analog control signals are differential signals, and the P and N terminals of the differential signals are closely adjacent. The digital channel signals are located on the right, upper right, and lower right of the outer ring of the standard defined layout. The digital channel signals are differential signals, and the P and N terminals of the differential signals are closely adjacent. The digital control signals are located on the top, bottom, and right sides of the outer ring of the standard defined layout. The digital control signals are differential signals, and the P and N terminals of the differential signals are closely adjacent. The analog power signals are located on the left, upper left, lower left, upper side, lower side, and right side of the inner circle of the standard defined layout, and the analog power signals are arranged in an alternating pattern. The digital power signals are located in the upper right, lower right, and right side of the inner circle of the standard defined layout, and the digital power signals are arranged in an alternating pattern. The ground signal is tightly coupled to the power signal and the analog channel signal. The ground signal is located in the center of the standard defined layout.

2. The micro-module testing device based on a standard interface definition according to claim 1, characterized in that, The signal generation unit (2) can generate two single-ended intermediate frequency signals with adjustable amplitude and frequency.

3. The micro-module testing device based on a standard interface definition according to claim 2, characterized in that, The host computer (1) and the FPGA chip (5) are electrically connected through the JTAG port.

4. The micro-module testing device based on a standard interface definition according to claim 1, characterized in that, It also includes a clock generation unit (9), which is electrically connected to the first ADC test device (41), the second ADC test device (42), the first DAC test device (61), the second DAC test device (62), and the FPGA chip (5), respectively.

5. A micro-module testing device based on a standard interface definition according to claim 1, characterized in that, The FPGA chip (5) is a Vertex-7 FPGA.

6. The micro-module testing device based on a standard interface definition according to claim 1, characterized in that, The clock generation unit (9) is model ADCLK946.

7. A micro-module testing device based on a standard interface definition according to any one of claims 1 to 6, characterized in that, It also includes a spectrum analyzer (8), which is electrically connected to the output of the signal generation unit (2) and the output of the DAC conditioning circuit (7).

8. A micro-module testing device based on a standard interface definition according to any one of claims 1 to 6, characterized in that, The signal interfaces of the first ADC test device (41), the second ADC test device (42), the first DAC test device (61), and the second DAC test device (62) all follow a unified standard interface definition. The signal interfaces of the first ADC test device (41), the second ADC test device (42), the first DAC test device (61), and the second DAC test device (62) all include: analog channel signal interface, analog control signal interface, analog power signal interface, digital channel signal interface, digital control signal interface, digital power signal interface, and ground signal interface.

9. A micro-module testing method based on standard interface definition, characterized in that, The micro-module testing device based on a standard interface definition, as described in any one of claims 1 to 6, utilizes a signal generation unit (2) to generate two single-ended intermediate frequency signals with adjustable amplitude and frequency; the ADC conditioning circuit (3) is responsible for establishing the ADC peripheral circuit and converting single-ended to differential signals; the first ADC testing device (41) and the second ADC testing device (42) are press-fitted to assemble the ADC micro-module, the ADC micro-module receives the differential conditioning signal, and generates the original sampling data; the first ADC testing device (41) and the second ADC testing device (42) are based on a standard interface definition and are compatible with typical ADCs. C micro-module; FPGA chip (5) is responsible for configuring the ADC micro-module and organizing the raw data collected by the ADC micro-module, and uploading the organized ADC sampling data to the host computer (1) for ADC dynamic performance analysis. FPGA is responsible for configuring the DAC micro-module and generating DAC transmission data. The first DAC test device (61) and the second DAC test device (62) press-fit the DAC micro-module. The DAC micro-module will transmit data and convert it into DA transmission signal. The first DAC test device (61) and the second DAC test device (62) are based on standard interface definition and are compatible with typical DAC micro-modules. The DAC conditioning circuit (7) is responsible for establishing the DAC peripheral circuit.

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