Display substrate, display panel and display device

Abstract

A display substrate, a display panel, and a display device are disclosed. The display substrate includes: a plurality of data lines disposed on a substrate, at least a portion of the data lines being located in a display area; a data driving chip located in a driving area; a plurality of fan-out lines, each fan-out line connecting one of the data lines and the data driving chip; wherein the plurality of fan-out lines are located in at least two conductive layers, and the orthographic projections of the fan-out lines in different conductive layers on the substrate overlap; a protective layer, at least a portion of which is located on the side of the top conductive layer away from the substrate, and the orthographic projection of the protective layer on the substrate overlaps at least with the orthographic projection of the fan-out lines in the top conductive layer on the substrate; the top conductive layer is the one furthest from the substrate among the at least two conductive layers, and the hardness of the protective layer is greater than the hardness of the fan-out lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Currently, display products can be categorized based on the location of the source driver chip: COG (chip on glass, where the chip is mounted on the display substrate and electrically connected to the driver circuit board via a flexible circuit board) products and COF (chip on film, where the IC is mounted on a circuit board and electrically connected to the driver circuit board via the circuit board) products. In COG display panels, the color filter substrate is positioned opposite the display substrate, with a portion of the display substrate extending beyond the color filter substrate. The data driver chip is located on the portion of the display substrate that extends beyond the color filter substrate. As living standards gradually improve, people have increasingly higher demands for the appearance design of display products, and current display products on the market strive for extremely narrow bezels. Summary of the Invention

[0003] In a first aspect, this disclosure provides a display substrate having a display area and a driving area located on one side of the display area, the display substrate comprising:

[0004] Multiple data lines disposed on a substrate, at least a portion of which are located in the display area;

[0005] The data driver chip is located in the driver area;

[0006] Multiple fan-out lines, each fan-out line connecting a data line to the data driver chip; wherein the multiple fan-out lines are located in at least two conductive layers, and the orthographic projections of the fan-out lines in different conductive layers on the substrate overlap.

[0007] A protective layer, at least a portion of which is located on the side of the top conductive layer away from the substrate, and the orthographic projection of the protective layer on the substrate overlaps at least with the orthographic projection of the fan-out line in the top conductive layer on the substrate; wherein the top conductive layer is the one furthest from the substrate among the at least two conductive layers, and the hardness of the protective layer is greater than the hardness of the fan-out line.

[0008] In some embodiments, a passivation layer is disposed on the side of the top conductive layer away from the substrate, and at least a portion of the protective layer is located on the side of the passivation layer away from the substrate.

[0009] In some embodiments, the protective layer is a continuous film.

[0010] In some embodiments, the top conductive layer is provided with a plurality of fan-out lines, the plurality of fan-out lines in the top conductive layer including: a plurality of first fan-out lines and a plurality of second fan-out lines, the first fan-out lines and the second fan-out lines being alternately arranged;

[0011] The protective layer includes: a plurality of first protective portions and a plurality of second protective portions spaced apart, wherein the first protective portions are located on the side of the passivation layer away from the substrate, and the orthographic projection of the first protective portion on the substrate overlaps with the orthographic projection of the first fan-out line on the substrate.

[0012] The second protective portion is located between the passivation layer and the substrate, and is in contact with the second fan-out line. The orthographic projection of the second protective portion on the substrate overlaps with the orthographic projection of the second fan-out line on the substrate.

[0013] In some embodiments, the second protective portion is a conductor and is located on the side of the second fan-out line facing the substrate, or the second protective portion is located on the side of the second fan-out line away from the substrate.

[0014] In some embodiments, the display substrate further includes a common electrode and pixel electrodes located in the display area.

[0015] When the protective layer is a continuous film layer, the protective layer is disposed in the same layer as the common electrode or the pixel electrode;

[0016] When the protective layer includes a first protective portion and a second protective portion, one of the first protective portion and the second protective portion is disposed in the same layer as the common electrode, and the other of the first protective portion and the second protective portion is disposed in the same layer as the pixel electrode.

[0017] In some embodiments, the display substrate further includes gate lines and data lines located in the display area;

[0018] The multiple fan-out lines are located in two conductive layers, one of which is the layer where the gate line is located, and the other of which is the layer where the data line is located.

[0019] In some embodiments, the source driver chip includes a plurality of driver groups arranged along a direction away from the display area, each driver group including a plurality of driver terminals, and each driver terminal being connected to a data line;

[0020] In this case, the center line connecting multiple drive ends in the same drive group is a convex shape that curves toward the display area.

[0021] In some embodiments, the display substrate further includes a conductive adhesive area, which is used to provide conductive adhesive that is electrically connected to a ground terminal;

[0022] The plurality of fan-out lines include at least one bent line, and the bent line and the conductive adhesive area overlap in a first direction, the first direction being the direction from the driving area to the display area;

[0023] The bending line includes: a first main line portion, a second main line portion, and a clearance portion connecting the two. The first main line portion is connected to the data driver chip, the second main line portion is connected to the data line, and the clearance portion is a bending line used to avoid the conductive adhesive area.

[0024] In some embodiments, there are multiple bend lines, and the avoidance portion of each bend line includes: at least one first line segment and at least one second line segment, the first line segment and the second line segment are alternately arranged, the first main line portion is connected to the first line segment, the extension direction of the first line segment forms a first acute angle with the first direction, the second line segment forms a second acute angle with the first direction, and the first acute angle is smaller than the second acute angle; in two adjacent bend lines, the distance between the two first line segments is greater than the distance between the two first main line portions.

[0025] Secondly, this disclosure also provides a display panel, including the above-described display substrate and a color filter substrate disposed opposite to the display substrate.

[0026] In some embodiments, the orthographic projection of the protective layer on the substrate includes a first projection portion and a second projection portion, wherein the orthographic projection of the color filter substrate on the substrate covers the first projection portion and does not overlap with the second projection portion.

[0027] In some embodiments, the widths of both the first projection portion and the second projection portion are between 0.1 and 0.4 mm in the direction from the driving area to the display area.

[0028] In some embodiments, an electrostatic discharge (ESD) protection layer is provided on the side of the color filter substrate away from the display substrate, and the display panel further includes a conductive adhesive that electrically connects the ESD protection layer to a ground terminal on the display substrate.

[0029] Thirdly, this disclosure also provides a display device, including the aforementioned display panel. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 This is a plan view of the display panel provided in some embodiments.

[0032] Figure 2 for Figure 1 A schematic diagram of the fan-out lines in a local area.

[0033] Figure 3 For along Figure 2 A cross-sectional view of line A-A' in the middle.

[0034] Figure 4 This is a plan view of a display substrate provided in some embodiments of this disclosure.

[0035] Figure 5 for Figure 4 A schematic diagram of the fan-out lines in a local area.

[0036] Figure 6 For along Figure 5 A cross-sectional view of line B-B' in the middle.

[0037] Figure 7 for Figure 4 Another schematic diagram of the fan-out lines in a local area.

[0038] Figure 8 For along Figure 7 A cross-sectional view of line C-C' in the middle.

[0039] Figure 9 This is a schematic diagram of the internal structure of the source driver chip provided in some embodiments of this disclosure.

[0040] Figure 10A This is a plan view of a display substrate provided in some other embodiments of this disclosure.

[0041] Figure 10B is Figure 10A A schematic diagram of a local area.

[0042] Figure 10C This is an enlarged schematic diagram of region A in Figure 10B.

[0043] Figure 11 This is a schematic diagram of two adjacent bends provided in some embodiments of this disclosure.

[0044] Figure 12 This is a schematic diagram of a display panel provided in some embodiments of the present disclosure.

[0045] Figure 13 For along Figure 12 A cross-sectional view of line D-D' in the middle.

[0046] Figure 14 for Figure 12 A plan view of the color filter substrate and protective layer in a local area. Detailed Implementation

[0047] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0049] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] Figure 1 Here is a plan view of the display panel provided in some embodiments, such as Figure 1 As shown, the display panel includes a display substrate 1 and a color filter substrate 2 disposed opposite to each other. The display substrate 1 has a display area AA and a peripheral area, the peripheral area surrounding the display area AA and including a driving area DA located on one side of the display area AA. The display substrate 1 includes multiple gate lines (not shown) and multiple data lines DL disposed on the substrate 1a. The multiple gate lines and multiple data lines DL are arranged intersectingly to define multiple pixel areas in the display area AA.

[0051] A data driver chip 10 and a bonding electrode PAD are also disposed on the substrate 1a. Both the data driver chip 10 and the bonding electrode PAD are located in the driving area DA, with the bonding electrode PAD positioned on the side of the data driver chip 10 furthest from the display area AA. One end of the flexible circuit board is electrically connected to the bonding electrode PAD, and the other end is electrically connected to the driving circuit board, used to provide signals from the driving circuit board to the display substrate 1. The data driver chip 10 is connected to the data line DL via a fan-out line 20 and provides data signals to the data line DL according to the driving signals provided by the driving circuit board.

[0052] During the manufacturing process of the display panel, after the display substrate 1 and the color filter substrate 2 are fabricated, the array substrate and the color filter substrate 2 are aligned. At this time, the color filter substrate 2 covers the driving area DA of the display substrate 1. In order to facilitate the electrical connection between the flexible circuit board and the display substrate 1, the color filter substrate 2 needs to be cut. Figure 1 The color filter substrate 2 in the text is the cut color filter substrate 2. For example... Figure 1 As shown, the color filter substrate 2 includes a first edge E1 near the driving region DA, and the orthographic projection of the first edge E1 on the substrate 1a intersects the orthographic projection of each fan-out line 20 on the substrate 1a.

[0053] Figure 2 for Figure 1 A schematic diagram of the fan-shaped lines in a local area. Figure 3 For along Figure 2 A cross-sectional view of line A-A', as shown Figure 2 and Figure 3 As shown, multiple fan-out lines 20 are distributed in different layers. For example, in two adjacent fan-out lines 20, one fan-out line 20 is located between the gate insulating layer GI and the substrate 1a, and the other fan-out line 20 is located between the gate insulating layer GI and the passivation layer PVX. However, in some products with high PPI (pixels per inch), the thickness of the passivation layer PVX is small, and it cannot effectively protect the fan-out lines 20 during the cutting of the color filter substrate 2. To prevent the fan-out lines 20 from being scratched during the cutting process of the color filter substrate 2, such as... Figure 3 As shown, in some products, a protective portion 30a is provided on the side of the passivation layer PVX away from the substrate 1a. The shape of the protective portion 30a is consistent with the shape of the fan-out line 20 located between the gate insulating layer GI and the passivation layer PVX, and the orthogonal projection of the protective portion 30a on the substrate 1a covers the orthogonal projection of the fan-out line 20 between the gate insulating layer GI and the passivation layer PVX on the substrate 1a. The protective portion 30a can be made of a material with high hardness, such as indium tin oxide (ITO).

[0054] but, Figure 3 The structure shown is difficult to apply to narrow-bezel products because: when Figure 3 When the structure described above is applied to narrow-bezel products, the spacing between fan-out lines 20 in the same layer decreases, and the spacing between protective parts 30a also needs to be reduced accordingly. However, since the exposure accuracy in the patterning process of protective parts 30a is lower than that in the patterning process of fan-out lines 20, when the distance between protective parts 30a decreases, some protective parts 30a may not be completely etched apart, resulting in uneven distribution of protective parts 30a and thus adverse effects. For example, protective parts 30a may generate parasitic capacitance with other conductive structures. Uneven distribution of protective parts 30a will lead to uneven distribution of parasitic capacitance, thereby affecting the signals on other conductive structures.

[0055] Figure 4 This is a plan view of a display substrate provided in some embodiments of this disclosure. Figure 5 for Figure 4 A schematic diagram of the fan-shaped lines in a local area. Figure 6 For along Figure 5 A cross-sectional view of line B-B', as shown Figures 4 to 6 As shown, the display substrate 1 has a display area AA and a driving area DA located on one side of the display area AA. The display substrate 1 includes: a substrate 1a, multiple data lines DL, multiple fan-out lines 20 disposed on the substrate 1a, and a data driver chip 10. At least a portion of the data lines DL are located in the display area AA. The data driver chip 10 is disposed in the driving area DA. The multiple fan-out lines 20 are disposed in the driving area DA, each fan-out line 20 corresponding to one data line DL. The fan-out lines 20 connect the corresponding data line DL to the data driver chip 10, thereby transmitting the data signal provided by the data driver chip 10 to the corresponding data line DL.

[0056] like Figure 6 As shown, multiple fan-out lines 20 are located in at least two conductive layers, with at least one fan-out line 20 in each conductive layer. The conductive layer furthest from the substrate 1a among the at least two conductive layers containing the multiple fan-out lines 20 is called the top conductive layer. The orthographic projections of the fan-out lines 20 in different conductive layers onto the substrate 1a overlap. That is, the orthographic projections of at least one fan-out line 20 in any conductive layer onto the substrate 1a overlap with the orthographic projections of fan-out lines 20 in other layers.

[0057] like Figure 5 and Figure 6As shown, the display substrate 1 further includes a protective layer 30, wherein at least a portion of the protective layer 30 is located on the side of the top conductive layer away from the substrate 1a, and the orthographic projection of the protective layer 30 on the substrate 1a overlaps with the orthographic projection of the fan-out lines 20 in the top conductive layer on the substrate 1a. For example, the orthographic projection of the protective layer 30 on the substrate 1a overlaps with the orthographic projection of one or more fan-out lines 20 in the top protective layer 30 on the substrate 1a. In one example, the orthographic projection of the protective layer 30 on the substrate 1a overlaps with the orthographic projection of each fan-out line 20 in the top protective layer 30 on the substrate 1a.

[0058] The protective layer 30 has a higher hardness than the fan-out line 20. For example, the material of the protective layer 30 includes indium tin oxide (ITO).

[0059] In this embodiment, the fan-out lines 20 connected to the data driver chip 10 are distributed in at least two conductive layers, and the orthographic projections of the fan-out lines 20 in different conductive layers on the substrate 1a overlap. Figure 2 Compared to the previous configuration, the area occupied by multiple fan-out lines 20 can be reduced. Therefore, when the display substrate 1 in this embodiment is used in a narrow bezel product, the spacing between the fan-out lines 20 will not be too small. Even if the protective layer 30 is designed as a structure of multiple protective parts, the situation where the protective parts in the same layer cannot be etched apart can be reduced.

[0060] In this embodiment, the display area AA is further provided with multiple gate lines, which are intersected and insulated from multiple data lines DL. The multiple gate lines and multiple data lines DL intersect to define multiple pixel areas, each pixel area being provided with a pixel electrode. In addition, the display area AA may also be provided with a common electrode, which is located on the side of the layer where the pixel electrode is located away from the substrate 1a. A slit is provided on the common electrode.

[0061] like Figure 6 As shown, in some embodiments, multiple fan-out lines 20 are distributed in two conductive layers, one of which is the layer containing the gate lines, and the other is the layer containing the data lines DL. That is, some fan-out lines 20 are disposed in the same layer as the gate lines, and other fan-out lines 20 are disposed in the same layer as the data lines DL. It should be noted that "disposed in the same layer" in the embodiments of this disclosure means that the two structures are formed in the same patterning process, so their materials are the same, but it does not mean that their distances from the substrate 1a are necessarily the same.

[0062] In one example, the fan-out lines 20 in the two conductive layers correspond one-to-one, and the orthographic projections of the corresponding fan-out lines 20 in the two conductive layers on the substrate 1a overlap. The two conductive layers are a top conductive layer and a bottom conductive layer, respectively. A passivation layer PVX is disposed on the side of the top conductive layer away from the substrate 1a, and a gate insulating layer GI is disposed between the bottom conductive layer and the top conductive layer.

[0063] In some embodiments, such as Figure 6 As shown, the protective layer 30 is located on the side of the passivation layer PVX away from the substrate 1a. The protective layer 30 is a continuous film layer. The protective layer 30 can be disposed in the same layer as the common electrode. In this case, the protective layer 30 can be fabricated simultaneously with the common electrode to simplify the fabrication process. Of course, in some other embodiments, the common electrode in the display area can be disposed on the side of the pixel electrode closer to the substrate 1a; in this case, the protective layer 30 can be disposed in the same layer as the pixel electrode.

[0064] Figure 7 for Figure 4 Another schematic diagram of the fan-out lines in a local area of ​​the center. Figure 8 For along Figure 7 A cross-sectional view of line C-C', as shown Figure 7 and Figure 8 As shown, in some embodiments, the protective layer 30 is no longer a continuous film layer. Specifically, each conductive layer has multiple fan-out lines 20, and the multiple fan-out lines 20 in the top conductive layer include a first fan-out line 21 and a second fan-out line 22, wherein the first fan-out line 21 and the second fan-out line 22 are alternately arranged. For example, the first fan-out line 21 and the second fan-out line 22 are arranged alternately.

[0065] The protective layer 30 includes a plurality of first protective portions 31 spaced apart and a plurality of second protective portions 32 spaced apart. The first protective portions 31 are located on the side of the passivation layer PVX away from the substrate 1a, and the orthographic projection of the first protective portion 31 on the substrate 1a overlaps with the orthographic projection of the first fan-out line 21 on the substrate 1a, thereby preventing the first fan-out line 21 from being damaged during the cutting process of the color filter substrate 2. The second protective portions 32 are located between the passivation layer PVX and the substrate 1a, and are in contact with the second fan-out line 22. The orthographic projection of the second protective portion 32 on the substrate 1a overlaps with the orthographic projection of the second fan-out line 22 on the substrate 1a.

[0066] In one example, the second protection part 32 is located on the side of the second fan-out line 22 away from the substrate 1a, thereby preventing the second fan-out line 22 from being damaged during the cutting process of the color filter substrate 2.

[0067] In another example, such as Figure 8As shown, the second protection part 32 is a conductor and is located on the side of the second fan-out line 22 facing the substrate 1a. In this case, the first protection part 31 can prevent the first fan-out line 21 from being damaged during the cutting process of the color filter substrate 2, and since the second protection part 32 is conductive, even if the first fan-out line 21 is damaged or even broken during the cutting process of the color filter substrate 2, the second protection part 32 can connect the two broken parts of the second fan-out line 22 to ensure that the signal can be transmitted.

[0068] In this embodiment, the first protective part 31 is disposed on the same layer as the common electrode, and the second protective part 32 is disposed on the same layer as the pixel electrode. This allows the first protective part 31 and the common electrode to be fabricated simultaneously, and the second protective part 32 and the pixel electrode to be fabricated simultaneously, simplifying the manufacturing process. Of course, in some other embodiments, the common electrode in the display area can be located on the side of the pixel electrode closer to the substrate 1a. In this case, the first protective part 31 can be disposed on the same layer as the pixel electrode, and the second protective part 32 can be disposed on the same layer as the common electrode.

[0069] The width of the first protective part 31 is 0.8 to 1.2 times the width of the first outgoing cable 21, and the width of the second protective part 32 is 0.8 to 1.2 times the width of the second outgoing cable 22, thereby improving the protection effect on the first outgoing cable 21 and the second outgoing cable 22. For example, the width of the first protective part 31 is 0.8, 0.9, 1, 1.1, or 1.2 times the width of the first outgoing cable 21. The width of the second protective part 32 is 0.8, 0.9, 1, 1.1, or 1.2 times the width of the second outgoing cable 22.

[0070] Figure 9 This is a schematic diagram of the internal structure of the source driver chip provided in some embodiments of this disclosure, such as... Figure 9 As shown, the source driver chip 10 includes multiple driver groups arranged along a direction away from the display area AA, and each driver group includes multiple driver terminals 11 (in Figure 9 In the diagram, different cross-sectional lines illustrate the driving terminals 11 in different driving groups, each driving terminal 11 connected to a data line DL. The center line connecting multiple driving terminals 11 within the same driving group is a convex shape curving towards the display area AA. When multiple driving terminals 11 within the same driving group are arranged in a straight line, to facilitate wiring between the source driver chip 10 and the fan-out lines 20 in the display area AA, the fan-out lines 20 at both ends need to be configured with a structure including vertical and inclined portions, with the vertical portion connected to the source driver chip 10; while when multiple driving terminals 11 within the same driving group are arranged in a straight line... Figure 9 When arranged as shown, the vertical portions of the fan-out lines 20 at both ends of the source driver chip 10 can be omitted, which helps to reduce the width of the driver area DA and facilitates the realization of a narrow bezel.

[0071] The number of drive ends 11 in each drive group can be the same or approximately the same. The center connection of the drive ends 11 in the same drive group can be an arc or a broken line.

[0072] In one example, the source driver chip 10 may further include multiple input terminals 12 for receiving signals provided by the flexible circuit board. Additionally, the source driver chip 10 may include alignment marks 13 to facilitate accurate placement of the source driver chip 10 at a target location on the substrate. The shape of the alignment marks 13 is not limited; for example, it may be a cross shape or other shapes.

[0073] Figure 10A This is a plan view of the display substrate provided in some other embodiments of this disclosure, such as... Figure 4 and 10A As shown, in some embodiments, the display substrate 1 further includes a conductive adhesive region CA, which is used to apply conductive adhesive that is electrically connected to the ground terminal. After the display substrate 1 and the matching substrate are assembled, conductive adhesive can be applied to the location of the conductive adhesive region CA, so that the conductive adhesive electrically connects the shielding layer on the matching substrate to the ground terminal.

[0074] In some embodiments, such as Figure 4 As shown, the display substrate 1 can be a right-angled rectangular structure. In other embodiments, such as... Figure 10A As shown, the display substrate 1 can be a rounded rectangle, and similarly, the display area AA can also be a rounded rectangle to meet diverse user needs. When the corners of the display substrate 1 are rounded, the conductive adhesive area CA is closer to the source driver chip 10. If the distance between the conductive adhesive area CA and the fan-out line 20 is too small, when large static electricity occurs or scratches are generated, the conductive adhesive in the conductive adhesive area CA is prone to short-circuiting or signal crosstalk with the fan-out line 20. To solve this problem, in this embodiment, a portion of the fan-out line 20 is... Figure 10C Structural design in the process.

[0075] Specifically, Figure 10B is Figure 10A A schematic diagram of a local area in the middle. Figure 10C This is an enlarged schematic diagram of region A in Figure 10B. The dashed line in Figure 10B represents the edge of the color filter substrate near the driving region DA. The orthographic projection of the color filter substrate onto the display substrate covers the entire region A and a portion of region B. Figures 10A to 10CAs shown, the multiple fan-out lines 20 include at least one bent line 201. The bent line 201 and the conductive adhesive area CA overlap in a first direction, which is the direction from the driving area DA to the display area AA. The overlap between the bent line 201 and the conductive adhesive area CA in the first direction means that, using a plane perpendicular to the first direction as a reference plane, the orthographic projection of the bent line 201 on the reference plane overlaps with the projection of the conductive adhesive of the conductive adhesive area CA on the reference plane.

[0076] The bending line 201 includes a first main line portion 20a, a second main line portion 20b, and a clearance portion 2011 connecting the two. The first main line portion 20a is connected to the data driver chip 10, the second main line portion 20b is connected to the data line DL, and the clearance portion 2011 is a bent line used to avoid the conductive adhesive area CA. This design can prevent the fan-out line 20 from short-circuiting with the conductive adhesive in the conductive adhesive area CA.

[0077] like Figure 10A As shown, the number of conductive adhesive areas CA is one or more. The data driver chip 10 connects multiple bend lines 201 near each conductive adhesive area CA. Each bend line 201 has a clearance portion 2011 including at least one first line segment 20c and at least one second line segment 20d, with the first line segment 20c and second line segment 20d alternating. A first main line portion 20a is connected to the first line segment 20c. The extension direction of the first line segment 20c forms a first acute angle α with a first direction (i.e., the direction from the driving area DA to the display area AA), and the first main line portion 20a forms a second acute angle β with the first direction. The first acute angle α is smaller than the second acute angle β. That is, the first main line portion 20a is relatively gentle, and the first line segment 20c is relatively steep.

[0078] In one example, the first acute angle α can be between 35° and 55°, and the second acute angle β can be between 60° and 80°. For example, the first acute angle is 45° and the second acute angle is 60°.

[0079] Figure 11 This is a schematic diagram of two adjacent bends provided in some embodiments of this disclosure. Since the exposure accuracy of traces at different angles may vary during manufacturing, to prevent short circuits between adjacent bends 201, in some embodiments, such as... Figure 11 As shown, in two adjacent bent lines 201, the distance a between the two first line segments 20c is greater than the distance b between the two first main line parts 20a.

[0080] It should be noted that two adjacent bend lines 201 mean that there are no other fan-out lines 20 between these two bend lines 201.

[0081] In some examples, the diagonal length of the display area AA is 5.05 inches. In two adjacent bend lines 201, the distance 'a' between two first line segments 20c is between 2.3 and 2.5 μm, and the distance 'b' between two adjacent first main line portions 20a is between 2.1 and 2.3 μm. For example, the distance 'a' between two first line segments 20c is 2.4 μm, and the distance 'b' between two adjacent first main line portions 20a is 2.2 μm.

[0082] In some embodiments, the extension directions of the second line segment 20d and the second main line portion 20b may both be the same as or substantially the same as the extension direction of the first main line portion 20a. The distance between two adjacent second line segments 20d in two adjacent bends may also be between 2.1 and 2.3 μm, for example, 2.2 μm.

[0083] It should be noted that, Figure 10C The example given uses a bent line consisting of two first segments 20c and one second segment 20d. In other examples, the number of first segments 20c and second segments 20d can also be different, as long as they can form a relief structure that bends away from the conductive adhesive area CA.

[0084] It should be noted that, Figure 5 Specifically, as shown in the enlarged schematic diagram of region B in Figure 10B, region B overlaps with the data driver chip 10 in the first direction, but does not overlap with the conductive adhesive region CA in the first direction. In this embodiment, the fan-out line 20 that overlaps with the conductive adhesive region CA in the first direction (as shown in the fan-out line 20 in region A of Figure 10B) may be provided with a clearance portion 2011. The fan-out line 20 that does not overlap with the conductive adhesive region CA in the first direction (as shown in the fan-out line 20 in region B of Figure 10B) is denoted as a first signal line. At least a portion of the first signal lines may not be provided with the aforementioned clearance portion 2011. At least one first signal line may include a vertical portion extending along the first direction and an inclined portion connecting the vertical portion and the data line DL.

[0085] Figure 12 This is a schematic diagram of a display panel provided in some embodiments of this disclosure. Figure 13 For along Figure 12 A cross-sectional view of line D-D' in the middle, as shown Figure 12 and Figure 13 As shown, the display panel includes the display substrate 1 in the above embodiment and the color filter substrate 2 disposed opposite to the display substrate 1.

[0086] Figure 14 for Figure 12In some embodiments, the orthographic projection of the first edge E1 of the color filter substrate 2 near the driving area DA on the substrate divides the orthographic projection of the protective layer 30 on the display substrate 1 into two parts: a first projection part and a second projection part. The orthographic projection of the color filter substrate 2 on the substrate 1a covers the first projection part and does not overlap with the second projection part, thereby ensuring that the protective layer 30 can protect the fan-out line 20 during the cutting process of the color filter substrate 2.

[0087] In some embodiments, such as Figure 14 As shown, the width W1 of the first projection portion in the first direction and the width W2 of the second projection portion in the first direction are both between 0.1 and 0.4 mm. In this case, even if there are process fluctuations during the cutting of the color filter substrate 2, the cutting line can fall on the protective layer 30, so that the protective layer 30 can play a good protective role; at the same time, it can prevent the protective layer 30 from being set too large and short-circuiting with other conductive structures.

[0088] In one example, the cutting precision is 0.15mm, the width W1 of the first projected portion in the first direction is greater than or equal to 0.15mm, for example, 0.15mm or 0.2mm; the width W2 of the second projected portion in the first direction is greater than or equal to 0.15mm, for example, 0.2mm or 0.3mm.

[0089] In some embodiments, such as Figure 13 As shown, an electrostatic discharge (ESD) shielding layer 3 is provided on the side of the color filter substrate 2 away from the display substrate 1. This ESD shielding layer 3 can be made of a transparent conductive material to prevent it from affecting the display effect. For example, the transparent conductive material is indium tin oxide (ITO). The display panel also includes a conductive adhesive 4, which electrically connects the ESD shielding layer 3 to the grounding terminal on the display substrate 1. This allows the static charge to be conducted to the grounding terminal when static electricity is generated on the color filter substrate 2, preventing static electricity from affecting the display.

[0090] In one example, conductive adhesive 4 can be silver adhesive.

[0091] This disclosure also provides a display device, which includes the display panel described in the above embodiments. The display device can be any product or component with display functionality, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0092] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, the display substrate having a display area and a driving area located on one side of the display area, characterized in that, The display substrate includes: Multiple data lines disposed on a substrate, at least a portion of which are located in the display area; The data driver chip is located in the driver area; Multiple fan-out lines, each fan-out line connecting a data line to the data driver chip; wherein the multiple fan-out lines are located in at least two conductive layers, and the orthographic projections of the fan-out lines in different conductive layers on the substrate overlap. A protective layer, at least a portion of which is located on the side of the top conductive layer away from the substrate, and the orthographic projection of the protective layer on the substrate overlaps at least with the orthographic projection of the fan-out line in the top conductive layer on the substrate; wherein the top conductive layer is the one furthest from the substrate among the at least two conductive layers, and the hardness of the protective layer is greater than the hardness of the fan-out line. The display substrate also has a conductive adhesive area, which is used to provide conductive adhesive that is electrically connected to the ground terminal; the multiple fan-out lines include at least one bent line, and the bent line and the conductive adhesive area overlap in a first direction, which is the direction from the driving area to the display area; The bending line includes: a first main line portion, a second main line portion, and a clearance portion connecting the two. The first main line portion is connected to the data driver chip, the second main line portion is connected to the data line, and the clearance portion is a bending line used to avoid the conductive adhesive area.

2. The display substrate according to claim 1, characterized in that, A passivation layer is disposed on the side of the top conductive layer away from the substrate, and at least a portion of the protective layer is located on the side of the passivation layer away from the substrate.

3. The display substrate according to claim 2, characterized in that, The protective layer is a continuous film.

4. The display substrate according to claim 2, characterized in that, The top conductive layer is provided with multiple fan-out lines, which include multiple first fan-out lines and multiple second fan-out lines, with the first fan-out lines and the second fan-out lines being arranged alternately. The protective layer includes: a plurality of first protective portions and a plurality of second protective portions spaced apart, wherein the first protective portions are located on the side of the passivation layer away from the substrate, and the orthographic projection of the first protective portion on the substrate overlaps with the orthographic projection of the first fan-out line on the substrate. The second protective portion is located between the passivation layer and the substrate, and is in contact with the second fan-out line. The orthographic projection of the second protective portion on the substrate overlaps with the orthographic projection of the second fan-out line on the substrate.

5. The display substrate according to claim 4, characterized in that, The second protective part is a conductor and is located on the side of the second fan-out line facing the substrate, or the second protective part is located on the side of the second fan-out line away from the substrate.

6. The display substrate according to claim 3 or 4, characterized in that, The display substrate also includes a common electrode and pixel electrodes located in the display area. When the protective layer is a continuous film layer, the protective layer is disposed in the same layer as the common electrode or the pixel electrode; When the protective layer includes a first protective portion and a second protective portion, one of the first protective portion and the second protective portion is disposed in the same layer as the common electrode, and the other of the first protective portion and the second protective portion is disposed in the same layer as the pixel electrode.

7. The display substrate according to any one of claims 1 to 5, characterized in that, The display substrate also includes gate lines and data lines located in the display area; The multiple fan-out lines are located in two conductive layers, one of which is the layer where the gate line is located, and the other of which is the layer where the data line is located.

8. The display substrate according to any one of claims 1 to 5, characterized in that, The source driver chip includes a plurality of driver groups arranged along a direction away from the display area, each driver group including a plurality of driver terminals, and each driver terminal being connected to a data line; In this case, the center line connecting multiple drive ends in the same drive group is a convex shape that curves toward the display area.

9. The display substrate according to any one of claims 1 to 5, characterized in that, The number of bends is multiple, and the avoidance portion of each bend includes: at least one first line segment and at least one second line segment, the first line segment and the second line segment are alternately arranged, the first main line portion is connected to the first line segment, the extension direction of the first line segment forms a first acute angle with the first direction, the second line segment forms a second acute angle with the first direction, and the first acute angle is smaller than the second acute angle; in two adjacent bends, the distance between the two first line segments is greater than the distance between the two first main line portions.

10. A display panel, characterized in that, It includes a display substrate as described in any one of claims 1 to 9, and a color filter substrate disposed opposite to the display substrate.

11. The display panel according to claim 10, characterized in that, The orthographic projection of the protective layer on the substrate includes a first projection portion and a second projection portion. The orthographic projection of the color filter substrate on the substrate covers the first projection portion and does not overlap with the second projection portion.

12. The display panel according to claim 11, characterized in that, In the direction from the driving area to the display area, the widths of both the first projection portion and the second projection portion are between 0.1 and 0.4 mm.

13. The display panel according to claim 10, characterized in that, An electrostatic discharge (ESD) protection layer is provided on the side of the color filter substrate away from the display substrate. The display panel also includes a conductive adhesive that electrically connects the ESD protection layer to the grounding terminal on the display substrate.

14. A display device, characterized in that, The display panel included in any one of claims 11 to 13.

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