Method for adjusting chip output characteristic parameters

Abstract

The present disclosure provides a chip output characteristic parameter adjustment method, and relates to the technical field of semiconductors. The method comprises the following steps: writing a first test data group into a chip to be adjusted according to a data write mode corresponding to data masking, wherein at least part of the data in the first test data group is masked; reading a first read data group from the chip to be adjusted according to a data read mode corresponding to data masking; and in the case where it is determined that the chip to be adjusted has a data read-write error according to the first test data group and the first read data group, adjusting a timing parameter of a test machine to adjust the output characteristic parameter of the chip to be adjusted through the adjustment of the timing parameter. According to the embodiment of the present disclosure, the yield of the chip can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for adjusting chip output characteristic parameters. Background Technology

[0002] In chip fabrication, testing is often required in the final stage to ensure the quality of the manufactured chip. During testing, to ensure the integrity of the chip's functionality, the yield can be improved by optimizing the chip's output performance in Final Test (FT).

[0003] However, existing adjustment methods cannot accurately adjust the chip's output performance parameters, resulting in low chip yield. Therefore, how to improve chip yield through accurate adjustment of chip output characteristics has become an urgent technical problem to be solved.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a method for adjusting chip output characteristic parameters, which at least to some extent overcomes the problem of low chip yield caused by the inability to accurately adjust chip output performance in related technologies.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for adjusting chip output characteristic parameters is provided, comprising:

[0008] According to the data writing method corresponding to the data masking, the first test data group is written to the chip to be adjusted, wherein at least part of the data in the first test data group is masked.

[0009] According to the data reading method corresponding to the data masking, read the first readout data group from the chip to be adjusted;

[0010] If it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the timing parameters of the test equipment are adjusted so as to adjust the output characteristic parameters of the chip to be adjusted.

[0011] In one embodiment, the timing parameters include: timing parameters of the data strobe signal.

[0012] If, based on the first set of test data and the first set of read data, it is determined that the chip to be adjusted has a data read / write error, the timing parameters of the test equipment are adjusted, including:

[0013] If a data readout error is determined in the chip to be adjusted based on the first test data group and the first readout data group, the timing parameters of the data strobe signal of the test instrument are adjusted. The clock deviation value of the chip to be adjusted is adjusted by adjusting the timing parameters of the data strobe signal. The clock deviation value is used to characterize the deviation between the data strobe signal and the clock signal.

[0014] In one embodiment, before writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask, the method further includes:

[0015] According to the data writing method corresponding to the data masking, the second test data group is written to the chip to be adjusted. The second test data group is generated according to the preset data masking rules, and at least part of the data in the second test data group is masked.

[0016] According to the data reading method corresponding to the data masking, read the second readout data group from the chip to be adjusted;

[0017] If a data write error is found in the chip to be adjusted based on the second test data group and the second read data group, the write clock of the test instrument is adjusted so as to adjust the output characteristic parameters of the chip to be adjusted.

[0018] In one embodiment, the chip to be adjusted includes a first-in-first-out (FIFO) register.

[0019] In addition, before writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data masking, the method also includes:

[0020] Write a preset data group to the FIFO register;

[0021] Read the third data group from the FIFO register;

[0022] If a data readout error is determined in the chip to be adjusted based on the preset data set and the third readout data set, the timing parameters are adjusted.

[0023] In one embodiment, the first data set to be tested is generated according to a preset data masking rule, which includes multiple data masking sub-rules.

[0024] The first set of data to be tested includes multiple data groups, each of which is generated by a data masking sub-rule. The number of data points masked varies in different data groups.

[0025] In one embodiment, the multiple data groups include at least one of the following:

[0026] The first type of data group is generated according to the first data masking sub-rule. The first type of data group includes multiple first data groups. The masked data of any two first data groups are different. The first data masking sub-rule is used to mask one data in each first data group.

[0027] The second type of data group is generated according to the second data masking sub-rule. The second type of data group includes multiple second data groups. At least one of the masked data in any two second data groups is different. The second data masking sub-rule is used to mask four data in each second data group.

[0028] The third data group is generated according to the third data masking sub-rule. The third data group includes multiple third data groups. At least one of the masked data in any two third data groups is different. The third data masking sub-rule is used to mask eight data in each third data group.

[0029] In one embodiment, adjusting the timing parameters of the test equipment includes:

[0030] The timing parameters of the test equipment are adjusted by the target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted.

[0031] According to the data writing method corresponding to the data masking, write the first test data group to the chip whose characteristic parameters have been adjusted;

[0032] According to the data readout method corresponding to the data masking, a new first readout data group is read out from the chip to be adjusted after the characteristic parameters have been adjusted.

[0033] If, after determining the characteristic parameters of the chip to be adjusted based on the first set of test data and the new first set of readout data, there is a data read / write error, return to the step of adjusting the timing parameters of the test instrument by the target adjustment amount until the data read / write of the chip to be adjusted is correct after determining the characteristic parameters of the chip to be adjusted based on the first set of test data and the new first set of readout data.

[0034] In one embodiment, adjusting the timing parameters of the test equipment by a target adjustment amount to obtain the adjusted timing parameters includes:

[0035] Within the preset range of timing parameter variations, the target adjustment amount is added to the timing parameters before adjustment to obtain the adjusted timing parameters.

[0036] In one embodiment, the testing equipment is used to adjust multiple chips sequentially.

[0037] After adjusting the timing parameters of the test equipment, the method also includes:

[0038] If the data read from the chip to be adjusted is correct by adjusting the timing parameters, the next chip in the series of chips to be adjusted is taken as the new chip to be adjusted.

[0039] Write the first test data group to the new chip to be adjusted according to the data writing method corresponding to the data masking.

[0040] According to the data reading method corresponding to the data masking, the new chip to be adjusted is read out to obtain a new first readout data group;

[0041] If, based on the first set of test data and the new first readout data set, it is determined that the new chip to be adjusted has a data readout error, the timing parameters of the test instrument are adjusted until the data readout of the new chip to be adjusted is correct. The next chip to be adjusted is then taken as the new chip to be adjusted, and the process of writing the first set of test data to the chip to be adjusted according to the data writing method corresponding to the data mask is returned until it is determined that the data readout of multiple chips is correct. The adjusted timing parameters corresponding to each chip are recorded.

[0042] In one embodiment, each first test data group includes N data points, and the chip to be adjusted includes N data shielding pins and N data transmission pins, where N is any integer.

[0043] According to the data writing method corresponding to the data masking, write the first test data group to the chip to be adjusted, including:

[0044] For the i-th data point in the first test data set, perform the following steps, where i is any positive integer less than or equal to N:

[0045] Transmit the i-th data to the i-th data transmission pin of the chip to be adjusted;

[0046] A level signal corresponding to the masking state of the i-th data is sent to the i-th data masking pin of the chip to be adjusted, so that after the chip receives the i-th data through the i-th data transmission pin, it can determine whether to mask and write the i-th data based on the level signal of the i-th data masking pin.

[0047] Specifically, when the i-th data is in a masked state, the level signal is the first level signal; when the i-th data is high and in an unmasked state, the level signal is the second level signal.

[0048] In one embodiment, writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask includes:

[0049] By masking the write command, the first test data group is written to the chip to be adjusted in the data writing method corresponding to the data masking;

[0050] And / or,

[0051] According to the data readout method corresponding to the data masking, the first readout data group is read from the chip to be adjusted, including:

[0052] By masking the read command, the first read data group is read from the chip to be adjusted using the data masking corresponding data read method.

[0053] In one embodiment, the method is applied to the high-speed testing phase of finished chip testing.

[0054] According to another aspect of this disclosure, a device for adjusting chip output characteristic parameters is provided, comprising:

[0055] The data writing module is used to write a first test data group to the chip to be adjusted according to the data writing method corresponding to the data masking. The first test data group is generated according to the preset data masking rules, and at least part of the data in the first test data group is masked.

[0056] The data readout module is used to read the first readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask;

[0057] The parameter adjustment module is used to adjust the timing parameters of the test instrument when it is determined that there is a data read / write error in the chip to be adjusted based on the first test data group and the first read data group, so as to adjust the output characteristic parameters of the chip to be adjusted by adjusting the timing parameters.

[0058] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described method for adjusting chip output characteristic parameters by executing the executable instructions.

[0059] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described method for adjusting chip output characteristic parameters.

[0060] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method for adjusting chip output characteristic parameters.

[0061] The chip output characteristic parameter adjustment method provided in this disclosure, since the first test data group is a data group generated according to a preset data masking rule with at least some data masked, can simulate the read and write function of the chip to be adjusted for complex data types by reading and writing the first test data group through the data masking function. Accordingly, in this disclosure embodiment, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write complex data types, avoiding the occurrence of unstable read and write operations for complex data types. Therefore, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, thereby improving the chip yield.

[0062] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0063] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0064] Figure 1 A flowchart illustrating a chip output characteristic parameter adjustment method in a related art is shown;

[0065] Figure 2 A system architecture diagram of a testing system provided in an embodiment of this disclosure is shown;

[0066] Figure 3 A schematic diagram of an exemplary transmission signal provided by an embodiment of this disclosure is shown;

[0067] Figure 4 A flowchart illustrating a method for adjusting chip output characteristic parameters according to an embodiment of this disclosure is shown.

[0068] Figure 5 A flowchart illustrating another method for adjusting chip output characteristic parameters provided in an embodiment of this disclosure is shown.

[0069] Figure 6 A flowchart illustrating another method for adjusting chip output characteristic parameters provided in an embodiment of this disclosure is shown.

[0070] Figure 7A schematic flowchart illustrating an exemplary method for adjusting chip output characteristic parameters provided in an embodiment of this disclosure is shown.

[0071] Figure 8 An exemplary shmoo test diagram before timing parameter adjustment, provided by an embodiment of this disclosure, is shown.

[0072] Figure 9 An exemplary shmoo test graph with adjusted timing parameters provided in an embodiment of this disclosure is shown;

[0073] Figure 10 A schematic diagram of a chip output characteristic parameter adjustment device provided in an embodiment of this disclosure is shown;

[0074] Figure 11 A structural block diagram of an electronic device provided in an embodiment of this disclosure is shown; and

[0075] Figure 12 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0076] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0077] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0078] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0079] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0080] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0081] During chip fabrication, factors such as process technology often lead to variations in values ​​such as time deviation t. DQSCK Output characteristic parameters that are too high or too low can affect the chip's read / write functionality, thus impacting chip yield. Therefore, adjusting the chip's output characteristics during the FT testing phase can improve chip yield.

[0082] In one related technology, Figure 1 A flowchart illustrating a method for adjusting chip output characteristic parameters in a related art is shown. Figure 1 As shown, the chip output characteristic parameter adjustment method in this related technology may include the following steps S11 to S15.

[0083] S11. Test the chip using the testing equipment. S12. Measure the output characteristic parameters of a large number of chips and use these as test results. S13. Obtain a unified adjustment scheme based on the test results. S14. Use the unified adjustment scheme to adjust most chips to their optimal parameters. S15. Measure the chip output characteristic parameters again.

[0084] However, existing adjustment methods cannot accurately adjust the chip's output characteristic parameters, resulting in low chip yield. Therefore, improving chip yield by increasing the adjustment accuracy of the chip's output characteristic parameters has become an urgent technical problem to be solved.

[0085] The inventors discovered through research that during high-speed chip testing, when performing read and write tests on chips using complex data types, the testing equipment may be unable to adjust the chip's output characteristic parameters to their optimal levels, leading to unstable chip data reading. In this specific situation, it's possible that the chip stores correct data, but the equipment cannot read the correct data and mistakenly identifies the chip as a failed chip, resulting in a loss of chip yield.

[0086] Based on this, this disclosure provides a scheme for adjusting chip output characteristic parameters, which can be applied to the FT testing scenario of chips. For example, it can be applied to the high-speed testing phase of FT testing. In this disclosure, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write data of complex data types, avoiding instability in the read / write of complex data types. Therefore, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read / write operations on complex data types, improving chip yield.

[0087] Before describing the technical solutions provided in the embodiments of this disclosure, the technical terms involved in the embodiments of this disclosure will be explained first.

[0088] (1) Final Test (FT), or FT for short, is used to test the performance of packaged chips and to detect the level of packaging process quality. FT testing may involve performing processes such as melting, reflow soldering, and aging tests on the chip to be tested. Furthermore, based on data transmission rate, FT testing can include high-speed testing and low-speed testing phases. For example, high-speed testing may include high-speed operation testing, and low-speed testing may include low-speed array testing.

[0089] (2) Data Strobe (DQS), which is used for data synchronization.

[0090] (3) Clock deviation value t DQSCK It is used to characterize the deviation between the data strobe signal DQS and the clock signal CK. Specifically, it can be the interval between the crossover point of the clock signal CK and the crossover point of the data strobe signal DQS.

[0091] (4) Data Mask (DM), also known as partial write.

[0092] After introducing the technical terminology, the following description will continue to describe the test system involved in the embodiments of this disclosure. Figure 2 A system architecture diagram of a test system provided in an embodiment of this disclosure is shown. Figure 2As shown, the test system may include a test bench 10 and multiple chips 21-2M placed on the test bench 10. Chips 21-2M can serve as devices under test (DUTs). The test bench 10 can be an automatic test equipment (ATE). For example, the test bench 10 can be a bench with FT testing capabilities, such as a high-speed bench.

[0093] In this embodiment of the disclosure, the test equipment 10 can select the chip to be adjusted from chips 21 to 2M, and write test data groups such as a first test data group and a second test data group to the chip to be adjusted. Each test data group may include N data points, where N is a positive integer greater than 1. For example, N can be the burst length of the data, such as 8 or 16.

[0094] The chip to be adjusted may include, but is not limited to, N data transmission pins (DQ) and N data masking pins. The i-th data transmission pin is used to transmit the i-th data in the data set under test, and the i-th data masking pin is used to determine whether to mask and write the i-th data in the data set under test. For example, a first-level signal on the i-th data masking pin can indicate that the i-th data is in a masked state, in which case it is not written after being received. A second-level signal on the i-th data masking pin can indicate that the i-th data is in a masked state, in which case it is written to the memory cell of the chip to be adjusted after being received. Here, i is any positive integer less than or equal to N.

[0095] After introducing the testing system, the following will use the first test data group as an example to illustrate the test data group involved in the embodiments of this disclosure.

[0096] The first set of data to be tested, for example, can be called burst data.

[0097] In terms of data generation methods, in some embodiments, the first data set to be tested can be generated according to a preset data masking rule. This preset data masking rule may include one or more data masking sub-rules, each sub-rule having a different number of data masks. In other embodiments, the first data set to be tested can be randomly generated.

[0098] In terms of data format, at least a portion of the data in each first test data group is masked. In some embodiments, the first test data group can be divided into multiple data groups, with a different number of masked data in each group. For example, when the preset data masking rule includes multiple data masking sub-rules, each data group in the first test data group can be generated by one data masking sub-rule. Through this embodiment, since each data group in the multiple data groups corresponds to a data masking sub-rule, and the number of masked data in different data groups is different, the first test data group containing multiple data groups in this embodiment can fully simulate the complex data types in the actual read and write process, so that the read and write function of the chip to be adjusted for complex data types can be accurately simulated according to the first test data group in the embodiment. Furthermore, the output characteristics of the chip to be adjusted can be further accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, further improving the chip yield.

[0099] In one example, the first set of data to be tested may include at least one of the following data sets a1 to a3.

[0100] Data group a1 is a first-class data group generated according to the first data masking sub-rule. The first-class data group includes multiple first data groups, where the masked data of any two first data groups is different. The first data masking sub-rule is used to mask one data point in each first data group. For example, if the data group includes 16-bit data DM0-DM15, then 16 first data groups can be generated, with the masked data of the 16 first data groups sequentially being DM0-DM15.

[0101] Data group a2 is a second type of data group generated according to the second data masking sub-rule. This second type of data group includes multiple second data groups, where at least one of the masked data points in any two second data groups is different. The second data masking sub-rule is used to mask four data points in each second data group.

[0102] Data group a3 is a third-class data group generated according to the third data masking sub-rule. This third-class data group includes multiple third data groups, where at least one of the masked data points in any two third data groups is different. The third data masking sub-rule is used to mask eight data points in each third data group.

[0103] This example demonstrates how a series of first test data sets can be generated systematically to accurately simulate complex data types encountered in actual processes. This allows for further precise adjustment of the output characteristics of the chip under adjustment, thereby improving chip yield. Optionally, the inventors discovered through research on complex data types that the aforementioned data sets a1-a3 can accurately represent complex data types. Therefore, these three types of data sets can be used to simply and accurately simulate complex data types, ensuring adjustment accuracy while reducing the difficulty of read / write testing of the chip under adjustment.

[0104] In a specific example, taking a data set consisting of 16-bit data DM0-DM15 as an example, the first test data set can include the following three types.

[0105] First data group: The masked data of the first data group is the first bit data DM0, the masked data of the second data group is the second bit data DM2, ..., the masked data of the sixteenth data group is the sixteenth bit data DM15.

[0106] Second data group: The masked data in the generated first data group can be in the following order: DM0, DM1, DM2, DM3; DM0, DM1, DM4, DM5; DM0, DM1, DM6, DM7; DM0, DM1, DM8, DM9; DM0, DM1, DM10, DM11; DM0, DM1, DM12, DM13; DM0, DM1, DM14, DM15; DM2, DM3, DM4, DM5; DM2, DM3 DM6, DM7; DM2, DM3, DM8, DM9; DM2, DM3, DM10, DM11; DM2, DM3, DM12, DM13; DM2, DM3, DM14, DM15; DM4, DM5 , DM6, DM7; DM4, DM5, DM8, DM9; DM4, DM5, DM10, DM11; ...; DM10, DM11, DM14, DM15; DM12, DM13, DM14, DM15.

[0107] Third data group: The masked data in the generated third data group can be in the following order: DM0, DM2, DM4, DM6, DM9, DM11, DM13, DM15; DM1, DM3, DM5, DM7, DM8, DM10, DM12, DM14; DM0, DM2, DM4, DM6, DM8, DM10, DM12, DM14; DM1, DM3, DM5, DM7, DM9, DM11, DM13, DM15.

[0108] After introducing the first set of data to be tested, the data strobe signal in the embodiments of this disclosure will be described in conjunction with the accompanying drawings. Figure 3 A schematic diagram of an exemplary transmission signal provided by an embodiment of this disclosure is shown. Wherein, P represents transmitted data.

[0109] like Figure 3 As shown, the transmission delay t of the first signal transmission pin DQ7_A clk1 The transmission delay t with the second signal transmission pin DQ7_B clk2 There is a deviation Δt between the data delay and the data strobe signal. The larger the deviation Δt, the greater the probability of read / write failure. The transmission delay t can be adjusted by regulating the data strobe signal. ck2 Adjustments are made to reduce the deviation Δt, thereby improving the read and write stability of the chip.

[0110] In passing Figure 3 Having introduced the data gating signal, the following section will provide a detailed description of this exemplary implementation method in conjunction with the accompanying drawings and embodiments.

[0111] This disclosure provides a method for adjusting chip output characteristic parameters, which can be performed by a test equipment. Exemplarily, it can be performed by a high-speed test equipment used for performing Fourier Transform (FT) testing.

[0112] Figure 4 A flowchart illustrating a method for adjusting chip output characteristic parameters according to an embodiment of this disclosure is shown, as follows: Figure 4 As shown, the method for adjusting the chip output characteristic parameters provided in this embodiment includes the following steps S410 to S430.

[0113] S410, according to the data writing method corresponding to the data masking, a first test data group is written to the chip to be adjusted. The first test data group is generated according to a preset data masking rule, and at least a portion of the data in the first test data group is masked. It should be noted that the first test data group can be referred to in the relevant description in the above-mentioned parts of the embodiments of this disclosure, and will not be repeated here.

[0114] In S410, the first set of data to be tested can be written into the memory cell of the chip to be adjusted.

[0115] In some embodiments, S410 may include step A1.

[0116] Step A1: By using the mask write command, the first test data group is written to the chip to be adjusted in the data writing mode corresponding to the data mask.

[0117] In this embodiment, the chip to be adjusted can be written using the original data shielding function of the test equipment. The technical solution of this embodiment can be achieved by utilizing the original data shielding function, which reduces the difficulty of adjustment.

[0118] In one embodiment, S410 may include: for the i-th data in the first test data group, performing steps A21 to A22, where i is any positive integer less than or equal to N.

[0119] Step A21: Transmit the i-th data to the i-th data transmission pin of the chip to be adjusted.

[0120] Step A22: Send a level signal corresponding to the masking state of the i-th data to the i-th data masking pin of the chip to be adjusted. This allows the chip to determine whether to mask and write the i-th data after receiving it through the i-th data transmission pin, based on the level signal of the i-th data masking pin. Specifically, when the i-th data is in a masked state, the level signal is a first level signal; when the i-th data is in an unmasked state, the level signal is a second level signal. One of the first and second level states is high, and the other is low.

[0121] For example, when the i-th data shield pin is in the first level state, the i-th data is not written, and when the i-th data shield pin is in the second level state, the i-th data is written.

[0122] For example, if the test machine transmits the data "10110110" to the chip to be adjusted, and the fourth data shielding pin is a first-level signal while the other data shielding pins are second-level signals, then the data "101X0110" can be written to the chip to be adjusted, where X indicates no writing (i.e., data shielding).

[0123] Through steps A21 and A22 above, the data corresponding to the data shield can be written through the data transmission pin and the data shield pin, thus realizing the correct writing of the data shielding function, thereby ensuring the reliability of the test and the reliability of the output characteristic parameter adjustment.

[0124] S420 reads the first readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask.

[0125] In S420, the first readout data group can be read from the memory cell of the chip to be adjusted.

[0126] In some embodiments, S420 may include step B1.

[0127] Step B2: By masking the read command, the first read data group is read from the chip to be adjusted using the data read method corresponding to the data masking.

[0128] In this embodiment, the chip to be adjusted can be read out using the original data shielding function of the test equipment. The technical solution of this embodiment can be achieved by using the original data shielding function, which reduces the difficulty of adjustment.

[0129] In one embodiment, S410 may include: performing steps B21 to B12 for the i-th data in the first test data group.

[0130] Step B21: Obtain the level signal of the i-th data shield pin.

[0131] Step B22: Determine whether to read the i-th data based on the level signal of the i-th data shield pin. Specifically, when the i-th data shield pin is in the first level state, the data of the i-th data transmission pin is not read; and when the i-th data shield pin is in the second level state, the data of the i-th data transmission pin is read.

[0132] For example, if the data on the 8 data transmission pins of the chip to be adjusted is "10110110", the 4th data shielding pin is a first level signal, and the other data shielding pins are second level signals, then the data "101X0110" can be read from the chip to be adjusted, where X indicates that it is not read (i.e., data shielding).

[0133] Through steps B21 and B22 above, the data corresponding to the data shield can be read out through the data transmission pin and the data shield pin, realizing the correct writing of the data shield function, thereby ensuring the reliability of the test and the reliability of the output characteristic parameter adjustment.

[0134] S430: If it is determined that there is a data read / write error in the chip to be adjusted based on the first test data group and the first read data group, the timing parameters of the test equipment are adjusted so as to adjust the output characteristic parameters of the chip to be adjusted.

[0135] The timing parameters of the test equipment can be parameters that affect the output characteristics of the chip to be adjusted. For example, they can be the timing parameters of the test equipment's data strobe signal, the timing parameters of the test equipment's write clock, etc., without specific limitations. In some examples, the timing parameters of the data strobe signal can be the time value of the data strobe signal; for example, timing parameters can also be parameters that can affect the output characteristics of the chip to be adjusted, such as the period of the data strobe signal and the start time of the rising edge, without specific limitations.

[0136] The output characteristic parameters of the chip to be adjusted can be parameters that characterize the output characteristics of the chip. For example, it could be the clock skew value t. DQSCK Among them, the clock deviation value t DQSCK Please refer to the relevant descriptions in the above sections of the embodiments of this disclosure, which will not be repeated here.

[0137] In some embodiments, a data read / write error can be determined to exist in the chip to be adjusted if the first test data group and the first read data group are inconsistent. Optionally, a correct read / write operation of the chip to be adjusted can be determined if the first test data group and the first read data group are consistent. For example, if the first test data group is "101X0110" and the first read data group is "100X0110", a data read / write error can be determined to exist in the chip to be adjusted.

[0138] In some embodiments, the timing parameters of the test equipment may include the timing parameters of the data strobe signal, and S430 may include the following step C1.

[0139] Step C1: If it is determined that there is a data readout error in the chip to be adjusted based on the first test data group and the first readout data group, the timing parameters of the data strobe signal of the test instrument are adjusted so as to adjust the clock deviation value of the chip to be adjusted through the adjustment of the timing parameters. The clock deviation value is used to characterize the deviation value between the data strobe signal and the clock signal.

[0140] In this embodiment, the data strobe signal can affect the clock deviation value t of the chip to be adjusted. DQSCK And the clock offset value t of the chip to be adjusted. DQSCK If the value is too large or too small, it will affect the chip's read and write functions. Accordingly, step C1 in this embodiment can accurately adjust the output characteristics of the chip to be adjusted, thereby improving the chip yield.

[0141] In some embodiments, S430 may include the following steps C2 to C5.

[0142] Step C2 involves adjusting the timing parameters of the test equipment by the target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted.

[0143] In one example, step C2 may include: within a preset timing parameter variation range, adding a target adjustment amount to the timing parameters before adjustment to obtain the adjusted timing parameters. For example, the preset parameter variation range can be [1.0 ns (nanoseconds), 3.5 ns]. For example, the target adjustment amount can be 5 ps (picoseconds). It should be noted that the preset parameter variation range and the target adjustment amount can also be set to other values ​​according to actual conditions and specific needs, without specific limitations. In this example, the timing parameters can be precisely adjusted by adding a target adjustment amount each time, thereby enabling fine-tuning of the timing parameters of the test equipment, improving the adjustment accuracy of the output characteristics of the chip to be adjusted, and further improving the chip yield.

[0144] In another example, step C2 may include: within a preset range of timing parameter variations, subtracting the target adjustment amount from the timing parameters before adjustment to obtain the adjusted timing parameters.

[0145] Step C3 involves writing the first test data group to the chip whose characteristic parameters have been adjusted, according to the data writing method corresponding to the data masking. Step C3 can be found in the above description of S410 in the embodiments of this disclosure, and is not specifically limited thereto.

[0146] Step C4: According to the data readout method corresponding to the data masking, read out the new first readout data group from the chip to be adjusted after the characteristic parameters have been adjusted. Step C3 can be found in the above description of S420 in the embodiments of this disclosure, and is not specifically limited thereto.

[0147] Step C5: If, based on the first test data set and the new first read data set, it is determined that there is a data read / write error in the chip to be adjusted after the characteristic parameters have been adjusted, return to the step of adjusting the timing parameters of the test instrument by the target adjustment amount (i.e., return to step C2, i.e., cyclically execute steps C2 to C5) until the data read / write of the chip to be adjusted is correct after the characteristic parameters have been adjusted based on the first test data set and the new first data set.

[0148] Optionally, steps C2 to C5 above can be implemented using the data strobe traversal function of the test equipment. For example, under this traversal function, the data strobe of the equipment can be set to scan from 1.0ns to 3.5ns, with a step size of 5ps.

[0149] In this embodiment, the timing parameters of the test machine can be accurately and meticulously adjusted in an orderly manner through the above steps C2 to C5, taking into account both adjustment accuracy and adjustment efficiency.

[0150] It should be noted that other methods can also be used to adjust the timing parameters of the test equipment in the S430, and there are no specific restrictions on this.

[0151] The chip output characteristic parameter adjustment method provided in this disclosure, since the first test data group is a data group generated according to a preset data masking rule with at least some data masked, can simulate the read and write function of the chip to be adjusted for complex data types by reading and writing the first test data group through the data masking function. Accordingly, in this disclosure embodiment, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write complex data types, avoiding the occurrence of unstable read and write operations for complex data types. Therefore, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, thereby improving the chip yield.

[0152] In some embodiments, the test equipment is used to adjust multiple chips sequentially. Accordingly, after S430, the method for adjusting the chip output characteristic parameters may further include steps D1 to D4.

[0153] Step D1: After adjusting the timing parameters to ensure correct data reading from the chip to be adjusted, the next chip in the sequence of chips to be adjusted is selected as the new chip to be adjusted. For example, see [link to example]. Figure 2 Chips 21-2M can be used sequentially as the chips to be adjusted.

[0154] Step D2: Write the first test data group to the new chip to be adjusted according to the data writing method corresponding to the data mask. Step D2 can be found in the above description of S410 in the embodiments of this disclosure, and will not be repeated here.

[0155] Step D3 involves reading data from the new chip to be adjusted according to the data reading method corresponding to the data masking, to obtain a new first readout data group. Step D3 can be found in the description of S420 above in the embodiments of this disclosure, and will not be repeated here.

[0156] Step D4: If it is determined that the new chip to be adjusted has a data readout error based on the first test data group and the new first readout data group, adjust the timing parameters of the test instrument until the data readout of the new chip to be adjusted is correct. Then, take the next chip to be adjusted as the new chip to be adjusted and return to the step of writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask (i.e., return to step D2) until it is determined that the data readout of multiple chips is correct. Record the adjusted timing parameters corresponding to each chip.

[0157] According to the embodiments of this disclosure, compared to a solution where uniform adjustment cannot ensure that each chip can be adjusted to the optimal value, the embodiments of this disclosure use a traversal approach to accurately adjust the output characteristics of each chip, thereby improving the consistency of chip output characteristics and further improving chip yield.

[0158] In one example, after recording the adjusted timing parameters for each chip, the characteristic parameters of the chip can be accurately adjusted using these adjusted timing parameters during high-speed testing. This example ensures precise testing and adjustment of each chip during high-speed testing, avoiding chip read / write anomalies caused by using complex data types, and improving chip yield.

[0159] In some embodiments, the chip output characteristic parameter adjustment method provided in this disclosure can be applied to the high-speed testing phase of chip finished product testing. Specifically, if the maximum data transmission rate is within the range of data transmission rates corresponding to high-speed transmission, the chip is considered to be under high-speed testing.

[0160] Optionally, if it is determined that data of complex data types still have an impact on the low-speed testing phase of the chip, the technical solutions of the embodiments of this disclosure can also be applied to the low-speed testing phase, without specific limitations.

[0161] The inventors discovered through research that complex data types can affect the read / write stability of chips during the high-speed testing phase of Fourier Transform (FT) testing, potentially leading to the misclassification of chips as failures during this phase. The embodiments disclosed herein avoid misclassifying normal chips as failures during the high-speed testing phase of FT testing, thereby effectively improving chip yield.

[0162] Figure 5 This illustration shows a flowchart of another method for adjusting chip output characteristic parameters provided by an embodiment of the present disclosure. This embodiment of the present disclosure is an optimization based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0163] like Figure 5 As shown, the method for adjusting the chip output characteristic parameters includes the following steps S510 to S560.

[0164] S510 writes the second test data group to the chip to be adjusted according to the data writing method corresponding to the data masking. The second test data group is generated according to the preset data masking rules, and at least part of the data in the second test data group is masked.

[0165] In some embodiments, the second data set to be tested is generated according to a preset data masking rule, which includes multiple data masking sub-rules. The second data set to be tested includes multiple types of data sets, wherein each type of data set is generated by one data masking sub-rule, and the number of data sets masked in different types of data sets is different. It should be noted that the second data set to be tested and the first data set to be tested can be the same or different, and there is no specific restriction on this.

[0166] It should be noted that the specific implementation of S510 can be found in the above description of S410 in the embodiments of this disclosure, and will not be repeated here.

[0167] S520 reads the second readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask.

[0168] It should be noted that the specific implementation of S520 can be found in the above description of S420 in the embodiments of this disclosure, and will not be repeated here.

[0169] S530, if it is determined that there is a data write error in the chip to be adjusted based on the second test data group and the second read data group, adjusts the write clock of the test instrument in order to adjust the output characteristic parameters of the chip to be adjusted by adjusting the write clock.

[0170] In some embodiments, S530 may include the following steps F2 to F5.

[0171] Step F2 involves adjusting the timing parameters of the write clock of the test instrument by the target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted.

[0172] In one example, step F2 may include: within a preset range of timing parameter variations, adding a target adjustment amount to the timing parameters before adjustment to obtain the adjusted timing parameters. For example, the preset parameter variation range may be [0.2ns, 1.2ns]. For example, the target adjustment amount may be 5ps (picoseconds). It should be noted that the preset parameter variation range and the target adjustment amount can also be set to other values ​​according to actual conditions and specific needs; there are no specific limitations on this.

[0173] Step F3 involves writing the second test data group to the chip whose characteristic parameters have been adjusted, according to the data writing method corresponding to the data masking. Step F3 can be found in the description of S410 above in the embodiments of this disclosure, and is not specifically limited thereto.

[0174] Step F4: According to the data readout method corresponding to the data masking, read out the new second readout data group from the chip to be adjusted after the characteristic parameters have been adjusted. Step F3 can be found in the above description of S420 in the embodiments of this disclosure, and is not specifically limited thereto.

[0175] In step F5, if the chip to be adjusted has data read / write errors after the characteristic parameters are adjusted based on the second test data group and the new second read data group, return to the step of adjusting the timing parameters of the write clock by the target adjustment amount (i.e., return to step F2, i.e., cyclically execute steps F2 to F5) until the data read / write of the chip to be adjusted is correct after the characteristic parameters are adjusted based on the second test data group and the new second data group.

[0176] Optionally, steps F2 to F5 above can be implemented using the data strobe traversal function of the test equipment. For example, under this traversal function, the data strobe of the equipment can be set to scan from 0.2ns to 1.2ns, with a step size of 5ps.

[0177] S540 writes the first test data group to the chip to be adjusted according to the data writing method corresponding to the data masking. At least part of the data in the first test data group is masked.

[0178] S540 is similar to S410; please refer to the details of S410 for further information, which will not be repeated here.

[0179] S550 reads the first readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask.

[0180] S550 is similar to S420; please refer to the details of S420 for further information, which will not be repeated here.

[0181] S560, if it is determined that there is a data readout error in the chip to be adjusted based on the first test data group and the first readout data group, the timing parameters of the data strobe signal of the test instrument are adjusted so as to adjust the clock deviation value of the chip to be adjusted by adjusting the timing parameters. The clock deviation value is used to characterize the deviation value between the data strobe signal and the clock signal.

[0182] S560 is similar to step C1, and the details of step C1 can be found therein, so it will not be repeated here.

[0183] The chip output characteristic parameter adjustment method provided in this disclosure, since the first test data group is a data group generated according to a preset data masking rule with at least some data masked, can simulate the read and write function of the chip to be adjusted for complex data types by reading and writing the first test data group through the data masking function. Accordingly, in this disclosure embodiment, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write complex data types, avoiding the occurrence of unstable read and write operations for complex data types. Therefore, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, thereby improving the chip yield.

[0184] Furthermore, by adjusting the write clock, the correctness of the data writing process can be ensured. With the written data being correct, the data reading process can be accurately adjusted by using the timing parameters of the data strobe signal, thereby ensuring precise adjustment of the entire read and write process. This, in turn, ensures accurate adjustment of the output characteristics of the chip to be adjusted, thus improving the chip yield.

[0185] In some embodiments, the test equipment is used to adjust multiple chips sequentially. Accordingly, the method for adjusting the chip output characteristic parameters after S530 and before S540 may further include steps G1 to G4.

[0186] Step G1: If the data read from the chip to be adjusted is correct after adjusting the write clock, the next chip among the multiple chips to be adjusted is selected as the new chip to be adjusted. For example, see [link to example]. Figure 2 Chips 21-2M can be used sequentially as the chips to be adjusted.

[0187] Step G2 involves writing the second test data group to the new chip to be adjusted according to the data writing method corresponding to the data masking. Step G2 can be found in the above description of S410 in the embodiments of this disclosure, and will not be repeated here.

[0188] Step G3 involves reading data from the new chip to be adjusted according to the data reading method corresponding to the data masking, to obtain a new second readout data group. Step G3 can be found in the above description of S420 in the embodiments of this disclosure, and will not be repeated here.

[0189] Step G4: If it is determined that the new chip to be adjusted has a data read error based on the second test data group and the new second read data group, adjust the timing parameters of the write clock until the data read of the new chip to be adjusted is correct. Then, take the next chip to be adjusted as the new chip to be adjusted and return to the step of writing the second test data group to the chip to be adjusted according to the data writing method corresponding to the data mask (i.e., return to step G2) until it is determined that the data read of multiple chips is correct. Record the adjusted timing parameters corresponding to each chip.

[0190] Figure 6 This illustration shows a flowchart of another method for adjusting chip output characteristic parameters according to an embodiment of the present disclosure. This embodiment is an optimization based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0191] like Figure 6 As shown, the chip to be adjusted includes a First-In-First-Out (FIFO) register, and the method for adjusting the chip output characteristic parameters includes the following steps S610 to S560.

[0192] S610, Write a preset data group to the FIFO register. In some embodiments, the preset data group may be a test data group specified in a preset standard protocol. The preset standard protocol may be a protocol that specifies the format of the refresh command. For example, it may be a Joint Electron Device Engineering Council (JEDEC) standard protocol. It should be noted that other standard protocols may also be used, without specific limitations. For example, the preset data group may include at least one of the following five data groups: "01010101", "10101010", "10011001", "01100110", and "11110000". For example, it may be one of the five data groups mentioned above.

[0193] S620 reads the third readout data group from the FIFO register.

[0194] It should be noted that the specific implementation of S620 can be found in the above description of S420 in the embodiments of this disclosure, and will not be repeated here.

[0195] S630 adjusts timing parameters if it is determined that the chip to be adjusted has a data readout error based on the preset data group and the third readout data group.

[0196] In some embodiments, S530 may include the following steps H2 to H5.

[0197] Step H2 involves adjusting the timing parameters of the test equipment by the target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted. For example, the timing parameters of the test equipment can be the timing parameters of the data strobe signal.

[0198] In one example, step H2 may include: within a preset range of timing parameter variations, adding a target adjustment amount to the original timing parameters to obtain the adjusted timing parameters. For example, the preset parameter variation range may be [1.0 ns, 3.5 ns]. For example, the target adjustment amount may be 5 ps (picoseconds). It should be noted that the preset parameter variation range and the target adjustment amount can also be set to other values ​​according to actual conditions and specific needs; no specific restrictions are imposed on this.

[0199] Step H3 involves writing a preset data group to the chip whose characteristic parameters have been adjusted, according to the data writing method corresponding to the data masking. Step H3 can be found in the above description of S410 in the embodiments of this disclosure, and is not specifically limited thereto.

[0200] Step H4 involves reading a new third readout data group from the chip to be adjusted after the characteristic parameters have been adjusted, according to the data readout method corresponding to the data masking. Step H4 can be found in the above description of S420 in the embodiments of this disclosure, and is not specifically limited thereto.

[0201] In step H5, if the chip to be adjusted has data read / write errors after the characteristic parameters are adjusted according to the preset data group and the new third read data group, return to the step of adjusting the timing parameters of the write clock by the target adjustment amount (i.e., return to step H2, i.e., cyclically execute step H2 to step H5) until the data read / write of the chip to be adjusted is correct after the characteristic parameters are adjusted according to the preset data group and the new third data group.

[0202] Optionally, steps H2 to H5 above can be implemented using the data strobe traversal function of the test equipment. For example, under this traversal function, the data strobe of the equipment can be set to scan from 1.0ns to 3.5ns, with a step size of 5ps.

[0203] S640, according to the data writing method corresponding to the data masking, writes the first test data group to the chip to be adjusted, wherein at least part of the data in the first test data group is masked.

[0204] S640 is similar to S410; please refer to the details of S410 for further information, which will not be repeated here.

[0205] S650 reads the first readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask.

[0206] S650 is similar to S420; please refer to the details of S420 for further information, which will not be repeated here.

[0207] S660, if it is determined that there is a data read / write error in the chip to be adjusted based on the first test data group and the first read data group, the timing parameters of the test instrument are adjusted so as to adjust the output characteristic parameters of the chip to be adjusted.

[0208] S660 is similar to S430; please refer to the details of S430 for further information, which will not be repeated here.

[0209] The chip output characteristic parameter adjustment method provided in this disclosure, since the first test data group is a data group generated according to a preset data masking rule with at least some data masked, can simulate the read and write function of the chip to be adjusted for complex data types by reading and writing the first test data group through the data masking function. Accordingly, in this disclosure embodiment, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write complex data types, avoiding the occurrence of unstable read and write operations for complex data types. Therefore, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, thereby improving the chip yield.

[0210] The inventors discovered through research that the presence of bad blocks (faulty memory areas) and bad pixels (faulty memory cells) in the chip's memory array can prevent the chip from reading and writing normally (for example, the presence of bad blocks and bad pixels may result in writing a 1 and misreading a 0). Directly accessing the chip's memory cells makes it impossible to distinguish whether the read / write failure is due to a chip malfunction or misalignment of timing parameters such as the data strobe. Through the embodiments of this disclosure, timing parameters such as the data strobe can be coarsely adjusted by performing read / write tests on the FIFO register, thus eliminating the influence of bad blocks and bad pixels on the test results and ensuring the reliability and accuracy of the adjustment.

[0211] In some embodiments, the test equipment is used to adjust multiple chips sequentially. Accordingly, the method for adjusting the chip output characteristic parameters after S630 and before S640 may further include steps J1 to J4.

[0212] Step J1: After adjusting the timing parameters to ensure correct data reading from the chip to be adjusted, the next chip among the multiple chips to be adjusted is selected as the new chip to be adjusted. For example, see [link to example]. Figure 2 Chips 21-2M can be used sequentially as the chips to be adjusted.

[0213] Step J2 involves writing a preset data group to the new chip to be adjusted. Step J2 can be found in the above description of S410 in the embodiments of this disclosure, and will not be repeated here.

[0214] Step J3: Read the data from the new chip to be adjusted according to the data reading method corresponding to the data masking to obtain a new third read data group.

[0215] Step J4: If it is determined that the new chip to be adjusted has a data read error based on the preset data group and the new third read data group, adjust the timing parameters of the write clock until the data read of the new chip to be adjusted is correct. Then, take the next chip to be adjusted as the new chip to be adjusted and return to the step of writing the preset data group to the chip to be adjusted according to the data writing method corresponding to the data mask (i.e., return to step J2) until it is determined that the data read of multiple chips is correct. Record the adjusted timing parameters corresponding to each chip.

[0216] To facilitate a comprehensive understanding of the technical solutions provided by the embodiments of this disclosure, an example will be used to illustrate the technical solutions of the embodiments of this disclosure.

[0217] Figure 7 A schematic flowchart illustrating an exemplary method for adjusting chip output characteristic parameters provided in an embodiment of this disclosure is shown. Figure 7 As shown, the method for adjusting the chip output characteristic parameters may include the following steps S701 to S715.

[0218] S701, the test equipment's data strobe is set to scan from 1.0ns to 3.5ns, with a step size of 5ps. For example, in the first loop, the data strobe can be set to 1.0ns, in the second loop it can be set to 1.0ns plus 5ps, ..., until the last loop when the data strobe is set to 3.5ns.

[0219] Optionally, before S701, it may also include: reading the DUT (i.e., chip) that is still currently enabled.

[0220] S702, through the MPC command, writes five sets of data 01010101, 10101010, 10011001, 01100110, 11110000 to the FIFO register of the chip corresponding to the current DUT (i.e., the chip to be adjusted).

[0221] S703 reads five sets of data from the FIFO register of the chip corresponding to the current DUT via the MPC command: 01010101, 10101010, 10011001, 01100110, 11110000.

[0222] S704: Determine if the current DUT (Device Under Test) can accurately read data. If the result is no, return to step S702. If the result is yes, continue to S705. The next loop begins upon returning to S702.

[0223] S705: Determine if all chips corresponding to the DUTs can accurately read the data. If the determination result is negative, then the next DUT of the current DUT is taken as the new current DUT, and the process returns to step S702. If the determination result is positive, then proceed to step S706. It should be noted that when returning to S702, the data strobe can be restored to its initial value, i.e., 1.0ns.

[0224] S706 sets the test instrument's write clock to scan from 0.2ns to 1.2ns, with a step size of 5ps. Optionally, before S706, it may also include reading the currently active DUT (i.e., chip).

[0225] S707 uses the mask write command to write the first data set to be tested into the memory cell of the chip corresponding to the current DUT.

[0226] S708 reads the first data group from the memory cell of the chip corresponding to the current DUT using the mask read command.

[0227] S709: Determine if the current DUT (Device Under Test) can accurately read data. If the result is no, return to step S707. If the result is yes, continue executing S710. Upon returning to S707, the next loop begins.

[0228] In step S710, it is determined whether the chips corresponding to all DUTs can accurately read the data. If the determination result is negative, the next DUT of the current DUT is taken as the new current DUT, and the process returns to step S707. If the determination result is positive, the process continues to step S711. It should be noted that when returning to S707, the data strobe can be restored to its initial value, which is 0.2ns.

[0229] S711 sets the machine's data strobe to scan from 1.0ns to 3.5ns, with a step size of 5ps. Optionally, before S711, it may also include reading the currently active DUT (i.e., chip).

[0230] S712 uses the mask write command to write the second data set to be tested into the memory cell of the chip corresponding to the current DUT.

[0231] S713 reads the second read data group from the memory cell of the chip corresponding to the current DUT through the mask read command.

[0232] S714: Determine if the current DUT (Device Under Test) can accurately read data. If the result is no, return to step S712. If the result is yes, continue to S715. The next loop begins upon returning to S712.

[0233] S715: Determine if all chips corresponding to the DUTs can accurately read the data. If the determination result is negative, then the next DUT of the current DUT is taken as the new current DUT, and the process returns to step S712. If the determination result is positive, then the optimal data strobe compensation amount for each DUT is recorded. It should be noted that when returning to S712, the data strobe can be restored to its initial value, i.e., 0.2ns.

[0234] Through steps S701 to S715 of this embodiment, the data strobe can be roughly adjusted by performing FIFO read / write tests to ensure that data (test data) can be read and written normally. Furthermore, by finely adjusting the write clock, data can be correctly written at high speeds. And, while ensuring correct writing, the data strobe can be finely adjusted to ensure that data can be correctly read at high speeds. This example demonstrates how the output characteristics of the chip under adjustment can be accurately adjusted based on whether there are read / write anomalies for complex data types, thereby improving chip yield.

[0235] To demonstrate the feasibility of the embodiments of this disclosure, the inventors conducted experiments on the output characteristics of the chip. Exemplarily, Figure 8 This illustration shows an exemplary shmoo test pattern before timing parameter adjustment, as provided in an embodiment of this disclosure. Figure 9 This illustration shows an exemplary SHMOO test graph with adjusted timing parameters provided in an embodiment of this disclosure. The horizontal axis represents the time deviation value t. DQSCK The vertical axis represents the read comparison voltage. Black squares indicate read / write failures, and light-colored squares indicate read / write successes. The vertical lines in the graph represent the data strobe of the test equipment.

[0236] exist Figure 8 In the image, the light-colored square area is located to the left of the vertical line, indicating poor chip consistency. This can be improved by adjusting the data strobe on the test equipment. Figure 9 In the middle, the vertical line is located in the center of the light-colored square area, which greatly improves chip consistency.

[0237] Based on the same inventive concept, this disclosure also provides a device for adjusting chip output characteristic parameters, as described in the following embodiments.

[0238] Figure 10 This diagram illustrates a device for adjusting chip output characteristic parameters according to an embodiment of the present disclosure. Figure 10 As shown, the chip output characteristic parameter adjustment device 1000 includes a data writing module 1010, a data reading module 1020, and a parameter adjustment module 1030.

[0239] The data writing module 1010 is used to write a first test data group to the chip to be adjusted according to the data writing method corresponding to the data masking. The first test data group is generated according to a preset data masking rule, and at least some of the data in the first test data group is masked.

[0240] The data readout module 1020 is used to read the first readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask.

[0241] The parameter adjustment module 1030 is used to adjust the timing parameters of the test instrument when it is determined that there is a data read / write error in the chip to be adjusted based on the first test data group and the first read data group, so as to adjust the output characteristic parameters of the chip to be adjusted by adjusting the timing parameters.

[0242] The chip output characteristic parameter adjustment device provided in this embodiment of the present disclosure, since the first test data group is a data group generated according to a preset data masking rule, with at least some data masked, can simulate the read and write function of the chip to be adjusted for complex data types by reading and writing the first test data group through the data masking function. Accordingly, in this embodiment of the present disclosure, when it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the output characteristic parameters of the chip to be adjusted are adjusted by adjusting the timing parameters of the test equipment. This enables the chip to be adjusted after parameter adjustment to correctly read and write complex data types, avoiding the occurrence of unstable read and write operations of complex data types by the chip to be adjusted. Thus, the output characteristics of the chip to be adjusted can be accurately adjusted based on whether the chip to be adjusted has abnormal read and write operations for complex data types, thereby improving the chip yield.

[0243] In one embodiment, the timing parameters include: timing parameters of the data strobe signal, and the parameter adjustment module 1030 is specifically configured as follows:

[0244] If a data readout error is determined in the chip to be adjusted based on the first test data group and the first readout data group, the timing parameters of the data strobe signal of the test instrument are adjusted so as to adjust the clock deviation value of the chip to be adjusted. The clock deviation value is used to characterize the deviation value between the data strobe signal and the clock signal.

[0245] In one embodiment, the data writing module 1010 is further configured to write a second test data group to the chip to be adjusted according to the data writing method corresponding to the data masking, wherein the second test data group is generated according to a preset data masking rule, and at least some of the data in the second test data group is masked.

[0246] The data readout module 1020 is also used to read out the second readout data group from the chip to be adjusted according to the data readout method corresponding to the data mask;

[0247] The parameter adjustment module 1030 is also used to adjust the write clock of the test instrument when it is determined that there is a data write error in the chip to be adjusted based on the second test data group and the second read data group, so as to adjust the output characteristic parameters of the chip to be adjusted by adjusting the write clock.

[0248] In one embodiment, the chip to be adjusted includes a first-in-first-out (FIFO) register.

[0249] The data writing module 1010 is also used to write a preset data group to the FIFO register;

[0250] The data readout module 1020 is also used to read the third readout data group from the FIFO register;

[0251] The parameter adjustment module 1030 is also used to adjust timing parameters when it is determined that there is a data readout error in the chip to be adjusted based on the preset data group and the third readout data group.

[0252] In one embodiment, the first data group to be tested is generated according to a preset data masking rule. The preset data masking rule includes multiple data masking sub-rules. The first data group to be tested includes multiple types of data groups. Each type of data group is generated by a data masking sub-rule. The number of data groups masked in different types of data groups is different.

[0253] In one embodiment, the multiple data groups include at least one of the following:

[0254] The first type of data group is generated according to the first data masking sub-rule. The first type of data group includes multiple first data groups. The masked data of any two first data groups are different. The first data masking sub-rule is used to mask one data in each first data group.

[0255] The second type of data group is generated according to the second data masking sub-rule. The second type of data group includes multiple second data groups. At least one of the masked data in any two second data groups is different. The second data masking sub-rule is used to mask four data in each second data group.

[0256] The third data group is generated according to the third data masking sub-rule. The third data group includes multiple third data groups. At least one of the masked data in any two third data groups is different. The third data masking sub-rule is used to mask eight data in each third data group.

[0257] In one embodiment, the parameter adjustment module 1030 is specifically configured as follows:

[0258] The timing parameters of the test equipment are adjusted by the target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted.

[0259] According to the data writing method corresponding to the data masking, write the first test data group to the chip whose characteristic parameters have been adjusted;

[0260] According to the data readout method corresponding to the data masking, a new first readout data group is read out from the chip to be adjusted after the characteristic parameters have been adjusted.

[0261] If, after determining the characteristic parameters of the chip to be adjusted based on the first set of test data and the new first set of readout data, there is a data read / write error, return to the step of adjusting the timing parameters of the test instrument by the target adjustment amount until the data read / write of the chip to be adjusted is correct after determining the characteristic parameters of the chip to be adjusted based on the first set of test data and the new first set of readout data.

[0262] In one embodiment, the parameter adjustment module 1030 is specifically configured to: within a preset range of timing parameter changes, add a target adjustment amount to the timing parameters before adjustment to obtain the adjusted timing parameters.

[0263] In one embodiment, the test equipment is used to adjust multiple chips sequentially. The test equipment is also used to select the next chip among the multiple chips as the new chip to be adjusted, provided that the data of the chip to be adjusted is read correctly by adjusting the timing parameters.

[0264] The data writing module 1010 is also used to write the first test data group to the new chip to be adjusted according to the data writing method corresponding to the data mask;

[0265] The data readout module 1020 is also used to read data from the new chip to be adjusted according to the data readout method corresponding to the data mask, so as to obtain a new first readout data group;

[0266] The parameter adjustment module 1030 is also used to adjust the timing parameters of the test instrument when it is determined that the new chip to be adjusted has a data read error based on the first test data group and the new first read data group, until the data read of the new chip to be adjusted is correct. Then, the next chip to be adjusted is taken as the new chip to be adjusted, and the process of writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask is returned until it is determined that the data read of multiple chips is correct, and the adjusted timing parameters corresponding to each chip are recorded.

[0267] In one embodiment, each first test data group includes N data points, and the chip to be adjusted includes N data shielding pins and N data transmission pins.

[0268] The data writing module 1010 is specifically configured to perform the following steps for the i-th data in the first data group to be tested, where i is any positive integer less than or equal to N: transmit the i-th data to the i-th data transmission pin of the chip to be adjusted; send a level signal corresponding to the masking state of the i-th data to the i-th data masking pin of the chip to be adjusted, so that after the chip to be adjusted receives the i-th data through the i-th data transmission pin, it can determine whether to mask and write the i-th data according to the level signal of the i-th data masking pin, wherein when the i-th data is in the masking state, the level signal is the first level signal; when the i-th data is high and in the unmasked state, the level signal is the second level signal.

[0269] In one embodiment, the data writing module 1010 is specifically configured to write the first test data group to the chip to be adjusted in a data writing mode corresponding to data masking by masking the write command.

[0270] In one embodiment, the data readout module 1020 is specifically configured to read out the first readout data group from the chip to be adjusted by masking the readout command and using the data readout method corresponding to the data masking.

[0271] In one embodiment, the device is used in the high-speed testing phase of finished chip testing.

[0272] It should be noted that, Figure 10 The chip output characteristic parameter adjustment device 1000 shown can perform... Figures 3 to 4 The various steps in the method embodiment shown are implemented. Figures 4 to 7 The processes and effects in the method embodiments shown are not described in detail here.

[0273] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0274] The following reference Figure 11 To describe an electronic device 1100 according to such an embodiment of the present disclosure. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0275] like Figure 11As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, and a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110).

[0276] The storage unit stores program code that can be executed by the processing unit 1110, causing the processing unit 1110 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0277] Storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 11201 and / or cache memory 11202, and may further include a read-only memory (ROM) 11203.

[0278] Storage unit 1120 may also include a program / utility 11204 having a set (at least one) of program modules 11205, such program modules 11205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0279] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0280] Electronic device 1100 can also communicate with one or more external devices 1140 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1100, and / or with any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). Such communication can be performed through input / output (I / O) interface 1150.

[0281] Furthermore, the electronic device 1100 can also communicate with one or more networks (such as local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via the network adapter 1160.

[0282] like Figure 11 As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130.

[0283] It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0284] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method according to the embodiments of this disclosure.

[0285] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Figure 12 A schematic diagram of a computer-readable storage medium provided in an embodiment of this disclosure is shown, such as... Figure 12 As shown, the computer-readable storage medium 1200 stores a program product capable of implementing the methods described above.

[0286] In some possible implementations, various aspects of this disclosure may also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the “Exemplary Methods” section of this specification according to various exemplary embodiments of this disclosure.

[0287] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0288] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein readable program code is carried. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0289] A readable signal medium can also be any readable medium other than a readable storage medium, which can send, propagate or transmit a program for use by or in connection with an instruction execution system, apparatus or device.

[0290] In some examples, program code contained on a computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0291] In practical implementation, program code for performing the operations of this disclosure can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0292] In cases involving remote computing devices, the remote computing devices can be connected to user computing devices via any type of network, including local area networks (LANs) or wide area networks (WANs), or they can be connected to external computing devices (e.g., via the Internet using an Internet service provider).

[0293] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a chip output characteristic parameter adjustment method provided in various optional embodiments of this disclosure.

[0294] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0295] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0296] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware.

[0297] Therefore, the technical solution according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the method according to the embodiments of this disclosure.

[0298] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein.

[0299] This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for adjusting chip output characteristic parameters, characterized in that, The method includes: According to the data writing method corresponding to the data masking, the first test data group is written to the chip to be adjusted, wherein at least part of the data in the first test data group is masked. According to the data reading method corresponding to the data masking, the first readout data group is read from the chip to be adjusted; If it is determined that the chip to be adjusted has a data read / write error based on the first test data group and the first read data group, the timing parameters of the test equipment are adjusted so as to adjust the output characteristic parameters of the chip to be adjusted through the adjustment of the timing parameters. The chip to be adjusted includes a first-in-first-out (FIFO) register. Furthermore, before writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask, the method further includes: Write a preset data group to the FIFO register; Read the third data group from the FIFO register; If it is determined that the chip to be adjusted has a data readout error based on the preset data group and the third readout data group, the timing parameters are adjusted.

2. The method according to claim 1, characterized in that, The timing parameters include: timing parameters of the data strobe signal, When it is determined, based on the first test data group and the first readout data group, that the chip to be adjusted has a data read / write error, the timing parameters of the test equipment are adjusted, including: If it is determined that the chip to be adjusted has a data readout error based on the first test data group and the first readout data group, the timing parameters of the data strobe signal of the test instrument are adjusted so as to adjust the clock deviation value of the chip to be adjusted by adjusting the timing parameters of the data strobe signal. The clock deviation value is used to characterize the deviation value between the data strobe signal and the clock signal.

3. The method according to claim 2, characterized in that, Before writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask, the method further includes: According to the data writing method corresponding to the data masking, a second test data group is written to the chip to be adjusted, wherein the second test data group is generated according to a preset data masking rule, and at least some of the data in the second test data group is masked. According to the data reading method corresponding to the data masking, the second readout data group is read from the chip to be adjusted; If a data write error is determined to exist in the chip to be adjusted based on the second test data group and the second read data group, the write clock of the test instrument is adjusted so as to adjust the output characteristic parameters of the chip to be adjusted through the adjustment of the write clock.

4. The method according to claim 1, characterized in that, The first set of data to be tested was generated according to a preset data masking rule, which includes multiple data masking sub-rules. The first data group to be tested includes multiple data groups, each of which is generated by a data masking sub-rule, and the number of data to be masked varies in different data groups.

5. The method according to claim 4, characterized in that, The multiple data groups include at least one of the following: The first type of data group is generated according to the first data masking sub-rule, wherein the first type of data group includes multiple first data groups, and the masked data of any two first data groups is different. The first data masking sub-rule is used to mask one data in each first data group. The second type of data group is generated according to the second data masking sub-rule, wherein the second type of data group includes multiple second data groups, and at least one of the masked data in any two second data groups is different. The second data masking sub-rule is used to mask four data in each second data group. The third data group is generated according to the third data masking sub-rule, wherein the third data group includes multiple third data groups, and at least one of the masked data in any two third data groups is different. The third data masking sub-rule is used to mask eight data in each third data group.

6. The method according to claim 1, characterized in that, The adjustment of the timing parameters of the testing equipment includes: The timing parameters of the test equipment are adjusted by a target adjustment amount to obtain the adjusted timing parameters, which are then used to adjust the output characteristic parameters of the chip to be adjusted. According to the data writing method corresponding to the data masking, the first test data group is written to the chip to be adjusted after the characteristic parameters are adjusted. According to the data readout method corresponding to the data masking, a new first readout data group is read out from the chip to be adjusted after the characteristic parameters are adjusted. If, based on the first test data set and the new first readout data set, it is determined that the chip to be adjusted after the characteristic parameters have been adjusted has a data read / write error, the process returns to the step of adjusting the timing parameters of the test instrument by the target adjustment amount, until it is determined based on the first test data set and the new first readout data set that the data read / write of the chip to be adjusted after the characteristic parameters have been adjusted is correct.

7. The method according to claim 6, characterized in that, The adjustment of the timing parameters of the test equipment by the target adjustment amount, to obtain the adjusted timing parameters, includes: Within the preset range of timing parameter variations, the target adjustment amount is added to the timing parameters before adjustment to obtain the adjusted timing parameters.

8. The method according to claim 1, characterized in that, The testing machine is used to adjust multiple chips sequentially. After adjusting the timing parameters of the testing machine, the method further includes: If the data read from the chip to be adjusted is correct by adjusting the timing parameters, the next chip in the plurality of chips to be adjusted is taken as the new chip to be adjusted. According to the data writing method corresponding to the data masking, the first test data group is written to the new chip to be adjusted. The new chip to be adjusted is read out according to the data reading method corresponding to the data masking to obtain a new first readout data group; If, based on the first test data group and the new first readout data group, it is determined that the new chip to be adjusted has a data readout error, the timing parameters of the test equipment are adjusted until the data readout of the new chip to be adjusted is correct. The next chip to be adjusted is then taken as the new chip to be adjusted, and the process of writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask is returned until it is determined that the data readout of all chips is correct. The adjusted timing parameters corresponding to each chip are recorded.

9. The method according to claim 1, characterized in that, Each group of first test data includes N data points, and the chip to be adjusted includes N data shielding pins and N data transmission pins, where N is any integer. The step of writing the first test data group to the chip to be adjusted according to the data writing method corresponding to the data mask includes: For the i-th data in the first test data group, perform the following steps, where i is any positive integer less than or equal to N: The i-th data is transmitted to the i-th data transmission pin of the chip to be adjusted; A level signal corresponding to the masking state of the i-th data is sent to the i-th data masking pin of the chip to be adjusted, so that after the chip to be adjusted receives the i-th data through the i-th data transmission pin, it can determine whether to mask and write the i-th data according to the level signal of the i-th data masking pin. Specifically, when the i-th data is in a masked state, the level signal is a first level signal; when the i-th data is high and in an unmasked state, the level signal is a second level signal.

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