A layout drawing method, device, electronic device, and storage medium

Abstract

The present invention discloses a layout drawing method, apparatus, electronic device, and storage medium. The layout drawing method includes: receiving a selection and movement instruction, selecting a corresponding bare chip according to the selection and movement instruction and moving the bare chip onto a PCB board, where the bare chip includes a chip body, at least one first pad, and a second pad having the same number as the first pad, and the first pad is located on a first surface of the chip body; receiving a pad layer establishment instruction, taking the film layer where the first pad is located as the pad layer according to the pad layer establishment instruction, and defining the pad layer as an external structure outside the bare chip; receiving an electrical connection instruction, and electrically connecting the first pad in the pad layer to a pin in the PCB board according to the electrical connection instruction. The present invention can directly place a bare chip onto a PCB board in a drawing software, facilitating a user to draw a layout with a bare chip, and greatly improving the efficiency of the user in drawing the layout.

Description

Technical Field

[0001] The present invention relates to the technical field of layout drawing, and in particular, to a layout drawing method, device, electronic device, and storage medium. Background Art

[0002] EDA (Electronic Design Automation) is a kind of generalized CAD and is a subdivision of industry software. The design of EDA software condenses a large amount of knowledge in disciplines such as mathematics, graph theory, physics, materials, and processes to achieve the automatic design of electronic products. Using EDA tools, electronic designers can start designing electronic systems from concepts, algorithms, protocols, etc., and complete the entire process of electronic products from circuit design, performance analysis to designing IC layouts or PCB layouts. After decades of development, EDA tools are also very rich and can be divided into circuit design and simulation tools, PCB design software, IC design software, PLD design tools, etc. according to functions and usage scenarios.

[0003] The current mainstream EDA software mainly supports placing packaged electronic components on a PCB board to complete the design of the PCB board. With the development of the times, in the process of designing a PCB board, it is not only limited to using packaged electronic components, but sometimes it is also necessary to directly draw a bare chip on the PCB board to complete the design of the PCB schematic diagram.

[0004] DRC (Design Rule Check) is a rule check for layout design, and its main purpose is to check all physical verification processes in the layout that may cause potential open circuits, short circuits, or adverse effects due to violating design rules. When using existing EDA software to draw a layout, if a bare chip is directly placed on the PCB board, DRC check errors will occur, and thus it is impossible to continue drawing the layout. Summary of the Invention

[0005] The present invention provides a layout drawing method, device, electronic device, and storage medium, which can directly place a bare chip on a PCB board in a drawing software, facilitating users to draw a layout with a bare chip and greatly improving the efficiency of users in drawing the layout.

[0006] According to one aspect of the present invention, there is provided a layout drawing method, and the layout drawing method includes:

[0007] Receive a selection and movement instruction, select a corresponding bare chip according to the selection and movement instruction, and move the bare chip onto a PCB board. Wherein, the bare chip includes a chip body, at least one first pad, and a second pad equal in number to the first pad. The first pad is located on a first surface of the chip body, the second pad is located on a second surface of the chip body, the first surface and the second surface are oppositely arranged, each first pad has a corresponding second pad, and the first pad is electrically connected to its corresponding second pad; when the bare chip is moved onto the PCB board, the second pad contacts the PCB board.

[0008] Receive a pad layer establishment instruction, and use the film layer where the first pad is located as the pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip.

[0009] Receive an electrical connection instruction, and electrically connect the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction.

[0010] Optionally, before receiving the selection and movement instruction, it further includes:

[0011] Receive a bare chip library establishment instruction, and establish a bare chip library according to the bare chip library establishment instruction. Wherein, the bare chip library includes various types of bare chips.

[0012] The step of selecting a corresponding bare chip according to the selection and movement instruction and moving the bare chip onto the PCB board includes:

[0013] Select a corresponding bare chip from the bare chip library according to the selection and movement instruction and move the bare chip onto the PCB board.

[0014] Optionally, the step of receiving the electrical connection instruction and electrically connecting the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction includes:

[0015] Receive the electrical connection instruction, select a bonding wire according to the electrical connection instruction, electrically connect the first end of the bonding wire to the first pad in the pad layer, and electrically connect the second end of the bonding wire to the pin in the PCB board.

[0016] Optionally, the bare chip includes at least two first pads.

[0017] The step of electrically connecting the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction includes:

[0018] Electrically connect each first pad in the pad layer to its corresponding pin in the PCB board according to the electrical connection instruction.

[0019] Optionally, the chip body includes vias and a conductive layer corresponding to each of the first pads; the side walls of each via are covered with the conductive layer;

[0020] The first pad is electrically connected to the second pad through the conductive layer on the side wall of the via.

[0021] According to another aspect of the present invention, a layout drawing device is provided. The layout drawing device includes: a selection and movement module, a pad layer establishment module, and an electrical connection module;

[0022] The selection and movement module is configured to receive a selection and movement instruction, and select a corresponding bare chip according to the selection and movement instruction and move the bare chip onto a PCB board. Wherein, a first surface of the bare chip includes first pads, a second surface of the bare chip includes second pads, the first surface and the second surface are oppositely arranged, and the first pads and the second pads are electrically connected; the second surface is in contact with the PCB board;

[0023] The pad layer establishment module is configured to receive a pad layer establishment instruction, and use the film layer where the first pads are located as a pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip;

[0024] The electrical connection module is configured to receive an electrical connection instruction, and electrically connect the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction.

[0025] Optionally, the layout drawing device provided in this embodiment further includes a bare chip library module;

[0026] The bare chip library module is configured to receive a bare chip library establishment instruction, and establish a bare chip library according to the bare chip library establishment instruction, where the bare chip library includes various types of bare chips;

[0027] The selection and movement module is specifically configured to select a corresponding bare chip from the bare chip library according to the selection and movement instruction and move the bare chip onto the PCB board.

[0028] Optionally, the electrical connection module is specifically configured to receive the electrical connection instruction, select bonding wires according to the electrical connection instruction, electrically connect a first end of the bonding wires to the first pads in the pad layer, and electrically connect a second end of the bonding wires to the pins in the PCB board.

[0029] According to another aspect of the present invention, an electronic device is provided. The electronic device includes:

[0030] At least one processor; and

[0031] A memory communicatively connected to the at least one processor; wherein,

[0032] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the layout drawing method according to any embodiment of the present invention.

[0033] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the layout drawing method according to any embodiment of the present invention when executed.

[0034] This embodiment provides a layout drawing method, which includes: receiving a selection and movement instruction, selecting a corresponding bare chip according to the selection and movement instruction, and moving the bare chip onto a PCB board, and then receiving a pad layer establishment instruction, and using the film layer where the first pads in the bare chip are located as the pad layer according to the pad layer establishment instruction. After the pad layer is established, an electronic device configured with drawing software will define the pad layer as an external structure outside the bare chip, that is, consider the pad layer and the bare chip excluding the first pads as two electrically connected devices. In this way, when the bare chip is located on the PCB board, DRC in the drawing software will not report an error, and the bare chip can be placed on the PCB board. Finally, after the pad layer is established, each first pad in the pad layer is electrically connected to the pins in the PCB board, so as to realize the electrical connection between the bare chip and the PCB board in the drawing software. This embodiment provides a layout drawing method, which can directly place a bare chip on a PCB board in a drawing software, facilitating the user to draw a layout with a bare chip and greatly improving the efficiency of the user in drawing a layout.

[0035] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0037] Figure 1 It is a flowchart of a layout drawing method according to an embodiment of the present invention;

[0038] Figure 2It is a schematic cross-sectional structure diagram of a bare chip provided according to an embodiment of the present invention;

[0039] Figure 3 It is a schematic structure diagram of a bare chip located on a PCB board provided according to an embodiment of the present invention;

[0040] Figure 4 It is a schematic flowchart of another layout drawing method provided according to an embodiment of the present invention;

[0041] Figure 5 It is a schematic structure diagram of a layout drawing device provided according to an embodiment of the present invention;

[0042] Figure 6 It is a schematic structure diagram of an electronic device provided according to an embodiment of the present invention. Detailed implementation manners

[0043] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 1 It is a schematic flowchart of a layout drawing method provided according to an embodiment of the present invention. Referring to Figure 1 , the layout drawing method provided in this embodiment includes the following steps:

[0046] S110. Receive a selection and movement instruction, select a corresponding bare chip according to the selection and movement instruction, and move the bare chip onto the PCB board. The bare chip includes a chip body, at least one first pad, and a second pad equal in number to the first pads. The first pads are located on a first surface of the chip body, the second pads are located on a second surface of the chip body, the first surface and the second surface are oppositely arranged, each first pad has its corresponding second pad, and the first pad is electrically connected to its corresponding second pad. When the bare chip is moved onto the PCB board, the second pads are in contact with the PCB board.

[0047] Specifically, the bare chip in this embodiment refers to a bare semiconductor component, that is, an unencapsulated semiconductor component. The selection and movement instruction includes the type of the bare chip required for the user to draw the layout and the position where the bare chip is moved onto the PCB board. The selection and movement instruction can be issued by the user. Exemplarily, the user can select the required type of bare chip from the bare chip library in the drawing software, and then drag the selected bare chip to the set position in the PCB board, which means that the user has sent the selection and movement instruction, and the electronic device configured with the drawing software (which can be EDA software) has received the selection and movement instruction.

[0048] Figure 2 is a schematic cross-sectional structure diagram of a bare chip provided according to an embodiment of the present invention. Refer to Figure 2 , the first pad 110 is short-circuited and electrically connected to its corresponding second pad 120. The chip body 130 in the bare chip 100 includes a through hole 131 and a conductive layer 132 corresponding to each first pad 110; the side wall of each through hole 131 is covered with the conductive layer 132; the first pad 110 and the second pad 120 are electrically connected through the conductive layer 132 on the side wall of the through hole 131.

[0049] Figure 3 is a schematic structural diagram of a bare chip located on a PCB board provided according to an embodiment of the present invention. Refer to Figure 3 , after receiving the selection and movement instruction, the bare chip 100 is placed at the corresponding position on the PCB board 200.

[0050] S120. Receive a pad layer establishment instruction, use the film layer where the first pads are located as the pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip.

[0051] Specifically, after receiving the pad layer establishment instruction, an electronic device configured with drafting software defines the film layer where the first pads are located as the pad layer. The pad layer includes all the first pads in the bare chip. After the pad layer is established, the electronic device configured with drafting software defaults that the first pads are detached from the bare chip and located in the pad layer, and defaults that the pad layer and the bare chip from which the first pads are detached are two structures. At this time, the DRC in the drafting software will not recognize a short circuit problem, that is, the DRC will not recognize the first pad and the second pad as a short circuit problem in a device, but only consider that the first pad in the pad layer is electrically connected to the second pad in the bare chip that does not include the first pad. Therefore, the DRC will not report an error, and the user can continue to draw the layout including the bare chip.

[0052] It should be noted that the pad layer is a virtual structure, and the bare chip that does not include the first pads is also a virtual structure. The pad layer establishment instruction can be sent by the user. Exemplarily, after the bare chip is placed on the PCB board, when the user selects all the first pads in the bare chip, it means that the user sends a pad layer establishment instruction to the electronic device configured with drafting software.

[0053] S130. Receive the electrical connection instruction, and electrically connect the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction.

[0054] Specifically, continuing to refer to Figure 3 , the first pads 110 can be electrically connected to the corresponding pins 210 in the PCB board 200 through bonding wires 300, so as to realize drawing the bare chip 100 on the PCB board.

[0055] It should be noted that the selection and movement instruction, the pad layer establishment instruction, and the electrical connection instruction in this embodiment can all be issued by the user. Each time the user issues an instruction, the electronic device configured with drafting software executes one step. In addition, the drafting software can be configured with a user-defined development function. The user can gather the basic steps of the layout drawing method provided in the embodiments of the present invention in the drafting software through a custom method and set a start drawing button for receiving. When the user clicks the start drawing button after establishing the required PCB board in the drafting software, the electronic device can automatically obtain each instruction in the layout drawing method in sequence and perform corresponding operations according to the instruction requirements.

[0056] This embodiment provides a layout drawing method, which includes: receiving a selection and movement instruction, selecting a corresponding bare chip according to the selection and movement instruction, and moving the bare chip to the PCB board. Then, receiving a pad layer establishment instruction, and taking the film layer where the first pad in the bare chip is located as the pad layer according to the pad layer establishment instruction. After the pad layer is established, an electronic device configured with drawing software will define the pad layer as an external structure outside the bare chip, that is, consider the pad layer and the bare chip excluding the first pad as two electrically connected devices. In this way, when the bare chip is located on the PCB board, DRC in the drawing software will not report an error, and the bare chip can be placed on the PCB board. Finally, after the pad layer is established, electrically connect each first pad in the pad layer to the pins in the PCB board, so as to realize the electrical connection between the bare chip and the PCB board in the drawing software. This embodiment provides a layout drawing method, which can directly place the bare chip on the PCB board in the drawing software, facilitating the user to draw a layout with a bare chip and greatly improving the efficiency of the user drawing the layout.

[0057] Optionally, Figure 4 is a schematic flowchart of another layout drawing method provided according to an embodiment of the present invention. Refer to Figure 4 , and this layout drawing method includes the following steps:

[0058] S210. Receive a bare chip library establishment instruction, and establish a bare chip library according to the bare chip library establishment instruction, where the bare chip library includes various types of bare chips.

[0059] Specifically, an electronic device configured with drawing software can store a bare chip library. When the bare chip library in the electronic device does not include the type of bare chip required by the user, the user can send a bare chip library establishment instruction. After the electronic device configured with drawing software receives the bare chip library establishment instruction, it can set a new bare chip according to the bare chip library instruction and store the new bare chip in the original bare chip library of the electronic device, thereby enriching the bare chip library.

[0060] S220. Receive a selection and movement instruction, and select a corresponding bare chip from the bare chip library according to the selection and movement instruction, and move the bare chip to the PCB board.

[0061] Specifically, after the electronic device configured with drawing software receives the selection and movement instruction, the electronic device will select a bare chip of the corresponding type from the bare chip library according to the type of the bare chip in the selection and movement instruction, and then move the bare chip to the set position on the PCB board.

[0062] S230. Receive a pad layer establishment instruction, take the film layer where the first pad is located as the pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip.

[0063] Specifically, step S230 is the same as step S120. For the specific content of step S230, please refer to the description of step S120 for details and will not be elaborated here.

[0064] S240. Receive an electrical connection instruction, and electrically connect the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction.

[0065] Specifically, step S240 is the same as step S130. For the specific content of step S240, please refer to the description of step S130 for details and will not be elaborated here.

[0066] Optionally, receiving an electrical connection instruction and electrically connecting the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction includes: receiving the electrical connection instruction, selecting a bonding wire according to the electrical connection instruction, electrically connecting the first end of the bonding wire to the first pad in the pad layer, and electrically connecting the second end of the bonding wire to the pin in the PCB board.

[0067] Specifically, continue to refer to Figure 3 , the bonding wire 300 can be a device stored in an electronic device configured with drawing software, and the bonding wire 300 has electrical conductivity. When the electronic device does not include the bonding wire 300, a bonding wire establishment instruction can be sent to the electronic device configured with drawing software. After receiving the bonding wire establishment instruction, the electronic device configured with drawing software establishes the bonding wire.

[0068] Each first pad 110 has its corresponding pin 210 in the PCB board 200. After the electronic device configured with drawing software receives the electrical connection instruction, the first pad 110 is electrically connected to its corresponding pin 210 through the bonding wire 300.

[0069] Optionally, the bare chip includes at least two first pads; electrically connecting the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction includes: electrically connecting each first pad in the pad layer to its corresponding pin in the PCB board according to the electrical connection instruction.

[0070] Specifically, each first pad has its corresponding pin in the PCB board, and the electrical connection instruction includes the corresponding pin of each first pad in the PCB board. When the electronic device configured with drawing software receives the electrical connection instruction, it will analyze the corresponding pin of each first pad according to the electrical connection instruction, and then electrically connect the first pad to its corresponding pin.

[0071] Figure 5 is a schematic structural diagram of a layout drawing device provided according to an embodiment of the present invention. Refer to Figure 5, the layout drawing device provided in this embodiment includes: a selection and movement module 310, a pad layer establishment module 320, and an electrical connection module 330; the selection and movement module 310 is configured to receive a selection and movement instruction, select a corresponding bare chip according to the selection and movement instruction, and move the bare chip onto a PCB board, where the bare chip includes a chip body, at least one first pad, and a second pad equal in number to the first pads, the first pads are located on a first surface of the chip body, the second pads are located on a second surface of the chip body, the first surface and the second surface are oppositely arranged, each first pad has its corresponding second pad, and the first pad is electrically connected to its corresponding second pad; when the bare chip is moved onto the PCB board, the second pads are in contact with the PCB board; the pad layer establishment module 320 is configured to receive a pad layer establishment instruction, and use the layer where the first pads are located as the pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip; the electrical connection module 330 is configured to receive an electrical connection instruction, and electrically connect the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction.

[0072] Optionally, the layout drawing device provided in this embodiment further includes a bare chip library module; the bare chip library module is configured to receive a bare chip library establishment instruction, and establish a bare chip library according to the bare chip library establishment instruction, where the bare chip library includes various types of bare chips; the selection and movement module is specifically configured to select a corresponding bare chip from the bare chip library according to the selection and movement instruction, and move the bare chip onto the PCB board.

[0073] Optionally, the electrical connection module is specifically configured to receive an electrical connection instruction, select a bonding wire according to the electrical connection instruction, electrically connect a first end of the bonding wire to the first pads in the pad layer, and electrically connect a second end of the bonding wire to the pins in the PCB board.

[0074] The layout drawing device provided in this embodiment has corresponding beneficial effects as the layout drawing method provided in any embodiment of the present invention. For technical details not elaborated in this embodiment, refer to the layout drawing method provided in any embodiment of the present invention.

[0075] Figure 6 is a schematic structural diagram of an electronic device provided according to an embodiment of the present invention. Refer to Figure 6 , Figure 6FIG. 0 shows a schematic structural diagram of an electronic device 10 that can be used to implement an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0076] As Figure 6 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. The memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0077] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0078] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the layout drawing method.

[0079] In some embodiments, the layout drawing method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the layout drawing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the layout drawing method by any other suitable means (e.g., by means of firmware).

[0080] The various embodiments of the systems and techniques described above in this document may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0081] The computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer programs may be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0082] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0083] For providing interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used for providing interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0084] The systems and techniques described herein can be implemented in a computing system that includes backend components (such as, for example, a data server), or a computing system that includes middleware components (such as, for example, an application server), or a computing system that includes frontend components (such as, for example, a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (such as, for example, a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0085] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The relationship between the client and the server is created by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0086] It should be understood that various forms of processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0087] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A layout drawing method, characterized in that, comprising: Receiving a selection and movement instruction, selecting a corresponding bare chip according to the selection and movement instruction and moving the bare chip onto a PCB board, wherein the bare chip includes a chip body, at least one first pad and a second pad equal in number to the first pads, the first pads are located on a first surface of the chip body, the second pads are located on a second surface of the chip body, the first surface and the second surface are oppositely arranged, each first pad has its corresponding second pad, and the first pad is electrically connected to its corresponding second pad; when the bare chip is moved onto the PCB board, the second pads are in contact with the PCB board; Receiving a pad layer establishment instruction, taking the film layer where the first pads are located as a pad layer according to the pad layer establishment instruction, and defining the pad layer as an external structure outside the bare chip; Receiving an electrical connection instruction, and electrically connecting the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction; The chip body includes a through hole and a conductive layer corresponding to each first pad; the side wall of each through hole is covered with the conductive layer; The first pad is electrically connected to the second pad through the conductive layer on the side wall of the through hole.

2. The layout drawing method according to claim 1, characterized in that, before receiving the selection and movement instruction, further comprising: Receiving a bare chip library establishment instruction, establishing a bare chip library according to the bare chip library establishment instruction, wherein the bare chip library includes various types of bare chips; The selecting a corresponding bare chip according to the selection and movement instruction and moving the bare chip onto a PCB board includes: Selecting a corresponding bare chip from the bare chip library according to the selection and movement instruction and moving the bare chip onto the PCB board.

3. The layout drawing method according to claim 1, characterized in that, the receiving the electrical connection instruction, and electrically connecting the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction, includes: Receiving the electrical connection instruction, selecting bonding wires according to the electrical connection instruction, electrically connecting a first end of the bonding wires to the first pads in the pad layer, and electrically connecting a second end of the bonding wires to the pins in the PCB board.

4. The layout drawing method according to claim 1, characterized in that, the bare chip includes at least two first pads; the receiving the electrical connection instruction, and electrically connecting the first pads in the pad layer to the pins in the PCB board according to the electrical connection instruction, includes: Electrically connecting each first pad in the pad layer to its corresponding pin in the PCB board according to the electrical connection instruction.

5. A layout drawing device, characterized in that, comprising: A selection and movement module, a pad layer establishment module and an electrical connection module; The selected movement module is used to receive a selected movement instruction, and select a corresponding bare chip according to the selected movement instruction and move the bare chip onto the PCB board. Wherein, the first surface of the bare chip includes a first pad, the second surface of the bare chip includes a second pad, the first surface and the second surface are oppositely arranged, and the first pad is electrically connected to the second pad; the second surface is in contact with the PCB board; The pad layer establishment module is used to receive a pad layer establishment instruction, and use the film layer where the first pad is located as the pad layer according to the pad layer establishment instruction, and define the pad layer as an external structure outside the bare chip; The electrical connection module is used to receive an electrical connection instruction, and electrically connect the first pad in the pad layer to the pin in the PCB board according to the electrical connection instruction; The chip body includes a through hole and a conductive layer corresponding to each of the first pads; the side wall of each through hole is covered with a conductive layer; The first pad is electrically connected to the second pad through the conductive layer on the side wall of the through hole.

6. The layout drawing device according to claim 5, wherein, it further includes a bare chip library module; The bare chip library module is used to receive a bare chip library establishment instruction, and establish a bare chip library according to the bare chip library establishment instruction. Wherein, the bare chip library includes various types of bare chips; The selected movement module is specifically used to select a corresponding bare chip from the bare chip library according to the selected movement instruction and move the bare chip onto the PCB board.

7. The layout drawing device according to claim 5, wherein, The electrical connection module is specifically used to receive the electrical connection instruction, select a bonding wire according to the electrical connection instruction, electrically connect the first end of the bonding wire to the first pad in the pad layer, and electrically connect the second end of the bonding wire to the pin in the PCB board.

8. An electronic device, wherein, the electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the layout drawing method according to any one of claims 1-4.

9. A computer-readable storage medium, wherein, the computer-readable storage medium stores computer instructions for causing a processor to execute the layout drawing method according to any one of claims 1-4 when executed.

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