Nitride non-volatile multi-valued logic memory and method of fabrication

Abstract

The application discloses a nitride non-volatile multi-value logic memory and a manufacturing method, and mainly solves the problems of poor durability, high delay and large leakage of the existing nitride non-volatile memory. The memory comprises a substrate, a nucleation layer, a channel layer, a floating gate layer, a first barrier layer, a first quantum well layer, a second barrier layer, an isolation layer and a gate contact layer from bottom to top. The first barrier layer, the first quantum well layer and the second barrier layer form a first resonant tunneling diode, and a series layer, a third barrier layer, a second quantum well layer and a fourth barrier layer are arranged between the second barrier layer and the isolation layer, the third barrier layer, the second quantum well layer and the fourth barrier layer form a second resonant tunneling diode, source electrodes and drain electrodes are arranged on both sides of the floating gate layer, a gate electrode is arranged on the gate contact layer, and a triode structure device is formed. The application can increase the current difference of writing and erasing, reduce the delay and leakage, easily realize the multi-value logic state, and can be used for high-density storage and multi-value logic circuits.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a multi-valued logic memory that can be used for high-density storage and multi-valued logic circuits. Background Technology

[0002] Non-volatile memories (NMRs) have attracted widespread attention from researchers due to their non-volatility, byte-by-byte access, high storage density, and low power consumption. Their application in computer systems, in particular, can eliminate energy loss during computational latency, potentially significantly reducing system power consumption. GaN materials possess advantages such as a wide bandgap, high breakdown field strength, high saturated electron velocity, and high thermal conductivity. Furthermore, GaN materials have high longitudinal optical phonon energy, enabling GaN resonant tunneling diodes to achieve rapid interband transitions with short resonant tunneling times. Resonant tunneling memories based on GaN resonant tunneling diodes can operate on a picosecond timescale, realizing high-speed non-volatile random access memory (RAM) applicable to high-speed computing applications such as field-programmable gate arrays (FPGAs) and sensor network systems.

[0003] However, due to the strong built-in electric field and polarization characteristics of nitride materials, the typical resonant tunneling level alignment process only occurs once. This means that a double-barrier single-quantum-well GaN resonant tunneling diode has only one differential negative resistance region with a large peak-to-valley current ratio, which cannot achieve multi-valued logic characteristics for compact and efficient circuit design. However, by connecting different GaN resonant tunneling diodes in series in the vertical direction, multiple differential negative resistance regions can be achieved, making them suitable for multi-valued logic circuits and memory circuits.

[0004] In 2021, the National Institute of Advanced Industrial Science and Technology (NIST) of Japan reported a nitride nonvolatile memory structure in its article "Growth and Characterization of GaN / AlN Resonant Tunneling Diodes for High-Performance Nonvolatile Memory". Figure 1 As shown, it includes, from bottom to top, a substrate, a GaN buffer layer, and an n... + GaN emitter ohmic contact layer, first GaN isolation layer, first AlN barrier layer, GaN quantum well layer, second AlN barrier layer, second GaN isolation layer, n + GaN collector ohmic contact layer and collector electrode, in n + An emitter electrode is located on one side of the GaN emitter ohmic contact layer. This memory device has the following drawbacks:

[0005] 1. The device adopts a double-barrier single quantum well structure with only one differential negative resistance region, which can only generate two stable states, 0 and 1, and cannot generate multi-valued logic states, which is not conducive to simplifying circuit design and integration.

[0006] 2. The device adopts a double-barrier single quantum well structure. The peak voltage and valley voltage in the differential negative resistance region are close, and the peak and valley currents are relatively small. The difference between the 0-state and 1-state current values ​​of the memory is small. During repeated erase and write processes, the erase and write states may become indistinguishable due to instability.

[0007] 3. The durability of memory writing and erasing is poor. After repeated pulse application, the device output characteristics will produce errors and degradation.

[0008] 4. Uneven distribution of dislocations in the active region of the device leads to severe leakage current, resulting in charge leakage between the quantum well and the outside, causing instability and delay in memory switching. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of the existing technologies by proposing a nitride non-volatile multi-valued logic memory and its fabrication method. This increases the current difference between the write and erase states of the memory, reduces the instability, delay, and write / erase state errors of the switches, improves durability, and simplifies circuit design and integration.

[0010] The technical solution of this invention is implemented as follows:

[0011] 1. A nitride non-volatile multi-valued logic memory, comprising, from bottom to top, a substrate, a nucleation layer, a channel layer, a floating gate layer, a first barrier layer, a first quantum well layer, a second barrier layer, an isolation layer, and a gate contact layer, wherein the first quantum well layer, the second barrier layer, and the first barrier layer constitute a first resonant tunneling diode, characterized in that:

[0012] Between the second barrier layer and the isolation layer, there are sequentially arranged a series layer, a third barrier layer, a second quantum well layer and a fourth barrier layer. The third barrier layer, the second quantum well layer and the fourth barrier layer constitute a second resonant tunneling diode and are connected in series with the first resonant tunneling diode. By changing the thickness and doping of the series layer, the series resistance can be changed, thereby achieving the control of the peak spacing of the differential negative resistance.

[0013] The floating gate layer has source and drain electrodes on both sides, and a gate electrode is provided on the gate contact layer. A passivation layer is wrapped around the gate electrode to the outside of the nucleation layer to form a transistor structure.

[0014] The output state of the memory is controlled by vertical current transport of two resonant tunneling diodes and lateral current transport of a transistor.

[0015] Furthermore, the tandem layer is any one of GaN, InGaN, and InN, with a thickness of 30nm-200nm and a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 20 cm -3 ;

[0016] Furthermore, the third and fourth barrier layers are both made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1nm-3nm.

[0017] Furthermore, the second quantum well layer is made of any one of GaN, InGaN, or InN, and has a thickness of 1nm-3nm;

[0018] Furthermore, the passivation layer is made of any one of SiN, Al2O3, or HfO2 materials.

[0019] Furthermore, the substrate is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride.

[0020] Furthermore, the nucleation layer is made of any one of AlN, GaN, or AlGaN materials, and has a thickness of 3nm-1000nm.

[0021] Furthermore, the channel layer uses a doping concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 100nm and 200nm, n + GaN, n + InGaN, n + Any one of InN;

[0022] Furthermore, the floating gate layer is made of any one of GaN, InGaN, and InN, and its thickness is 4nm-15nm;

[0023] Furthermore, both the first and second barrier layers are made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1nm-3nm.

[0024] Furthermore, the first quantum well layer is made of any one of GaN, InGaN, or InN, and has a thickness of 1nm-3nm;

[0025] Furthermore, the isolation layer is made of any one of GaN, InGaN, and InN, and its thickness is 4nm-15nm;

[0026] Furthermore, the gate contact layer uses a doping concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 50nm and 200nm, n + GaN, n + InGaN, n + Any of InN.

[0027] 2. A method for fabricating a nitride non-volatile multi-valued logic memory, characterized by comprising the following:

[0028] 1) Nucleation layers of 3nm-1000nm are grown on a substrate using metal-organic chemical vapor deposition or molecular beam epitaxy.

[0029] 2) Using metal-organic chemical vapor deposition or molecular beam epitaxy, grow a doping concentration of 1×10⁻⁶ on the nucleation layer. 19 cm -3 -5×10 20 cm -3 A channel layer with a thickness of 100nm-200nm;

[0030] 3) A floating gate layer with a thickness of 4nm-15nm is grown on the channel layer using molecular beam epitaxy.

[0031] 4) A first barrier layer with a thickness of 1nm-3nm is grown on the floating gate layer using molecular beam epitaxy.

[0032] 5) A first quantum well layer with a thickness of 1 nm-3 nm is grown on the first barrier layer using molecular beam epitaxy.

[0033] 6) A second barrier layer with a thickness of 1 nm to 3 nm is grown on the first quantum well layer using molecular beam epitaxy.

[0034] 7) Using molecular beam epitaxy, a doping concentration of 1×10⁻⁶ was grown on the second barrier layer. 19 cm -3 -5×10 20 cm -3 A series layer with a thickness of 30nm-200nm;

[0035] 8) A third barrier layer with a thickness of 1 nm-3 nm was grown on the tandem layer using molecular beam epitaxy.

[0036] 9) A second quantum well layer with a thickness of 1 nm-3 nm was grown on the third barrier layer using molecular beam epitaxy.

[0037] 10) A fourth barrier layer with a thickness of 1 nm-3 nm was grown on the second quantum well using molecular beam epitaxy.

[0038] 11) An isolation layer with a thickness of 4nm-15nm was grown on the fourth barrier layer using molecular beam epitaxy.

[0039] 12) Using molecular beam epitaxy, a doping concentration of 1×10⁻⁶ is grown on the isolation layer. 19 cm -3 -5×10 20 cm -3 A gate contact layer with a thickness of 50nm-200nm;

[0040] 13) Using traditional optical lithography, a mesa isolation pattern is formed on the gate contact layer. Then, using photoresist as a mask, the epitaxial material is etched using inductively coupled plasma etching with a BCl3 / Cl2 gas source to form a square mesa isolation shallow trench with a depth to the nucleation layer.

[0041] 14) Electron beam lithography is used to form a square pattern on the gate contact layer. Using photoresist as a mask, the Ti / Au metal layer is evaporated by electron beam evaporation to form the gate electrode.

[0042] 15) Using the gate electrode metal as a mask, an inductively coupled plasma etching method is used with a BCl3 / Cl2 gas source to etch to the channel layer, forming a square mesa from the floating gate layer to the gate electrode.

[0043] 16) Using traditional optical lithography, source and drain electrode patterns are formed on the left and right sides of the channel layer. Then, using photoresist as a mask, the Ti / Al / Ni / Au metal layer is evaporated by electron beam evaporation to form the source and drain electrodes.

[0044] 17) A passivation layer with a thickness of 50nm-200nm is deposited on the surface of the entire device area using plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0045] 18) Using conventional optical lithography, the gate electrode, source electrode and drain electrode via patterns are formed on the passivation layer. Using photoresist as a mask, reactive ion etching is used with SF6 gas source to form the gate electrode, source electrode and drain electrode vias.

[0046] 19) Using traditional optical lithography, gate electrode, source electrode and drain electrode Pad patterns are formed on the surface of the gate electrode, source electrode and drain electrode via. Then, using photoresist as a mask, an Au metal layer is evaporated by electron beam evaporation to form gate electrode Pad, source electrode Pad and drain electrode Pad interconnected with the gate electrode, source electrode and drain electrode respectively, thus completing the memory fabrication.

[0047] Compared with the prior art, the present invention has the following advantages:

[0048] 1. This invention employs a structure of two resonant tunneling diodes connected in series in the vertical direction to transport current, enabling the realization of multiple logic states in the memory. The difference in peak voltage of the differential negative resistance can be adjusted by regulating the resistance of the series layer between the two resonant tunneling diodes. Simultaneously, the use of a three-terminal transistor allows for the control of the memory's output state. 2. Because this invention uses a structure of two resonant tunneling diodes connected in series in the vertical direction, it not only generates multiple differential negative resistance regions, realizing multiple logic states and achieving high storage density, thus simplifying circuit design and integration, but also increases the peak voltage difference and peak-to-valley current ratio in the differential negative resistance regions, improving peak current and solving the problem of indistinguishable 0 and 1 states due to instability during repeated erase and write operations.

[0049] 3. This invention uses molecular beam epitaxy to grow the epitaxial layer of the memory, which enables precise control of the material growth thickness. Furthermore, the epitaxial quantum well interface has a low dislocation density, low interface roughness, and small thickness fluctuation, which can reduce the instability and delay of memory switching, reduce memory leakage current, and improve the durability of memory writing and erasing. Attached Figure Description

[0050] Figure 1 This is a structural diagram of a traditional nitride non-volatile memory;

[0051] Figure 2 This is a structural diagram of the nitride non-volatile multi-valued logic memory of the present invention;

[0052] Figure 3 This is a schematic diagram of the process for fabricating a nitride non-volatile multi-valued logic memory according to the present invention. Detailed Implementation

[0053] Reference Figure 2 The present invention discloses a nitride non-volatile multi-valued logic memory, comprising a substrate 1, a nucleation layer 2, a channel layer 3, a floating gate layer 4, a first barrier layer 5, a first quantum well layer 6, a second barrier layer 7, a series layer 8, a third barrier layer 9, a second quantum well layer 10, a fourth barrier layer 11, an isolation layer 12, and a gate contact layer 13. Source and drain electrodes are provided on both sides of the floating gate layer 4. A gate electrode is provided on the gate contact layer 13. A passivation layer 14 surrounds the gate electrode to the outside of the nucleation layer.

[0054] The substrate 1 is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride.

[0055] The nucleation layer 2 is made of any one of AlN, GaN, or AlGaN materials, with a thickness of 3nm-1000nm, and is located on the substrate 1.

[0056] The channel layer 3 uses a doping concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 100nm and 200nm, n + GaN, n + InGaN, n + Any one of InN, which is located above nucleation layer 2;

[0057] The floating gate layer 4 is made of any one of GaN, InGaN, and InN, and its thickness is 4nm-15nm. It is located above the channel layer 3.

[0058] The first barrier layer 5, the second barrier layer 7, the third barrier layer 9 and the fourth barrier layer 11 are any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN and BPN, with a thickness of 1nm-3nm. The first barrier layer 5 is located above the floating gate layer 4, the second barrier layer 7 is located above the first quantum well 6, the third barrier layer 9 is located above the tandem layer 8, and the fourth barrier layer 11 is located above the second quantum well layer 10.

[0059] The first quantum well layer 6 and the second quantum well layer 10 are any one of GaN, InGaN, and InN, with a thickness of 1nm-3nm. The first quantum well layer 6 is located above the first barrier layer 5, and the second quantum well layer 10 is located above the third barrier layer 9.

[0060] The tandem layer 8 is made of any one of GaN, InGaN, or InN, with a thickness of 30nm-200nm and a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 20 cm -3 It is located above the second barrier layer 7;

[0061] The isolation layer 12 is made of any one of GaN, InGaN, and InN, and its thickness is 4nm-15nm. It is located above the fourth barrier layer 11.

[0062] The gate contact layer 13 uses a doping concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 50nm and 200nm, n + GaN, n + InGaN, n + Any one of InN, which is located above isolation layer 12;

[0063] The passivation layer 14 is made of any one of SiN, Al2O3, and HfO2 materials, and it is wrapped around the outside of the gate electrode to the nucleation layer.

[0064] The first barrier layer 5, the first quantum well layer 6, and the second barrier layer 7 constitute the first resonant tunneling diode; the third barrier layer 9, the second quantum well layer 10, and the fourth barrier layer 11 constitute the second resonant tunneling diode and are connected in series with the first resonant tunneling diode.

[0065] The floating gate layer 4 has source electrodes and drain electrodes on both sides, and the gate contact layer 13 has a gate electrode, forming a transistor structure.

[0066] Multiple differential negative resistance regions are generated by vertical transport current of two resonant tunneling diodes and lateral transport current of transistors, realizing multi-valued logic states of the memory. The difference in peak voltage of differential negative resistance can be controlled by changing the doping concentration and thickness of the series layer.

[0067] Reference Figure 3 The present invention provides three embodiments of a nitride non-volatile multi-valued logic memory and its fabrication method.

[0068] In Example 1, on a self-supporting gallium nitride substrate, the first, second, third, and fourth barrier layers are all made of AlN with a thickness of 1.5 nm, the first and second quantum well layers are both made of GaN with a thickness of 2.5 nm, and the tandem layer is made of GaN with a doping concentration of 5 × 10⁻⁶. 20 cm -3 A nitride non-volatile multi-valued logic memory with a GaN thickness of 30nm and a SiN passivation layer of 200nm thickness.

[0069] Step 1: Grow an AlN nucleation layer, such as... Figure 3 (a).

[0070] Molecular beam epitaxy was used to deposit a 3 nm thick AlN nucleation layer on a self-supporting gallium nitride substrate.

[0071] The process conditions used for depositing the AlN nucleation layer were: temperature 750℃, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 400W.

[0072] Step two, grow the channel layer, such as Figure 3 (b)

[0073] Molecular beam epitaxy was used to grow AlN nucleation layers with a doping concentration of 5 x 10⁻⁶. 20 cm -3 n with a thickness of 100nm + GaN channel layer.

[0074] The process conditions for growing the channel layer are: temperature 750℃, gallium beam equilibrium vapor pressure 3.5×10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.8 × 10⁻⁶. -8 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0075] Step 3, grow the floating gate layer, such as Figure 3 (c)

[0076] A GaN floating gate layer with a thickness of 15 nm was grown on the channel layer using molecular beam epitaxy.

[0077] The process conditions for growing the floating gate layer are: temperature 750℃, gallium beam equilibrium vapor pressure 3.5×10⁻⁶. -7 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0078] Step four, deposit the first barrier layer, such as Figure 3 (d)

[0079] A first AlN barrier layer with a thickness of 1.5 nm was deposited on the floating gate layer using molecular beam epitaxy.

[0080] The process conditions for depositing the first AlN barrier layer were: temperature 750℃, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, with a nitrogen plasma radio frequency source power of 400W.

[0081] Step 5: Deposit the first quantum well layer, as follows Figure 3 (e).

[0082] A first GaN quantum well layer with a thickness of 2.5 nm was deposited on the first AlN barrier layer using molecular beam epitaxy.

[0083] The process conditions for depositing the first GaN quantum well layer were: a temperature of 750℃ and a gallium beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0084] Step six, deposit the second barrier layer, such as Figure 3 (f).

[0085] A second AlN barrier layer with a thickness of 1.5 nm was deposited on the first GaN quantum well layer using molecular beam epitaxy.

[0086] The process conditions for depositing the second AlN barrier layer were: temperature 750℃, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, with a nitrogen plasma radio frequency source power of 400W.

[0087] The first AlN barrier layer, the first GaN quantum well layer, and the second AlN barrier layer form the first resonant tunneling diode.

[0088] Step 7, deposit tandem layers, such as Figure 3 (g)

[0089] Molecular beam epitaxy was used to deposit a doping concentration of 5 × 10⁻⁶ on the second AlN barrier layer. 20 cm -3 A GaN tandem layer with a thickness of 30nm.

[0090] The process conditions for depositing the tandem layer are: a temperature of 750℃ and a gallium beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.8 × 10⁻⁶. -8 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0091] Step 8: Deposit the third barrier layer, such as Figure 3 (h).

[0092] A third AlN barrier layer with a thickness of 1.5 nm was deposited on the tandem layer using molecular beam epitaxy.

[0093] The process conditions for depositing the third AlN barrier layer were: temperature 750℃, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, with a nitrogen plasma radio frequency source power of 400W.

[0094] Step nine, deposit the second quantum well layer, as follows: Figure 3 (i).

[0095] A second GaN quantum well layer with a thickness of 2.5 nm was deposited on the third AlN barrier layer using molecular beam epitaxy.

[0096] The process conditions for depositing the second GaN quantum well layer are: a temperature of 750℃ and a gallium beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0097] Step 10: Deposit the fourth barrier layer, such as... Figure 3 (j).

[0098] A fourth AlN barrier layer with a thickness of 1.5 nm was deposited on the second quantum well layer using molecular beam epitaxy.

[0099] The process conditions for depositing the fourth AlN barrier layer were: temperature 750℃, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, with a nitrogen plasma radio frequency source power of 400W.

[0100] The aforementioned third AlN barrier layer, second GaN quantum well layer, and fourth AlN barrier layer form a second resonant tunneling diode.

[0101] Step 11, grow an isolation layer, such as Figure 3 (k).

[0102] A GaN isolation layer with a thickness of 15 nm was grown on the fourth barrier layer using molecular beam epitaxy.

[0103] The process conditions for growing the GaN isolation layer are: temperature 750℃, gallium beam equilibrium vapor pressure 3.5×10⁻⁶. -7 Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0104] Step 12, grow the gate contact layer, such as Figure 3 (l).

[0105] Molecular beam epitaxy was used to grow a 200 nm thick layer with a doping concentration of 5 × 10⁻⁶ on the isolation layer. 20 cm -3 n + GaN gate contact layer.

[0106] growth n + The process conditions for the GaN gate contact layer are: a temperature of 750℃ and a gallium beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.8 × 10⁻⁶. -8Torr, nitrogen flow rate is 0.6 sccm, nitrogen plasma radio frequency source power is 400W.

[0107] Step thirteen: On the gate contact layer, perform spin coating, photolithography, development, and etching of the epitaxial material to form a mesh-like mesa isolation trench with a depth reaching the nucleation layer, such as... Figure 3 (m).

[0108] 13.1) The mesa isolation pattern is formed using photolithography:

[0109] 13.1a) Spin-coating AZ5214 photoresist, first at a spin speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating for 3 seconds at a speed of 4000 rad / min and an acceleration of 2000 rad / min. 2 Spin coat at 30s for 3min, then bake at 95℃ for 90s;

[0110] 13.1b) The AZ5214 photoresist on the gate contact layer is exposed using conventional optical lithography;

[0111] 13.1c) The exposed photoresist is developed using RZX-3038 developer for 45 seconds to form a grid-like mesa isolation pattern.

[0112] 13.2) Etching to form mesa isolation:

[0113] The inductively coupled plasma etching method is used to form mesa isolation with a depth to the nucleation layer by using photoresist as a mask.

[0114] The process conditions for inductively coupled plasma etching are: Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 300 s.

[0115] Step fourteen: A square photolithographic pattern is formed on the gate contact layer. Using photoresist as a mask, the Ti / Au metal layer is evaporated using electron beam evaporation to form the gate electrode, as shown below. Figure 3 (n).

[0116] 14.1) Photolithography forms a square mesa pattern:

[0117] 14.1a) Spin-coat PMMA A4 photoresist onto the gate contact layer, then spin-coat at a rotation speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin-coat for 3 seconds at a speed of 4000 rad / min and an acceleration of 2000 rad / min. 2 Spin coat at 180℃ for 30 seconds, then bake at 180℃ for 90 seconds;

[0118] 14.1b) Electron beam lithography was used to expose PMMA A4 photoresist with an electron dose ratio of 750.

[0119] 14.1c) Using a solution of tetramethyl dipentanone and isopropanol in a ratio of 3:1, the exposed photoresist was developed for 120 seconds and then fixed with isopropanol for 30 seconds to form a square mesa pattern.

[0120] 14.2) Electron beam evaporation is used, with a vacuum level of less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of Under the specified process conditions, a Ti / Au metal combination with a thickness of 0.04 μm / 0.5 μm was deposited on the gate contact layer after mesa isolation to complete the gate electrode fabrication.

[0121] Step 15: On the gate contact layer, perform homogenization, photolithography, development, and etching to form a square mesa from the floating gate layer to the gate electrode, as shown below. Figure 3 (o).

[0122] 15.1) The mesa isolation pattern is formed using photolithography:

[0123] 15.1a) Spin-coating AZ5214 photoresist, first at a spin speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coating for 3 seconds at a speed of 4000 rad / min and an acceleration of 2000 rad / min. 2 Spin coat at 30s for 3min, then bake at 95℃ for 90s;

[0124] 15.1b) The AZ5214 photoresist on the gate contact layer is exposed using conventional optical lithography;

[0125] 15.1c) The exposed photoresist is developed using RZX-3038 developer for 45 seconds to form a mesa isolation pattern.

[0126] 15.2) Etching to form a square mesa:

[0127] Using inductively coupled plasma etching, a square mesa with a depth reaching the floating gate layer is formed by etching with photoresist as a mask.

[0128] The process conditions for inductively coupled plasma etching are: Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 300 s.

[0129] Step sixteen: Form source and drain electrodes on the left and right sides of the channel layer, such as... Figure 3 (p).

[0130] 16.1) Photolithography to form source and drain electrode patterns:

[0131] 16.1a) Spin-coat AZ5214 photoresist on both sides of the GaN channel layer, first at a rotation speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coat for 3 seconds at 4000 rad / min, then at 2000 rad / min with an acceleration of 2000 rad. 2 Spin coat at 30s for 3min, then bake at 95℃ for 90s;

[0132] 16.1b) The AZ5214 photoresist on the GaN channel layer is exposed using conventional optical lithography;

[0133] 16.1c) The photoresist after exposure is developed with RZX-3038 developer for 45 seconds to form source and drain electrode patterns on the left and right sides of the channel layer.

[0134] 16.2) Using electron beam evaporation, Ti / Al / Ni / Au metal composites were deposited on the channel layer with metal thicknesses of 0.05μm / 0.12μm / 0.08μm / 0.08μm respectively; then, rapid thermal annealing was performed for 30s in a nitrogen atmosphere at 830℃ to form the source electrode and drain electrode.

[0135] The process conditions for electron beam evaporation are: vacuum degree less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of

[0136] Step 17: Deposit a passivation layer, such as... Figure 3 (q).

[0137] A 200 nm thick SiN passivation layer was deposited in the surface region from the gate electrode to the nucleation layer using plasma-enhanced chemical vapor deposition.

[0138] The process conditions used in the plasma-enhanced chemical vapor deposition method are: time 60s, pressure 2200mTorr, temperature 350℃, SiH4 flow rate 13.5sccm, NH3 flow rate 10sccm, and N2 flow rate 1000sccm.

[0139] Step 18: Photolithography and etching are performed on the SiN passivation layer to form gate, source, and drain vias, such as... Figure 3 (r).

[0140] 18.1) Photolithography is used to form the gate electrode, source electrode, and drain electrode via patterns on the SiN passivation layer:

[0141] 18.1a) Spin-coating AZ5214 photoresist onto the SiN passivation layer, first at a rotation speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin coat for 3 seconds at 4000 rad / min, then at 2000 rad / min with an acceleration of 2000 rad. 2 Rotate at 30 seconds per minute, then bake at 95°C for 90 seconds.

[0142] 18.1b) Using conventional optical lithography, the AZ5214 photoresist on the SiN passivation layer is exposed;

[0143] 18.1c) The exposed photoresist is developed with RZX-3038 developer for 45 seconds to form three via patterns: gate electrode, source electrode, and drain electrode.

[0144] 18.2) Using reactive ion etching, with photoresist as a mask, the gate electrode via pattern, source electrode via pattern and drain electrode via pattern are etched onto the metal surfaces of the gate electrode, source electrode and drain electrode respectively to form the gate electrode, source electrode and drain electrode via.

[0145] The process conditions used in the reactive ion etching method are: pressure of 1500 mTorr, power of 200 W, SF6 flow rate of 8 sccm, CHF3 flow rate of 10 sccm, and He flow rate of 150 sccm.

[0146] Step nineteen: Photolithography and evaporation are performed on the gate electrode via, source electrode via, and drain electrode via to form the gate electrode metal pad, source electrode metal pad, and drain electrode metal pad, as shown below. Figure 3 (s).

[0147] 19.1) Photolithographically form the gate electrode, source electrode, and drain electrode metal pad patterns on the gate electrode via, source electrode via, and drain electrode via:

[0148] 19.1a) Spin-coat AZ5214 photoresist onto the gate, source, and drain vias, first at a rotation speed of 500 rad / min and an acceleration of 1000 rad. 2 / Spin-coat for 3 seconds at a speed of 4000 rad / min and an acceleration of 2000 rad / min. 2 Spin coat at 30s for 3min, then bake at 95℃ for 90s;

[0149] 19.1b) The AZ5214 photoresist was exposed using a traditional optical lithography method;

[0150] 19.1c) The exposed photoresist is developed with RZX-3038 developer for 45 seconds to form the gate electrode, source electrode and drain electrode metal pad patterns;

[0151] 19.2) Using electron beam evaporation, the metal lead patterns of the gate electrode, source electrode, and drain electrode are shaped according to... Au metal with a thickness of 80 nm was evaporated at a certain rate and then soaked in acetone to form gate electrode metal pad, source electrode metal pad and drain electrode metal pad respectively, thus completing the memory fabrication.

[0152] In Example 2, on a sapphire substrate, the first, second, third, and fourth barrier layers are fabricated using InAlN with a thickness of 3 nm; the first and second quantum well layers are fabricated using InGaN with a thickness of 1 nm; and the tandem layer is fabricated using InGaN with a thickness of 200 nm and a doping concentration of 1 × 10⁻⁶. 20 cm -3 In 0.1 Ga 0.9 N, the passivation layer is a 50nm thick Al2O3 nitride non-volatile multi-valued logic memory.

[0153] Step 1, grow a GaN nucleation layer, such as Figure 3 (a).

[0154] Using metal-organic chemical vapor deposition (MOCVD), a 500 nm thick GaN nucleation layer was deposited on a sapphire substrate under the following process conditions: temperature 1300 °C, pressure 40 Torr, gallium source flow rate 200 sccm, ammonia flow rate 5000 sccm, and hydrogen flow rate 3500 sccm.

[0155] Step 2, Growth In 0.1 Ga 0.9 N-channel layer, such as Figure 3 (b)

[0156] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 600℃, pressure 200 Torr, gallium source flow rate 50 sccm, indium source flow rate 120 sccm, silicon source flow rate 200 sccm, ammonia flow rate 3000 sccm, and hydrogen flow rate 3000 sccm, a 200 nm thick GaN nucleation layer with a doping concentration of 1 x 10⁻⁶ was grown on a GaN nucleation layer. 20 cm -3 In 0.1 Ga 0.9 N-channel layer.

[0157] Step 3, Growth In 0.1 Ga 0.9 N-floating gate layer, such as Figure 3 (c)

[0158] Molecular beam epitaxy was used at a temperature of 540℃, a nitrogen flow rate of 1.6 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, nitrogen RF source power 350W process conditions, in In 0.1 Ga 0.9 An 8nm thick In layer is grown on the N-channel layer. 0.1 Ga 0.9 N-floating gate layer.

[0159] Step 4, Growth In 0.1 Al 0.9 N is the first barrier layer, such as Figure 3 (d)

[0160] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 2.1 × 10⁻⁶. -7 Torr, with a nitrogen plasma RF source power of 350W, in In 0.1 Ga 0.9 An In layer with a thickness of 3 nm and an In composition of 10% is deposited on the N-type floating gate layer. 0.1 Al 0.9 N is the first barrier layer.

[0161] Step 5, Growth In 0.1 Ga 0.9 N first quantum well layer, such as Figure 3 (e).

[0162] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Al 0.9 An In layer with a thickness of 1 nm is deposited on the first barrier layer. 0.1 Ga 0.9 N is the first quantum well layer.

[0163] Step 6, Growth In 0.1 Al 0.9 N is the second barrier layer, such as Figure 3 (f).

[0164] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶.-7 Torr, the equilibrium vapor pressure of the aluminum beam is 2.1 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Ga 0.9 An In layer with a thickness of 3 nm and an In composition of 10% is deposited on the first quantum well layer. 0.1 Al 0.9 N is the second barrier layer.

[0165] The above In 0.1 Al 0.9 N First Barrier Layer, In 0.1 Ga 0.9 N first quantum well layer and In 0.1 Al 0.9 The second barrier layer forms the first resonant tunneling diode.

[0166] Step 7, Growth In 0.1 Ga 0.9 N-series layers, such as Figure 3 (g)

[0167] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.2 × 10⁻⁶. - 8 Torr, a nitrogen-based RF source with a power of 380W, under process conditions in In 0.1 Al 0.9 A 200 nm thick doping concentration of 1 × 10⁻⁶ is deposited on the second barrier layer. 20 cm -3 In 0.1 Ga 0.9 N-series layers.

[0168] Step 8, Growth In 0.1 Al 0.9 N is the third barrier layer, such as Figure 3 (h).

[0169] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 2.1 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Ga 0.9 An In layer with a thickness of 3 nm and an In composition of 10% is deposited on the N-tandem layer.0.1 Al 0.9 N is the third barrier layer.

[0170] Step 9, Growth In 0.1 Ga 0.9 N second quantum well layer, such as Figure 3 (i).

[0171] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Al 0.9 An In layer with a thickness of 1 nm is deposited on the third barrier layer. 0.1 Ga 0.9 N-second quantum well layer.

[0172] Step 10, Growth In 0.1 Al 0.9 N is the fourth barrier layer, such as Figure 3 (j).

[0173] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 2.1 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Ga 0.9 An In layer with a thickness of 3 nm and an In composition of 10% is deposited on the second quantum well layer. 0.1 Al 0.9 N is the fourth barrier layer.

[0174] The above In 0.1 Al 0.9 N third barrier layer, In 0.1 Ga 0.9 N second quantum well layer and In 0.1 Al 0.9 The fourth barrier layer N forms a second resonant tunneling diode.

[0175] Step 11, Growth In 0.1 Ga 0.9 N isolation layer, such as Figure 3 (k).

[0176] Molecular beam epitaxy was used at a temperature of 540℃, a nitrogen flow rate of 1.6 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶. -7Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Al 0.9 A 10nm thick In layer is grown on the fourth barrier layer. 0.1 Ga 0.9 N isolation layer.

[0177] Step 12, Growth In 0.1 Ga 0.9 N gate contact layer, such as Figure 3 (l).

[0178] Molecular beam epitaxy was used, with the temperature set at 540℃, nitrogen flow rate at 1.6 sccm, and indium beam equilibrium vapor pressure at 0.8 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.2 × 10⁻⁶. - 8 Torr, a nitrogen-based RF source with a power of 350W, under In... 0.1 Ga 0.9 A 100 nm thick N-isolation layer with a doping concentration of 1 x 10⁻⁶ is grown on it. 20 cm -3 In 0.1 Ga 0.9 N-gate contact layer.

[0179] Step 13, in In 0.1 Ga 0.9 On the N-gate contact layer, epitaxial material is homogenized, photolithographically etched, developed, and etched to form a grid-like mesa-shaped isolation trench with a depth reaching the nucleation layer, such as... Figure 3 (m).

[0180] The specific implementation of this step is the same as step thirteen in Example 1.

[0181] Step 14, in In 0.1 Ga 0.9 A square photolithographic pattern is formed on the N-type gate contact layer. Using photoresist as a mask, a Ti / Au metal layer is evaporated on the photolithographic pattern using electron beam evaporation to form the gate electrode. Figure 3 (n).

[0182] 14a) Photolithography forms a square mesa pattern:

[0183] The specific implementation of this step is the same as step 14.1) in Embodiment 1.

[0184] 14b) Electron beam evaporation technology is used, with a vacuum level of less than 1.5 × 10⁻⁶. -3Pa, power range of 300-800W, evaporation rate of The process conditions are as follows: a gate electrode is deposited on a square photolithographic pattern, wherein the deposited metal is a Ti / Au metal combination with a metal thickness of 0.03μm / 0.4μm.

[0185] Step 15, in In 0.1 Ga 0.9 On the N-gate contact layer, homogenization, photolithography, development, and etching are performed to form a square mesa extending from the floating gate layer to the gate electrode, such as... Figure 3 (o).

[0186] The specific implementation of this step is the same as step fifteen of Embodiment 1.

[0187] Step 16, in In 0.1 Ga 0.9 Source and drain electrodes are formed on the left and right sides of the N-channel layer, such as Figure 3 (p).

[0188] 16a) In In 0.1 Ga 0.9 Source and drain electrode patterns are formed on both sides of the N-channel layer by photolithography:

[0189] The specific implementation of this step is the same as step 16.1) in Embodiment 1.

[0190] 16b) Electron beam evaporation technology is used, with a vacuum level of less than 1.6 × 10⁻⁶. -3 Pa, power range of 600-900W, evaporation rate of Under the specified process conditions, metals were deposited on the source and drain electrode patterns, respectively. The deposited metals were a Ti / Al / Ni / Au metal combination with a thickness of 0.02μm / 0.2μm / 0.05μm / 0.05μm. Then, rapid thermal annealing was performed for 30s in a nitrogen atmosphere at 830℃ to form the source and drain electrodes.

[0191] Step 17: Deposit a 50nm Al2O3 dielectric passivation layer, such as... Figure 3 (q).

[0192] Using atomic layer deposition (ALD) with the following process conditions set: time 40 s, pressure 2000 mTorr, temperature 300 °C, Al(CH3)3 flow rate 850 sccm, H2O flow rate 350 sccm, and N2 flow rate 1000 sccm, a 50 nm thick Al2O3 dielectric passivation layer was deposited on the surface region from the gate electrode to the nucleation layer.

[0193] Step 18: Photolithography and etching are performed on the Al2O3 passivation layer to form gate electrode, source electrode, and drain electrode vias, such as... Figure 3(r).

[0194] The specific implementation of this step is the same as step eighteen of Embodiment 1.

[0195] Step 19: Form gate electrode metal pads, source electrode metal pads, and drain electrode metal pads on the gate electrode via, source electrode via, and drain electrode via, respectively, as follows: Figure 3 (s).

[0196] The specific implementation of this step is the same as step nineteen in Example 1.

[0197] In Example 3, on a silicon substrate, the first, second, third, and fourth barrier layers are fabricated using AlGaN with a thickness of 1 nm; the first and second quantum well layers are fabricated using InN with a thickness of 3 nm; and the tandem layer is fabricated using InN with a thickness of 50 nm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The InN is a non-volatile multi-valued logic memory with a passivation layer of HfO2 nitride with a thickness of 100 nm.

[0198] Step A: Using molecular beam epitaxy (MBE), at a temperature of 650℃, a nitrogen flow rate of 3.0 sccm, and an aluminum beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 7.5 × 10⁻⁶. -7 Under the process conditions of Torr, with a nitrogen RF source power of 380W, an Al layer with a thickness of 1000nm was deposited on a silicon substrate. 0.8 Ga 0.2 N nucleation layer, such as Figure 3 (a).

[0199] Step B involves molecular beam epitaxy at a temperature of 500℃, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.0 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 380W, under Al 0.8 Ga 0.2 A 120 nm thick N-nucleation layer with a doping concentration of 1 × 10⁻⁶ is grown on it. 19 cm -3 n + InN channel layer, such as Figure 3 (b)

[0200] Step C involves molecular beam epitaxy at a temperature of 500℃, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, under process conditions, in n+ A 4nm thick InN floating gate layer is grown on the InN channel layer, such as Figure 3 (c)

[0201] Step D involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an aluminum beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 The equilibrium vapor pressure of the gallium beam is 7.5 × 10⁻⁶. -7 Under the process conditions of Torr and a nitrogen plasma RF source power of 380W, a first Al layer with a thickness of 1nm and an Al composition of 40% was deposited on the InN floating gate layer. 0.4 Ga 0.6 N-barrier layer, such as Figure 3 (d)

[0202] Step E: Molecular beam epitaxy is used at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, under process conditions of a nitrogen RF source power of 380W, in the first Al 0.4 Ga 0.6 A first InN quantum well layer with a thickness of 3 nm is deposited on the N barrier layer, such as Figure 3 (e).

[0203] Step F involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an aluminum beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 The equilibrium vapor pressure of the gallium beam is 7.5 × 10⁻⁶. -7 Under the process conditions of Torr and a nitrogen plasma RF source power of 380W, a second Al layer with a thickness of 1nm and an Al composition of 40% was deposited on the first InN quantum well layer. 0.4 Ga 0.6 N-barrier layer, the aforementioned first Al 0.4 Ga 0.6 N-barrier layer, first InN quantum well layer, and second Al 0.4 Ga 0.6 The N-barrier layer forms the first resonant tunneling diode, such as Figure 3 (f).

[0204] Step G involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.0 × 10⁻⁶. -8 Torr, under process conditions of a nitrogen RF source power of 380W, in the second Al 0.4 Ga 0.6A 50 nm thick N-barrier layer with a doping concentration of 1 × 10⁻⁶ is deposited on it. 19 cm -3 InN cascaded layers, such as Figure 3 (g)

[0205] Step H involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an aluminum beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 The equilibrium vapor pressure of the gallium beam is 7.5 × 10⁻⁶. -7 Under the process conditions of Torr and a nitrogen plasma RF source power of 380W, a third Al layer with a thickness of 1nm and an Al composition of 40% was deposited on the InN tandem layer. 0.4 Ga 0.6 N-barrier layer, such as Figure 3 (h).

[0206] Step I: Molecular beam epitaxy was performed at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, under the process conditions of the third Al 0.4 Ga 0.6 A second InN quantum well layer with a thickness of 3 nm is deposited on the N barrier layer, such as Figure 3 (i).

[0207] Step J involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an aluminum beam equilibrium vapor pressure of 3.5 × 10⁻⁶. -7 The equilibrium vapor pressure of the gallium beam is 7.5 × 10⁻⁶. -7 Under the process conditions of Torr and a nitrogen plasma RF source power of 380W, a fourth Al with a thickness of 1nm and an Al composition of 40% was deposited on the second InN quantum well. 0.4 Ga 0.6 N-barrier layer, the aforementioned third Al 0.4 Ga 0.6 N-barrier layer, second InN quantum well layer and fourth Al 0.4 Ga 0.6 The N-barrier layer forms a second resonant tunneling diode, such as Figure 3 (j).

[0208] Step K involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, under the process conditions of the fourth Al 0.4 Ga 0.6 A 4nm thick InN isolation layer is deposited on the N barrier layer, such as Figure 3 (k).

[0209] Step L involves using molecular beam epitaxy at a temperature of 500°C, a nitrogen flow rate of 3.0 sccm, and an indium beam equilibrium vapor pressure of 2.3 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.0 × 10⁻⁶. -8 Torr, under process conditions of 380W nitrogen RF source power, deposits a 50nm thick InN isolation layer with a doping concentration of 1×10⁻⁶. 19 cm -3 n + InN gate contact layer, such as Figure 3 (l).

[0210] Step M, in n + On the InN gate contact layer, epitaxial material is homogenized, photolithographically etched, developed, and etched to form a grid-like mesa-shaped isolation trench with a depth reaching the nucleation layer, such as... Figure 3 (m).

[0211] The specific implementation of this step is the same as step thirteen in Example 1.

[0212] Step N, in n + A square photolithographic pattern is formed on the InN gate contact layer. Using photoresist as a mask, a Ti / Au metal layer is evaporated on the photolithographic pattern using electron beam evaporation to form the gate electrode. Figure 3 (n).

[0213] N1) Photolithography forms a square mesa pattern:

[0214] The specific implementation of this step is the same as step 14a) in Example 1.

[0215] N2) uses electron beam evaporation technology in vacuum conditions less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of Under the specified process conditions, metal is deposited on a square mesa pattern to fabricate a gate electrode, wherein the deposited metal is a Ti / Au metal combination with a metal thickness of 0.02μm / 0.3μm.

[0216] Step O, in n + On the InN gate contact layer, homogenization, photolithography, development, and etching are performed to form a square mesa from the floating gate layer to the gate electrode, such as... Figure 3 (o).

[0217] The specific implementation of this step is the same as step fifteen of Embodiment 1.

[0218] Step P, in n + Source and drain electrodes are formed on the left and right sides of the InN channel layer, such as Figure 3 (p).

[0219] P1) in n + The source and drain electrode patterns are formed on both sides of the InN channel layer by photolithography:

[0220] The specific implementation of this step is the same as step 16.1) in Embodiment 1.

[0221] P2) Using electron beam evaporation technology, in a vacuum degree less than 1.4 × 10⁻⁶ -3 Pa, power range of 400-800W, evaporation rate of Under the specified process conditions, Ti / Al / Ni / Au metal composites were deposited on the source and drain electrode patterns, with metal thicknesses of 0.02μm / 0.05μm / 0.04μm / 0.04μm, respectively. Then, rapid thermal annealing was performed at 830℃ in a nitrogen atmosphere to form the source and drain electrodes.

[0222] Step Q: Deposit an HfO2 dielectric passivation layer, such as... Figure 3 (q).

[0223] Using atomic layer deposition (ALD), under the following conditions: time 70 s, temperature 280 °C, ethyl methylamino hafnium flow rate 1200 sccm, H2O flow rate 110 sccm, and N2 flow rate 1000 sccm, a 100 nm thick HfO2 dielectric passivation layer was deposited in the surface region from the gate electrode to the nucleation layer.

[0224] Step R involves photolithography and etching on the Al2O3 passivation layer to form gate, source, and drain vias, such as... Figure 3 (r).

[0225] The specific implementation of this step is the same as step eighteen of Embodiment 1.

[0226] Step S: Gate electrode metal pads, source electrode metal pads, and drain electrode metal pads are formed on the gate electrode via, source electrode via, and drain electrode via, respectively, as shown below. Figure 3 (s).

[0227] The specific implementation of this step is the same as step nineteen in Example 1.

[0228] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. For example, in addition to self-supporting gallium nitride, sapphire, and silicon, the substrate may also be any one of silicon carbide, diamond, aluminum nitride, and boron nitride; in addition to AlN, InAlN, and AlGaN, the first barrier layer, second barrier layer, third barrier layer, and fourth barrier layer may also be any one of InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A nitride non-volatile multi-valued logic memory, comprising, from bottom to top, a substrate (1), a nucleation layer (2), a channel layer (3), a floating gate layer (4), a first barrier layer (5), a first quantum well layer (6), a second barrier layer (7), an isolation layer (12), and a gate contact layer (13), wherein the first quantum well layer (6), the second barrier layer (7), and the first barrier layer (5) constitute a first resonant tunneling diode; characterized in that: Between the second barrier layer (7) and the isolation layer (12), there are sequentially arranged a series layer (8), a third barrier layer (9), a second quantum well layer (10) and a fourth barrier layer (11). The series resistance is changed by changing the thickness and doping of the series layer, thereby controlling the differential negative resistance peak spacing. The third barrier layer (9), the second quantum well layer (10) and the fourth barrier layer (11) constitute the second resonant tunneling diode and are connected in series with the first resonant tunneling diode. The floating gate layer (4) has source electrodes and drain electrodes on both sides, and a gate electrode is provided on the gate contact layer (13). The gate electrode to the outside of the nucleation layer (2) is wrapped with a passivation layer (14) to form a transistor structure. The output state of the memory is controlled by vertical current transport of two resonant tunneling diodes and lateral current transport of a transistor.

2. The memory as claimed in claim 1, characterized in that: The tandem layer (8) is made of any one of GaN, InGaN, or InN, with a thickness of 30 nm-200 nm and a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 20 cm -3 ; The third barrier layer (9) and the fourth barrier layer (11) are both made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1 nm to 3 nm. The second quantum well layer (10) is made of any one of GaN, InGaN, or InN, and has a thickness of 1 nm to 3 nm. The passivation layer (14) is made of any one of SiN, Al2O3, or HfO2 materials.

3. The memory as described in claim 1, characterized in that: The substrate (1) is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride. The nucleation layer (2) is made of any one of AlN, GaN, or AlGaN materials, and has a thickness of 3 nm to 1000 nm. The channel layer (3) is doped with a concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 100 nm and 200 nm, n + GaN, n + InGaN, n + Any one of InN; The floating gate layer (4) is any one of GaN, InGaN, and InN, and its thickness is 4 nm-15 nm.

4. The memory as claimed in claim 1, characterized in that: The first barrier layer (5) and the second barrier layer (7) are both made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1 nm to 3 nm. The first quantum well layer (6) is made of any one of GaN, InGaN, or InN, and has a thickness of 1 nm to 3 nm. The isolation layer (12) is any one of GaN, InGaN, and InN, and its thickness is 4 nm-15 nm. The gate contact layer (13) is doped with a concentration of 1x10⁻⁶. 19 cm -3 -5x10 20 cm -3 Between 50 nm and 200 nm, n + GaN, n + InGaN, n + Any of InN.

5. A method for fabricating a nitride non-volatile multi-valued logic memory, characterized in that, Including the following: 1) Nucleation layers of 3 nm to 1000 nm are grown on a substrate using metal-organic chemical vapor deposition or molecular beam epitaxy. 2) Using metal-organic chemical vapor deposition or molecular beam epitaxy, grow a doping concentration of 1×10⁻⁶ on the nucleation layer. 19 cm -3 -5×10 20 cm -3 A channel layer with a thickness of 100 nm-200 nm; 3) A floating gate layer with a thickness of 4 nm-15 nm was grown on the channel layer using molecular beam epitaxy. 4) A first barrier layer with a thickness of 1 nm-3 nm is grown on the floating gate layer using molecular beam epitaxy. 5) A first quantum well layer with a thickness of 1 nm-3 nm is grown on the first barrier layer using molecular beam epitaxy. 6) A second barrier layer with a thickness of 1 nm-3 nm is grown on the first quantum well layer using molecular beam epitaxy. 7) Using molecular beam epitaxy, a layer with a thickness of 30 nm-200 nm and a doping concentration of 1 × 10⁻⁶ is grown on the second barrier layer. 19 cm -3 -5×10 20 cm -3 Serial layers; 8) A third barrier layer with a thickness of 1 nm-3 nm was grown on the tandem layer using molecular beam epitaxy. 9) A second quantum well layer with a thickness of 1 nm-3 nm was grown on the third barrier layer using molecular beam epitaxy. 10) A fourth barrier layer with a thickness of 1 nm-3 nm was grown on the second quantum well using molecular beam epitaxy. 11) An isolation layer with a thickness of 4 nm-15 nm was grown on the fourth barrier layer using molecular beam epitaxy. 12) Using molecular beam epitaxy, a doping concentration of 1×10⁻⁶ is grown on the isolation layer. 19 cm -3 -5×10 20 cm -3 A gate contact layer with a thickness of 50 nm-200 nm; 13) Using traditional optical lithography, a mesa isolation pattern is formed on the gate contact layer. Then, using photoresist as a mask, the epitaxial material is etched using inductively coupled plasma etching with a BCl3 / Cl2 gas source to form a square mesa isolation shallow trench with a depth to the nucleation layer. 14) Electron beam lithography is used to form a square pattern on the gate contact layer. Using photoresist as a mask, the Ti / Au metal layer is evaporated by electron beam evaporation to form the gate electrode. 15) Using the gate electrode metal as a mask, an inductively coupled plasma etching method is used with a BCl3 / Cl2 gas source to etch to the channel layer, forming a square mesa from the floating gate layer to the gate electrode; 16) Using traditional optical lithography, source and drain electrode patterns are formed on the left and right sides of the channel layer. Then, using photoresist as a mask, the Ti / Al / Ni / Au metal layer is evaporated by electron beam evaporation to form the source and drain electrodes. 17) A passivation layer with a thickness of 50 nm-200 nm is deposited from the gate electrode to the surface of the nucleation layer using plasma-enhanced chemical vapor deposition or atomic layer deposition. 18) Using conventional optical lithography, the gate electrode, source electrode and drain electrode via patterns are formed on the passivation layer. Using photoresist as a mask, reactive ion etching is used with SF6 gas source to form the gate electrode, source electrode and drain electrode vias respectively. 19) Using traditional optical lithography, gate electrode, source electrode and drain electrode Pad patterns are formed on the surface of the gate electrode, source electrode and drain electrode via. Then, using photoresist as a mask, an Au metal layer is evaporated by electron beam evaporation to form gate electrode Pad, source electrode Pad and drain electrode Pad interconnected with the gate electrode, source electrode and drain electrode respectively, thus completing the memory fabrication.

6. The manufacturing method as described in claim 5, characterized in that: The process conditions for the metal-organic chemical vapor deposition in steps 1) and 2) are as follows: The temperature is 600 o C-1300 o C, pressure 40 Torr-200 Torr, ammonia flow rate 3000 sccm-5000 sccm, aluminum source flow rate 4 sccm-50 sccm, gallium source flow rate 50 sccm-200 sccm, indium source flow rate 60 sccm-120 sccm, silicon source flow rate 200 sccm-500 sccm, hydrogen flow rate 3000 sccm-5000 sccm.

7. The method as described in claim 5, characterized in that: The molecular beam epitaxy method in steps 1)-12) has the following process conditions: Temperature is 500 o C-750 o C, nitrogen flow rate is 0.6 sccm-3.0 sccm, gallium beam equilibrium vapor pressure is 3.5×10 -7 Torr-7.5×10 -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.6 × 10⁻⁶. -7 Torr-3.5×10 -7 Torr, the equilibrium vapor pressure of the indium beam is 0.8 × 10⁻⁶. -7 Torr-2.3×10 -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.0 × 10⁻⁶. -8 Torr-3.8×10 -8 Torr, with a nitrogen RF source power of 350 W-400 W.

8. The method as described in claim 5, characterized in that: The conventional optical lithography method in steps 13) and 15) uses the following process conditions: AZ5214 photoresist is used, and the rotation speed is 500 rad / min, and the acceleration is 1000 rad. 2 / Spin-coat for 3 seconds at a speed of 4000 rad / min and an acceleration of 2000 rad / min. 2 Spin coating for 30 seconds at a speed of 1000 min, baking time for 90 seconds, temperature for 95℃; developer used RZX-3038, development time for 45 seconds.

9. The method as described in claim 5, characterized in that: The electron beam lithography method used in 14) has the following process conditions: PMMA A4 photoresist is used, the baking time is 90s, and the temperature is 180°C. o C, electron dose ratio of 750, lithographic circular pattern diameter of 1µm-4µm, developer of 3:1 tetramethyldipentanone and isopropanol, time of 120s, fixer of isopropanol, time of 30s.

10. The method as described in claim 5, characterized in that: The plasma-enhanced chemical vapor deposition method used in step 17) has the following process conditions: pressure of 2200 mTorr and temperature of 350°C. o C, SiH4 flow rate is 13.5 sccm, NH3 flow rate is 10 sccm, N2 flow rate is 1000 sccm, and time is 30s-120s.

11. The method as described in claim 5, characterized in that: The inductively coupled plasma etching method in steps 13) and 15) has the following process conditions: Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 300s-420s.

12. The method as described in claim 5, characterized in that: The electron beam evaporation method in steps 14) and 16) has the following process conditions: vacuum degree less than 1.4 × 10⁻⁶. -3 Pa -1.6×10 -3 Process conditions with a power range of 300~900 W and an evaporation rate of 1-3 Å / s.

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