Layout structure and its design methods and systems, digital cell library, equipment and media

Abstract

A layout structure, its design method and system, digital cell library, device, and medium are disclosed. The method includes: providing multiple initial layout layers, each including N-type active regions and P-type active regions, and multiple gate patterns; allocating multiple gate plug patterns according to the digital cells corresponding to each initial layout layer to form different digital cell layouts, including a first digital cell layout and a second digital cell layout. In each digital cell layout, the gate plug pattern is located at least in the active region. The layout of the gate plug pattern includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal. This invention improves the flexibility of digital cell layout design.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a layout structure and its design method and system, digital cell library, device and medium. Background Technology

[0002] In designing digital cell layouts, three factors need to be considered: power consumption, performance, and area. However, these three factors are interdependent; typically, improvements in digital cell performance often lead to increases in both area and power consumption. Therefore, it is necessary to consider the actual application scenarios and design a customized digital cell layout library to meet the requirements.

[0003] As the size of digital cells continues to shrink, many new processes and technologies have been introduced, which has improved the performance of digital cells and reduced power consumption and area when digital cells reach the same frequency.

[0004] However, the current digital unit layout is still difficult to adapt to more application scenarios. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a layout structure and its design method and system, a digital cell library, device and medium, thereby improving the flexibility of digital cell layout design.

[0006] To address the aforementioned problems, embodiments of the present invention provide a layout structure design method, comprising: providing multiple initial layout layers for forming different digital units, each initial layout layer including an active region, the active region including an N-type active region and a P-type active region adjacent along a first direction, the initial layout layer further including multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction, the gate patterns spanning the N-type active region and the P-type active region, the first direction being perpendicular to the second direction; allocating multiple gate plug patterns according to the digital units corresponding to each initial layout layer to form different multiple digital unit layouts, the digital unit layout including a first digital unit layout and a second digital unit layout. In each of the digital cell layouts, a plurality of gate plug patterns are located above the gate pattern, and the gate plug patterns are located at least above the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are equal.

[0007] Accordingly, embodiments of the present invention also provide a layout structure, including: multiple digital unit layouts for forming different digital units, including a first digital unit layout and a second digital unit layout, each of the digital unit layouts including an active region, the active region including an N-type active region and a P-type active region adjacent along a first direction; the digital unit layout includes: a gate layout layer, the gate layout layer including multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction, the gate patterns spanning the N-type active region and the P-type active region, the first direction being perpendicular to the second direction; a gate plug layout layer, located above the gate layout layer, the gate plug layout layer including multiple gate plug patterns, the... The gate plug pattern is located above the gate pattern, and the gate plug pattern is located at least in the active region; wherein, depending on the application scenario of the digital unit corresponding to each digital unit layout, the layout of the gate plug pattern includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are equal.

[0008] Accordingly, this invention also provides a layout structure design system, comprising: an initial layout layer providing module, configured to provide multiple initial layout layers for forming different digital units, each initial layout layer including an active region, the active region including an N-type active region and a P-type active region adjacent along a first direction, the initial layout layer further including multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction, the gate patterns spanning the N-type active region and the P-type active region, the first direction being perpendicular to the second direction; and a pattern allocation module, configured to allocate multiple gate plug patterns according to the digital units corresponding to each initial layout layer, forming different multiple digital unit layouts, the digital unit layout including a first digital unit... In the first digital cell layout and the second digital cell layout, in each digital cell layout, a plurality of gate plug patterns are located above the gate pattern, and the gate plug patterns are located at least above the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are equal.

[0009] Accordingly, embodiments of the present invention also provide a digital unit library, including the layout structure provided in embodiments of the present invention.

[0010] Accordingly, embodiments of the present invention also provide an apparatus, including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the layout structure design method provided in embodiments of the present invention.

[0011] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the layout structure design method provided in embodiments of the present invention.

[0012] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0013] In the layout structure design method provided by this invention, multiple gate plug patterns are allocated to each initial layout layer to form multiple digital cell layouts of different types. The digital cell layout includes a first digital cell layout and a second digital cell layout. The layout of the gate plug patterns includes one or two of the following: the number of gate plug patterns in the N-type active regions of the first and second digital cell layouts is not equal; the number of gate plug patterns in the P-type active regions of the first and second digital cell layouts is not equal; and in digital cells, when the cell areas are equal, the gate plugs formed on the gate structure of the N-type active region and the gate plugs formed on the P-type active region are... The different ratios of gate plugs on the gate structure of the active region will have a corresponding impact on the performance of the digital unit. Therefore, in the present invention embodiment, when designing the digital unit layout, in the step of allocating multiple gate plug patterns to each initial layout layer, the number of gate plug patterns allocated to the N-type active region and the P-type active region in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital unit. Under the condition of satisfying the design rules, as many gate plug patterns as possible can be allocated in the N-type active region, or as many gate plug patterns as possible can be allocated in the P-type active region, forming a digital unit layout that meets the requirements of various application scenarios, thereby improving the flexibility of the digital unit layout design.

[0014] In the layout structure provided by this embodiment of the invention, the digital cell layout includes a gate plug layer located above the gate plug layer. The gate plug layer includes multiple gate plug patterns. The layout of the gate plug patterns includes one or two of the following: the number of gate plug patterns in the N-type active regions of the first and second digital cell layouts is not equal; the number of gate plug patterns in the P-type active regions of the first and second digital cell layouts is not equal. When the cell areas of the digital cells are equal, the difference in the ratio of the number of gate plugs on the gate structure in the N-type active region to the number of gate plugs on the gate structure in the P-type active region will affect... The performance of the digital unit is affected accordingly. Therefore, in the embodiments of the present invention, in the digital unit layout, according to the distribution of the number of gate plug patterns in the N-type active region and the P-type active region in each digital unit layout, the digital units corresponding to different digital unit layouts can adapt to the needs of different application scenarios. In the N-type active region, a digital unit layout with more gate plug patterns than other digital unit layouts, or in the P-type active region, a digital unit layout with more gate plug patterns than other digital unit layouts, can enable the digital units corresponding to the digital unit layout to meet the needs of various application scenarios, thereby facilitating the diversification of the application of the digital unit layout. Attached Figure Description

[0015] Figure 1 This is a flowchart of an embodiment of the layout structure design method of the present invention;

[0016] Figures 2 to 4 This is a schematic diagram of each step in one embodiment of the design method for the standard layout structure of the present invention;

[0017] Figure 5 This is a schematic diagram of an embodiment of the layout structure of the present invention;

[0018] Figure 6 This is a functional block diagram of an embodiment of the layout structure design system of the present invention;

[0019] Figure 7 This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation

[0020] As the background technology shows, the design of digital cell layouts requires consideration of three factors: power consumption, performance, and area. However, these three factors are interdependent; typically, improvements in digital cell performance often lead to increases in both area and power consumption.

[0021] In the layout of a digital cell, active and drain doped regions are formed on both sides of the gate structure in the active region. Therefore, in traditional processes, due to the limitations of photolithography alignment accuracy, the plugs on the gate structure located in the active region may short-circuit with the source and drain doped layers of the active region, leading to digital cell failure. Therefore, plugs cannot be added to the gate structure in the active region of the digital cell layout to connect to the upper metal layer; that is, gate plugs can only be formed in the passive region.

[0022] With advancements in process technology, improved alignment precision in photolithography, and the introduction of self-aligned processes, it has become possible to add plugs to the gate structure in the active region. This allows for the formation of gate plugs, also known as contact over active gates (COAGs), on the gate structure in the active region. The introduction of COAGs enables gate plugs to be formed not only in passive regions but also in active regions, which helps reduce the cell area of ​​the digital cell layout, thereby achieving further miniaturization of the chip.

[0023] However, although the introduction of COAG has saved a significant amount of cell area in digital cell layout, the current distribution of COAG in digital cell layout is relatively simple. Consequently, the digital cells formed by using digital cell layout are also relatively simple, making it difficult to meet the increasingly diverse application scenarios of today.

[0024] To address the aforementioned technical problems, embodiments of the present invention provide a layout structure design method. (See reference...) Figure 1 The flowchart illustrates an embodiment of the layout structure design method of the present invention.

[0025] In this embodiment, the layout structure design method includes the following basic steps:

[0026] Step S1: Provide multiple initial layout layers for forming different digital units. Each initial layout layer includes an active region. The active region includes an N-type active region and a P-type active region adjacent to each other along a first direction. The initial layout layer also includes multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction. The gate patterns span the N-type active region and the P-type active region. The first direction is perpendicular to the second direction.

[0027] Step S2: Assign multiple gate plug patterns to the digital cells corresponding to each initial layout layer to form multiple digital cell layouts of different types. The layout layers include a first digital cell layout and a second digital cell layout. In each digital cell layout, multiple gate plug patterns are located above the gate pattern, and the gate plug patterns are located at least above the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are equal.

[0028] In digital cells, when the cell areas are equal, the ratio of the number of gate plugs formed on the gate structure of the N-type active region to the number of gate plugs formed on the gate structure of the P-type active region will have a corresponding impact on the performance of the digital cell. Therefore, in this embodiment of the invention, when designing the digital cell layout, in the step of allocating multiple gate plug patterns to each initial layout layer, the number of gate plug patterns allocated to the N-type active region and the P-type active region in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital cell. Under the condition of satisfying the design rules, as many gate plug patterns as possible can be allocated in the N-type active region, or as many gate plug patterns as possible can be allocated in the P-type active region, forming a digital cell layout that meets the requirements of various application scenarios, thereby improving the flexibility of the digital cell layout design.

[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 2 to 4 This is a schematic diagram of each step in one embodiment of the layout structure design method of the present invention.

[0031] refer to Figure 2 Step S1: Provide multiple initial version layers 10 for forming different digital units, each initial version layer 10 including an active region 100A, the active region 100A including a region along a first direction (e.g., ...). Figure 2 (As shown in the X direction) Adjacent N-type active regions 100N and P-type active regions 100P, the initial plate layer 10 also includes extending along the first direction and along the second direction (as shown in the X direction). Figure 2Multiple gate patterns 110 arranged in parallel (as shown in the Y direction) span the N-type active region 100N and the P-type active region 100P, with the first direction perpendicular to the second direction.

[0032] The layout structure design method is used to form a digital unit layout. The initial layout layer 10 is used as the base layout for digital unit layout design, and the formed digital unit layout is used to form different digital units.

[0033] Digital cell layout is used to form digital cells. The types of digital cells include various basic units such as NAND gates, flip-flops, inverters, AND gates, registers, data selectors, and full adders. Each digital cell corresponds to multiple cell circuits of different sizes (W / L) and different drive capabilities.

[0034] Accordingly, in this embodiment, the types of digital units include NAND gates, AND gates, flip-flops, multiplexers (MUX), or inverters (INV).

[0035] In the process of multi-channel data transmission, a circuit that can select any one of the channels as needed is called a data selector, also known as a multiplexer or multiplexer switch.

[0036] An inverter is a circuit that can reverse the phase of an input signal by 180 degrees.

[0037] The layout of the digital unit corresponding to the data selector is more complex, while the layout of the digital unit corresponding to the inverter is simpler. However, the layout structure design method in this embodiment can be used to obtain data selectors or inverters that are suitable for more application scenarios.

[0038] The active region 100A is the area where active devices are formed.

[0039] Depending on the doping type, active devices include N-type active devices and P-type active devices. Accordingly, in this embodiment, the active region 100A includes an N-type active region 100N and a P-type active region 100P that are adjacent along the first direction.

[0040] In this embodiment, the initial layer 10 also includes a passive region 100U located between adjacent N-type active regions 100N and P-type active regions 100P, and the gate pattern 110 also spans the passive region 100U.

[0041] The passive region 100U is the area where passive devices are formed. Typically, the passive region 100U is used to isolate adjacent active regions 100A. Therefore, the passive region 100U is located between adjacent N-type active regions 100N and P-type active regions 100P, and the gate pattern 110 also spans the passive region 100U.

[0042] The gate pattern 110 is used to form a gate structure, which is used to control the opening or closing of the device channel.

[0043] In this embodiment, the initial layer 10 also includes a fin pattern (not shown) located in the active region 100A, the fin pattern extending along the second direction and arranged parallel to the first direction.

[0044] Fin patterns are used to form fins, which in turn provide channels for the device.

[0045] In this embodiment, the fin pattern is located below the gate pattern 110.

[0046] In semiconductor manufacturing, the gate structure spans the fins in its region and covers part of the top and sidewalls of the fins. Therefore, the gate pattern 110 is orthogonal to the fin pattern in the active region 100A. Specifically, when there are multiple fin patterns in the active region 100A, one gate pattern 110 is orthogonal to multiple fin patterns.

[0047] In this embodiment, COAG patterns can be designed in the active region 100A, thereby forming multiple fin patterns in both the N-type active region 100N and the P-type active region 100P, which greatly saves the unit area of ​​the digital unit layout.

[0048] As an example, both the N-type active region 100N and the P-type active region 100P include three fin patterns.

[0049] In this embodiment, the unit area of ​​each initial layer 10 is equal, so that the unit area of ​​each subsequent digital unit layout is equal.

[0050] In this embodiment, the initial layer 10 further includes: source-drain interconnect patterns (not shown), located on both sides of the gate pattern 110, extending along a first direction and arranged parallel to each other along a second direction.

[0051] Source-drain interconnect patterns are used to form source-drain interconnects, which are used to bring out the electrical properties of the source-drain doped layers of the device.

[0052] In semiconductor manufacturing, source and drain doped layers are formed in the fins on both sides of the gate structure. Therefore, in this embodiment, the source and drain interconnect pattern is located on both sides of the gate pattern 110.

[0053] In this embodiment, the initial layer 10 further includes: a gate cut-off pattern (not shown), which is orthogonal to a portion of the gate pattern.

[0054] The gate cut-off pattern is used to define the cut-off position of the gate structure and to form a gate isolation structure at the cut-off position. Thus, in practical applications, a gate cut-off pattern orthogonal to the gate pattern is formed at the position where the gate structure needs to be cut off.

[0055] In semiconductor manufacturing, the gate structure is formed first, and then the gate structure is cut off.

[0056] It should be noted that in this embodiment, the number of gate patterns 110 in each initial layer 10 is the same, and the number of fin patterns in each initial layer 10 is the same. Accordingly, the unit area of ​​each initial layer 10 is equal.

[0057] In this embodiment, before allocating multiple gate plug patterns according to the digital units corresponding to each initial version layer 10, the method further includes: determining the application scenario of the digital units corresponding to each initial version layer 10.

[0058] Different digital units are used in different application scenarios (e.g., high-frequency scenarios or low-power scenarios), and different application scenarios will place different requirements on the performance of digital units. Accordingly, the application scenario is related to the type of digital unit.

[0059] As an example, in this embodiment, the digital unit includes a first type of digital unit and a second type of digital unit. The frequency of the application scenario of the first type of digital unit is greater than that of the application scenario of the second type of digital unit. According to the frequency requirements of the application scenario of the digital unit, the digital unit layout corresponding to the first type of digital unit and the second type of digital unit is designed subsequently.

[0060] As an example, in this embodiment, the digital unit includes a first type of digital unit and a second type of digital unit. The power consumption of the second type of digital unit application scenario is less than that of the first type of digital unit application scenario. According to the power consumption requirements of the digital unit application scenario, the digital unit layout corresponding to the first type of digital unit and the second type of digital unit is designed subsequently.

[0061] Reference Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the first digital unit layout. Figure 4This is a schematic diagram of the second digital cell layout. Step S2 is executed: Multiple gate plug patterns 120 are allocated according to the digital cells corresponding to each initial layout layer 10, forming multiple digital cell layouts of different types (not shown). The layout layers include a first digital cell layout 10a and a second digital cell layout 10b. In each digital cell layout, multiple gate plug patterns 120 are located above gate patterns 110, and the gate plug patterns 120 are at least located above the active region 100A. The layout of the gate plug patterns 120 includes one or more of the following: First... The number of gate plug patterns 120 in the N-type active region 100N of the first digital cell layout 10a and the second digital cell layout 10b is not equal; the number of gate plug patterns 120 in the N-type active region 100N of the first digital cell layout 10a and the second digital cell layout 10b is equal; the number of gate plug patterns 120 in the P-type active region 100P of the first digital cell layout 10a and the second digital cell layout 10b is not equal; the number of gate plug patterns 120 in the P-type active region 100P of the first digital cell layout 10a and the second digital cell layout 10b is equal.

[0062] In this embodiment, based on the application scenario of the digital unit corresponding to each initial layout layer 10, multiple gate plug patterns 120 are assigned to each initial layout layer 10 to form multiple digital unit layouts of different types.

[0063] Gate plug pattern 120 is used to form a gate plug, which is used to bring out the electrical properties of the gate structure.

[0064] In digital cells, when the cell areas are equal, the different ratios of the number of gate plugs formed on the gate structure of the N-type active region 100N and the number of gate plugs formed on the gate structure of the P-type active region 100P will have a corresponding impact on the performance of the digital cell. Therefore, in this embodiment, when designing the digital cell layout, in the step of allocating multiple gate plug patterns 120 to each initial layout layer 10, the number of gate plug patterns 120 allocated to the N-type active region 100N and the P-type active region 100P in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital cell. Under the condition of satisfying the design rules, as many gate plug patterns 120 as possible can be allocated to the N-type active region 100N, or as many gate plug patterns as possible can be allocated to the P-type active region 100P, forming a digital cell layout that meets the requirements of various application scenarios, thereby improving the flexibility of digital cell layout design.

[0065] In this embodiment, the gate plug pattern 120 is also located above the gate pattern 110 of the passive region 100U.

[0066] In this embodiment, the gate plug pattern 120 is located above the gate pattern 110 of the active region 100A. Correspondingly, when forming the digital cell corresponding to the digital cell layout, a COAG structure can be formed, saving the cell area of ​​the digital cell layout. At the same time, in order to make full use of the top space of the gate structure, the gate plug can also be formed on the gate structure of the passive region 100U. Correspondingly, the gate plug pattern 120 is also located above the gate pattern 110 of the passive region 100U.

[0067] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit include: the frequency of the first type of digital unit application scenario is greater than the frequency of the second type of digital unit application scenario.

[0068] Accordingly, the first digital cell layout 10a is used to form the first type of digital cell, and the second layout 10b is used to form the second type of digital cell. In the N-type active region 100N, the number of gate plug patterns 120 in the first digital cell layout 10a is greater than the number of gate plug patterns 120 in the second digital cell layout 10b.

[0069] In actual semiconductor manufacturing processes, the different placement of the COAG structure on top of the gate structure does not affect the DC electrical parameters of the digital cell, such as the threshold voltage and saturation current. However, it does affect the capacitance and resistance of the digital cell. Specifically, due to the different doping types of the P-type active region 100P and the N-type active region 100N, when the COAG structure is formed in the N-type active region 100N, the digital cell has a larger capacitance and a smaller resistance, resulting in a higher operating frequency and higher power consumption.

[0070] Therefore, in semiconductor digital cells, when the COAG structure is formed on the gate structure of the N-type active region 100N, it is beneficial to improve the operating frequency of the digital cell.

[0071] Specifically, the cell areas of the first digital cell layout 10a and the second digital cell layout 10b are equal. Compared with the second digital cell layout 10b, in the N-type active region 100N, the number of gate plug patterns 120 in the first digital cell layout 10a is greater than the number of gate plug patterns 120 in the second digital cell layout 10b. Consequently, the operating frequency of the first type of digital cell is greater than the operating frequency of the second type of digital cell, thus satisfying the situation where the frequency of the first type of digital cell application scenario is greater than the frequency of the second type of digital cell application scenario.

[0072] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit also include: the power consumption of the second type of digital unit application scenario is less than the power consumption of the first type of digital unit application scenario.

[0073] Accordingly, the first digital cell layout 10a is used to form the first type of digital cell, and the second digital cell layout 10b is used to form the second type of digital cell. In the P-type active region 100N, the number of gate plug patterns 120 in the second digital cell layout 10b is greater than the number of gate plug patterns 120 in the first digital cell layout 10a.

[0074] In actual semiconductor manufacturing processes, when the COAG structure is formed in a 100pP P-shaped active region, the digital cell has a small capacitance and a large resistance, resulting in lower power consumption and a lower operating frequency.

[0075] Therefore, in a semiconductor digital cell, when the COAG structure is formed on the gate structure of the P-type active region 100P, it is beneficial to reduce the operating power consumption of the semiconductor digital cell.

[0076] Specifically, the cell areas of the first digital cell layout 10a and the second digital cell layout 10b are equal. Compared with the second digital cell layout 10b, in the P-type active region 100P, the number of gate plug patterns 120 in the first digital cell layout 10a is greater than the number of gate plug patterns 120 in the second digital cell layout 10b. Consequently, the power consumption of the first type of digital cell is less than that of the second type of digital cell, thus satisfying the requirement that the power consumption of the first type of digital cell application scenario is less than that of the second type of digital cell application scenario.

[0077] In this embodiment, the total number of gate plug patterns 120 located in the N-type active region 100N and the P-type active region 100P is equal in the second digital unit layout 10b and the first digital unit layout 10a.

[0078] For digital units with the same circuit structure and identical transistor dimensions, the required number of gate plugs is consistent. In other words, the total number of gate plug patterns 120 in the digital unit layout forming the same digital unit is consistent. In this embodiment, the total number of gate plug patterns 120 in the N-type active region 100N and P-type active region 100P of the second digital unit layout 10b is equal to the total number of gate plug patterns 120 in the N-type active region 100N and P-type active region 100P of the first digital unit layout 10a. The number of gate plug patterns 120 in the passive region 100U is also equal, which is beneficial for forming digital unit layouts with consistent areas. This improves the design flexibility of digital unit layouts while making the dimensions of digital unit layouts more consistent, reducing the complexity of forming the corresponding digital units in the subsequent digital unit layout.

[0079] In this embodiment, after assigning multiple gate plug patterns 120 to each initial layer 10, the method further includes assigning contact hole patterns, first metal line patterns, and second metal line patterns to each initial layer 10.

[0080] The contact hole pattern is used to form an interconnect plug, the first metal line pattern is used to form a first metal line, the second metal line pattern is used to form a second metal line, the interconnect plug is used to electrically interconnect the source / drain interconnect with the first metal line, or to electrically interconnect the first metal line with the second metal line, and the first metal line, the second metal line, and the interconnect plug are used to realize the back-end interconnect of the digital unit.

[0081] Accordingly, the present invention also provides a layout structure. Figure 5 This is a schematic diagram of an embodiment of the layout structure of the present invention.

[0082] refer to Figure 5 The layout structure includes: multiple digital unit layouts for forming different digital units, including a first digital unit layout (such as...). Figure 5 (a)) and the second digital unit layout (e.g. Figure 5 (b)) Each digital unit layout includes an active region 100A, and the active region 100A includes a region along a first direction (e.g., Figure 5 (As shown in the X direction) Adjacent N-type active regions 100N and P-type active regions 100P; the digital cell layout includes: a gate plate layer, the gate plate layer including extending along a first direction and along a second direction (as shown in the X direction); Figure 5 Multiple gate patterns 110 arranged in parallel (as shown in the Y direction) span the N-type active region 100N and the P-type active region 100P, with the first direction perpendicular to the second direction; a gate plug layer, located above the gate pattern layer, includes multiple gate plug patterns 120, which are located above the gate patterns 110 and are at least located in the active region 100A; wherein, the layout of the gate plug patterns 120 is determined according to the application scenario of the digital unit corresponding to each digital unit layout. This includes one or more of the following situations: the number of gate plug patterns 120 in the N-type active region 100N of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns 120 in the N-type active region 100N of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns 120 in the P-type active region 100P of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns 120 in the P-type active region 100P of the first digital cell layout and the second digital cell layout are equal.

[0083] The first and second digital unit layouts are used to form the first type of digital unit and the second type of digital unit, respectively.

[0084] Digital cell layout is used to form digital cells. Digital cells include various basic units such as NAND gates, flip-flops, inverters, AND gates, registers, data selectors, and full adders. Each digital cell corresponds to multiple cell circuits of different sizes (W / L) and different drive capabilities.

[0085] Accordingly, in this embodiment, the types of digital units include NAND gates, AND gates, flip-flops, data selectors, or inverters.

[0086] In the process of multi-channel data transmission, a circuit that can select any one of the channels as needed is called a data selector, also known as a multiplexer or multiplexer switch.

[0087] An inverter is a circuit that can reverse the phase of an input signal by 180 degrees.

[0088] The digital cell layout corresponding to a data selector is more complex, while the digital cell layout corresponding to an inverter is simpler. However, the digital cell layout design method in this embodiment can be used to obtain data selectors or inverters that are suitable for more application scenarios.

[0089] The active region 100A is the area where active devices are formed.

[0090] Depending on the doping type, active devices include N-type active devices and P-type active devices. Accordingly, in this embodiment, the active region 100A includes an N-type active region 100N and a P-type active region 100P that are adjacent along the first direction.

[0091] In this embodiment, the digital cell layout also includes a passive region 100U located between adjacent N-type active regions 100N and P-type active regions 100P, and the gate pattern 110 also spans the passive region 100U.

[0092] The passive region 100U is the area where passive devices are formed. Typically, the passive region 100U is used to isolate adjacent active regions 100A. Therefore, the passive region 100U is located between adjacent N-type active regions 100N and P-type active regions 100P, and the gate pattern 110 also spans the passive region 100U.

[0093] The gate pattern 110 is used to form a gate structure, which is used to control the opening or closing of the device channel.

[0094] In this embodiment, the digital unit layout also includes a fin layout layer, which includes fin patterns located in the active region 100A. The fin patterns extend along the second direction and are arranged in parallel along the first direction.

[0095] Fin patterns are used to form fins, which in turn provide channels for the device.

[0096] In this embodiment, the fin pattern is located below the gate pattern 110.

[0097] In semiconductor manufacturing, the gate structure spans the fins in its region and covers part of the top and sidewalls of the fins. Therefore, the gate pattern 110 is orthogonal to the fin pattern in the active region 100A. Specifically, when there are multiple fin patterns in the active region 100A, one gate pattern 110 is orthogonal to multiple fin patterns.

[0098] In this embodiment, COAG patterns can be designed in the active region 100A, thereby forming multiple fin patterns in both the N-type active region 100N and the P-type active region 100P, which greatly saves the unit area of ​​the digital unit layout.

[0099] As an example, both the N-type active region 100N and the P-type active region 100P include three fin patterns.

[0100] In this embodiment, the area of ​​each digital unit layout is equal.

[0101] In this embodiment, the digital cell layout further includes a source-drain interconnect layer, which includes source-drain interconnect patterns located on both sides of the gate pattern 110. The source-drain interconnect patterns extend along a first direction and are arranged in parallel along a second direction.

[0102] Source-drain interconnect patterns are used to form source-drain interconnects, which are used to bring out the electrical properties of the source-drain doped layers of the device.

[0103] In semiconductor manufacturing, source and drain doped layers are formed in the fins on both sides of the gate structure. Therefore, in this embodiment, the source and drain interconnect pattern is located on both sides of the gate pattern 110.

[0104] In this embodiment, the digital cell layout further includes a gate cut-off layer, which includes a gate cut-off pattern that is orthogonal to a portion of the gate pattern.

[0105] The gate cut-off pattern is used to define the cut-off position of the gate structure and to form a gate isolation structure at the cut-off position, so that in practical applications, a gate cut-off pattern with orthogonal gate pattern is formed at the position where the gate structure needs to be cut off.

[0106] In semiconductor manufacturing, the gate structure is formed first, and then the gate structure is cut off.

[0107] It should be noted that in this embodiment, the number of gate patterns 110 in each digital unit layout is the same, and the number of fin patterns in each digital unit layout is the same. Accordingly, the unit area of ​​each digital unit layout is equal.

[0108] In this embodiment, different digital units are used in different application scenarios (e.g., high-frequency scenarios or low-power scenarios), and different application scenarios will impose different requirements on the performance of the digital units.

[0109] As an example, in this embodiment, the frequency of the first type of digital unit application scenario is greater than the frequency of the second type of digital unit application scenario.

[0110] As an example, in this embodiment, the power consumption of the second type of digital unit application scenario is less than that of the first type of digital unit application scenario.

[0111] Gate plug pattern 120 is used to form a gate plug, which is used to bring out the electrical properties of the gate structure.

[0112] In digital cells, when the cell areas are equal, the ratio of the number of gate plugs on the gate structure of the N-type active region 100N to the number of gate plugs on the gate structure of the P-type active region 100P will have a corresponding impact on the performance of the digital cell. Therefore, in this embodiment, in the digital cell layout, according to the number distribution of gate plug patterns 120 in the N-type active region 100N and the P-type active region 100P in each digital cell layout, the digital cells corresponding to different digital cell layouts can adapt to the needs of different application scenarios. A digital cell layout with more gate plug patterns 120 in the N-type active region 100N than other digital cell layouts, or a digital cell layout with more gate plug patterns 120 in the P-type active region 100P than other digital cell layouts, can enable the digital cells corresponding to the digital cell layout to meet the needs of various application scenarios, thereby facilitating the diversification of the application of the digital cell layout.

[0113] In this embodiment, the gate plug pattern 120 is also located above the gate pattern 110 of the passive region 100U.

[0114] In this embodiment, the gate plug pattern 120 is located above the gate pattern 110 of the active region 100A. Correspondingly, when forming the digital cell corresponding to the digital cell layout, a COAG structure can be formed, saving the cell area of ​​the digital cell layout. At the same time, in order to make full use of the top space of the gate structure, the gate plug can also be formed on the gate structure of the passive region 100U. Correspondingly, the gate plug pattern 120 is also located above the gate pattern 110 of the passive region 100U.

[0115] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit include: the frequency of the first type of digital unit application scenario is greater than the frequency of the second type of digital unit application scenario.

[0116] Accordingly, the first digital cell layout is used to form the first type of digital cell, and the second digital cell layout is used to form the second type of digital cell. In the N-type active region 100N, the number of gate plug patterns 120 in the first digital cell layout is greater than the number of gate plug patterns 120 in the second digital cell layout.

[0117] In actual semiconductor manufacturing processes, the different placement of the COAG structure on top of the gate structure does not affect the DC electrical parameters of the digital cell, such as the threshold voltage and saturation current. However, it does affect the capacitance and resistance of the digital cell. Specifically, due to the different doping types of the P-type active region 100P and the N-type active region 100N, when the COAG structure is formed in the N-type active region 100N, the digital cell has a larger capacitance and a smaller resistance, resulting in a higher operating frequency and higher power consumption.

[0118] Therefore, in semiconductor digital cells, when the COAG structure is formed on the gate structure of the N-type active region 100N, it is beneficial to improve the operating frequency of the digital cell.

[0119] Specifically, the cell areas of the first digital cell layout and the second digital cell layout are equal. Compared with the second digital cell layout, in the N-type active region 100N, the number of gate plug patterns 120 in the first digital cell layout is greater than the number of gate plug patterns 120 in the second digital cell layout. Consequently, the operating frequency of the first type of digital cell is greater than the operating frequency of the second type of digital cell, thus satisfying the situation where the frequency of the first type of digital cell application scenario is greater than the frequency of the second type of digital cell application scenario.

[0120] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit also include: the power consumption of the second type of digital unit application scenario is less than the power consumption of the first type of digital unit application scenario.

[0121] Accordingly, the first digital cell layout is used to form the first type of digital cell, and the second digital cell layout is used to form the second type of digital cell. In the P-type active region 100N, the number of gate plug patterns 120 in the second digital cell layout is greater than the number of gate plug patterns 120 in the first digital cell layout.

[0122] In actual semiconductor processes, when the COAG structure is formed in the 100p P-shaped active region, the digital cell has a smaller capacitance and a larger resistance, resulting in lower power consumption and a lower operating frequency.

[0123] Therefore, in a semiconductor digital cell, when the COAG structure is formed on the gate structure of the P-type active region 100P, it is beneficial to reduce the operating power consumption of the semiconductor digital cell.

[0124] Specifically, the cell areas of the first digital cell layout and the second digital cell layout are equal. Compared with the second digital cell layout, in the P-type active region 100P, the number of gate plug patterns 120 in the first digital cell layout is greater than the number of gate plug patterns 120 in the second digital cell layout. Consequently, the power consumption of the first type of digital cell is less than that of the second type of digital cell, thus satisfying the requirement that the power consumption of the first type of digital cell application scenario is less than that of the second type of digital cell application scenario.

[0125] In this embodiment, the total number of gate plug patterns 120 located in the N-type active region 100N and the P-type active region 100P is equal in the second digital cell layout and the first digital cell layout.

[0126] For digital units with the same circuit structure and identical transistor dimensions within the circuit structure, the required number of gate plugs is consistent. In other words, the total number of gate plug patterns 120 in the digital unit layout forming the same digital unit is consistent. In this embodiment, the total number of gate plug patterns 120 located in the N-type active region 100N and P-type active region 100P in the second digital unit layout is equal to the total number of gate plug patterns 120 located in the N-type active region 100N and P-type active region 100P in the first digital unit layout. Correspondingly, the number of gate plug patterns 120 located in the passive region 100U is also equal. This facilitates the formation of digital unit layouts with consistent areas, thereby improving the design flexibility of digital unit layouts while ensuring that the dimensions of digital unit layouts are relatively consistent, reducing the complexity of subsequent formation of digital units corresponding to the digital unit layout.

[0127] In this embodiment, the digital unit layout further includes: a contact hole layer, including a contact hole pattern; a first metal wire layer, including a first metal wire pattern; and a second metal wire layer, including a second metal wire pattern.

[0128] The contact hole pattern is used to form an interconnect plug, the first metal line pattern is used to form a first metal line, the second metal line pattern is used to form a second metal line, the interconnect plug is used to electrically interconnect the source / drain interconnect with the first metal line, or to electrically interconnect the first metal line with the second metal line, and the first metal line, the second metal line, and the interconnect plug are used to realize the back-end interconnect of the digital unit.

[0129] Accordingly, the present invention also provides a layout structure design system. Figure 6 This is a functional block diagram of an embodiment of the layout structure design system of the present invention.

[0130] In this embodiment, the layout structure design system 50 includes: an initial layout layer providing module 501, used to provide multiple initial layout layers for forming different digital units, each initial layout layer including an active region, the active region including N-type active regions and P-type active regions adjacent along a first direction, the initial layout layer also including multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction, the gate patterns spanning the N-type active regions and P-type active regions, the first direction being perpendicular to the second direction; and a pattern allocation module 502, used to allocate multiple gate plug patterns according to the digital units corresponding to each initial layout layer, forming multiple digital unit layouts of different types, the layout layer including a first digital unit. In both the first and second digital cell layouts, a plurality of gate plug patterns are located above the gate pattern, and the gate plug patterns are located at least in the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first and second digital cell layouts is not equal; the number of gate plug patterns in the N-type active regions of the first and second digital cell layouts is equal; the number of gate plug patterns in the P-type active regions of the first and second digital cell layouts is not equal; and the number of gate plug patterns in the P-type active regions of the first and second digital cell layouts is equal.

[0131] The initial layout layer provided by the layout layer provider module 501 is used as the base layout for digital unit layout design, and the resulting digital unit layout is used to form different digital units.

[0132] Digital cell layout is used to form digital cells. Digital cells include various basic units such as NAND gates, flip-flops, inverters, AND gates, registers, data selectors, and full adders. Each digital cell corresponds to multiple cell circuits of different sizes (W / L) and different drive capabilities.

[0133] Accordingly, in this embodiment, the types of digital units include NAND gates, AND gates, flip-flops, data selectors, or inverters.

[0134] In the process of multi-channel data transmission, a circuit that can select any one of the channels as needed is called a data selector, also known as a multiplexer or multiplexer switch.

[0135] An inverter is a circuit that can reverse the phase of an input signal by 180 degrees.

[0136] The layout of the digital unit corresponding to the data selector is more complex, while the layout of the digital unit corresponding to the inverter is simpler. However, the layout structure design method in this embodiment can be used to obtain data selectors or inverters that are suitable for more application scenarios.

[0137] The active region is the area where active devices are formed.

[0138] Depending on the doping type, active devices include N-type active devices and P-type active devices. Accordingly, in this embodiment, the active region includes N-type active regions and P-type active regions adjacent to each other along the first direction.

[0139] In this embodiment, the initial layer also includes a passive region located between adjacent N-type active regions and P-type active regions, and the gate pattern also spans the passive region.

[0140] The passive region is the area where passive devices are formed. Typically, the passive region is used to isolate adjacent active regions. Therefore, the passive region is located between adjacent N-type active regions and P-type active regions, and the gate pattern also spans the passive region.

[0141] Gate patterns are used to form gate structures, which are used to control the opening or closing of the device channel.

[0142] In this embodiment, the initial layer also includes fin patterns located in the active region, which extend along the second direction and are arranged in parallel along the first direction.

[0143] Fin patterns are used to form fins, which in turn provide channels for the device.

[0144] In this embodiment, the fin pattern is located below the gate pattern.

[0145] In semiconductor manufacturing, the gate structure spans the fins in its region and covers part of the top and sidewalls of the fins. Therefore, the gate pattern is orthogonal to the fin patterns in the active region. Specifically, when there are multiple fin patterns in the active region, one gate pattern is orthogonal to multiple fin patterns.

[0146] In this embodiment, COAG patterns can be designed in the active region, so that multiple fin patterns can be formed in both the N-type and P-type active regions, which greatly saves the unit area of ​​the digital unit layout.

[0147] As an example, both the N-type and P-type active regions include three fin patterns.

[0148] In this embodiment, the unit area of ​​each initial layer is equal, so that the unit area of ​​each subsequent digital unit layout is equal.

[0149] In this embodiment, the initial layer further includes: source-drain interconnect patterns located on both sides of the gate pattern, extending along a first direction and arranged parallel to each other along a second direction.

[0150] Source-drain interconnect patterns are used to form source-drain interconnects, which are used to bring out the electrical properties of the source-drain doped layers of the device.

[0151] In semiconductor manufacturing, source and drain doped layers are formed in the fins on both sides of the gate structure. Therefore, in this embodiment, the source and drain interconnect patterns are located on both sides of the gate pattern.

[0152] In this embodiment, the initial layer also includes: a gate cut-off pattern, which is orthogonal to a portion of the gate pattern.

[0153] The gate cut-off pattern is used to define the cut-off position of the gate structure and to form a gate isolation structure at the cut-off position. Thus, in practical applications, a gate cut-off pattern orthogonal to the gate pattern is formed at the position where the gate structure needs to be cut off.

[0154] In semiconductor manufacturing, the gate structure is formed first, and then the gate structure is cut off.

[0155] It should be noted that in this embodiment, the number of gate patterns in each initial layer is the same, and the number of fin patterns in each initial layer is the same. Accordingly, the unit area of ​​each initial layer is equal.

[0156] This embodiment also includes an application scenario determination module, used to determine the application scenario of the digital unit corresponding to each initial version layer.

[0157] Different digital units are used in different application scenarios (e.g., high-frequency scenarios or low-power scenarios), and different application scenarios will place different requirements on the performance of digital units. Accordingly, the application scenario is related to the type of digital unit.

[0158] As an example, in this embodiment, the digital unit includes a first type of digital unit and a second type of digital unit. The frequency of the application scenario of the first type of digital unit is greater than that of the application scenario of the second type of digital unit. According to the frequency requirements of the application scenario of the digital unit, the digital unit layout corresponding to the first type of digital unit and the second type of digital unit is designed subsequently.

[0159] As an example, in this embodiment, the digital unit includes a first type of digital unit and a second type of digital unit. The power consumption of the second type of digital unit application scenario is less than that of the first type of digital unit application scenario. According to the power consumption requirements of the digital unit application scenario, the digital unit layout corresponding to the first type of digital unit and the second type of digital unit is designed subsequently.

[0160] The pattern allocation module 502 is used to allocate multiple gate plug patterns according to the digital cells corresponding to each initial layout layer, forming multiple digital cell layouts of different types. The digital cell layout includes a first digital cell layout and a second digital cell layout. In each digital cell layout, multiple gate plug patterns are located above the gate pattern, and the gate plug patterns are at least located above the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are equal.

[0161] In this embodiment, the graphic allocation module 502 is also used to allocate multiple gate plug patterns to each initial layout layer according to the application scenario of the digital unit corresponding to each initial layout layer, so as to form multiple digital unit layouts of different types.

[0162] Gate plug patterns are used to form gate plugs, which are used to bring out the electrical properties of the gate structure.

[0163] In digital cells, when the cell areas are equal, the ratio of the number of gate plugs formed on the gate structure of the N-type active region to the number of gate plugs formed on the gate structure of the P-type active region will have a corresponding impact on the performance of the digital cell. Therefore, in this embodiment, when designing the digital cell layout, in the step of allocating multiple gate plug patterns to each initial layout layer, the number of gate plug patterns allocated to the N-type and P-type active regions in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital cell. Under the condition of satisfying the design rules, as many gate plug patterns as possible can be allocated in the N-type active region, or as many gate plug patterns as possible can be allocated in the P-type active region, forming a digital cell layout that meets the requirements of various application scenarios, thereby improving the flexibility of digital cell layout design.

[0164] In this embodiment, the gate plug pattern is also located above the gate pattern in the passive region.

[0165] In this embodiment, the gate plug pattern is located above the gate pattern in the active region. Correspondingly, when forming the digital cell corresponding to the digital cell layout, a COAG structure can be formed, saving the cell area of ​​the digital cell layout. At the same time, in order to make full use of the top space of the gate structure, the gate plug can also be formed on the gate structure in the passive region. Correspondingly, the gate plug pattern is also located above the gate pattern in the passive region.

[0166] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit include: the frequency of the first type of digital unit application scenario is greater than the frequency of the second type of digital unit application scenario.

[0167] Accordingly, the first digital cell layout is used to form the first type of digital cell, and the second digital cell layout is used to form the second type of digital cell. In the N-type active region, the number of gate plug patterns in the first digital cell layout is greater than the number of gate plug patterns in the second digital cell layout.

[0168] In actual semiconductor manufacturing processes, the different placement of the COAG structure on top of the gate structure does not affect the DC electrical parameters of the digital cell, such as the threshold voltage and saturation current. However, it does affect the capacitance and resistance of the digital cell. Specifically, due to the different doping types of the P-type and N-type active regions, when the COAG structure is formed in the N-type active region, the digital cell has a larger capacitance and a smaller resistance, resulting in a higher operating frequency and higher power consumption.

[0169] Therefore, in semiconductor digital cells, when the COAG structure is formed on the gate structure of the N-type active region, it is beneficial to improve the operating frequency of the digital cell.

[0170] Specifically, the cell areas of the first digital cell layout and the second digital cell layout are equal. Compared with the second digital cell layout, in the N-type active region, the number of gate plug patterns in the first digital cell layout is greater than the number of gate plug patterns in the second digital cell layout. Consequently, the operating frequency of the first type of digital cell is greater than the operating frequency of the second type of digital cell, thus satisfying the situation where the frequency of the first type of digital cell application scenario is greater than the frequency of the second type of digital cell application scenario.

[0171] As can be seen from the foregoing, in this embodiment, the application scenarios of the digital unit also include: the power consumption of the second type of digital unit application scenario is less than the power consumption of the first type of digital unit application scenario.

[0172] Accordingly, the first digital cell layout is used to form the first type of digital cell, and the second digital cell layout is used to form the second type of digital cell. In the P-type active region, the number of gate plug patterns in the second digital cell layout is greater than the number of gate plug patterns in the first digital cell layout.

[0173] In actual semiconductor processes, when the COAG structure is formed in the P-shaped active region, the digital cell has a smaller capacitance and a larger resistance, resulting in lower power consumption and a lower operating frequency.

[0174] Therefore, in a semiconductor digital cell, when the COAG structure is formed on the gate structure of the P-type active region, it is beneficial to reduce the operating power consumption of the semiconductor digital cell.

[0175] Specifically, the cell areas of the first digital cell layout and the second digital cell layout are equal. Compared with the second digital cell layout, in the P-type active region, the number of gate plug patterns in the first digital cell layout is greater than the number of gate plug patterns in the second digital cell layout. Consequently, the power consumption of the first type of digital cell is less than that of the second type of digital cell, thus satisfying the requirement that the power consumption of the first type of digital cell application scenario is less than that of the second type of digital cell application scenario.

[0176] In this embodiment, the total number of gate plug patterns located in the N-type active region and the P-type active region is equal in the second digital cell layout and the first digital cell layout.

[0177] For digital units with the same circuit structure and identical transistor dimensions, the required number of gate plugs is consistent. In other words, the total number of gate plug patterns in the digital unit layout forming the same digital unit is consistent. In this embodiment, the total number of gate plug patterns located in the N-type active region and P-type active region in the second digital unit layout is equal to the total number of gate plug patterns located in the N-type active region and P-type active region in the first digital unit layout. The number of gate plug patterns located in the passive region is also equal, which is beneficial for forming digital unit layouts with consistent areas. This improves the design flexibility of digital unit layouts while ensuring that the size of digital unit layouts is relatively consistent, reducing the complexity of forming the corresponding digital units in the subsequent digital unit layout.

[0178] In this embodiment, after assigning multiple gate plug patterns to each initial plate layer, the method further includes: assigning contact hole patterns, first metal line patterns, and second metal line patterns to each initial plate layer.

[0179] The contact hole pattern is used to form an interconnect plug, the first metal line pattern is used to form a first metal line, the second metal line pattern is used to form a second metal line, the interconnect plug is used to electrically interconnect the source / drain interconnect with the first metal line, or to electrically interconnect the first metal line with the second metal line, and the first metal line, the second metal line, and the interconnect plug are used to realize the back-end interconnect of the digital unit.

[0180] Accordingly, the present invention also provides a digital unit library, including the layout structure of the foregoing embodiments.

[0181] As can be seen from the foregoing embodiments, in digital cells, when the cell areas of digital cells are equal, the different ratios of the number of gate plugs formed on the gate structure of the N-type active region and the number of gate plugs formed on the gate structure of the P-type active region will have a corresponding impact on the performance of the digital cell. Therefore, in this embodiment, when designing the digital cell layout, in the step of allocating multiple gate plug patterns to each initial layout layer, the number of gate plug patterns allocated to the N-type active region and the P-type active region in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital cell. Under the condition of satisfying the design rules, as many gate plug patterns as possible can be allocated in the N-type active region, or as many gate plug patterns as possible can be allocated in the P-type active region, forming multiple digital cell layouts that meet the requirements of various application scenarios, thereby improving the flexibility of digital cell layout design and thus increasing the diversity of the digital cell library.

[0182] The diversity of digital cell libraries can effectively improve the efficiency of synthesis tools and automatic placement and routing tools, while also giving designers more freedom to optimize performance, area, power consumption and cost.

[0183] This invention also provides a device that can implement the layout structure design method provided in this invention through the above-described layout structure design method in the form of a loading program. An optional hardware structure of the terminal device provided in this invention can be as follows: Figure 7 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0184] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04. Communication interface 02 can be an interface of a communication module for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. Memory 03 may include high-speed RAM and may also include non-volatile memory (NVM), such as at least one disk storage device. Memory 03 stores one or more computer instructions, which are executed by processor 01 to implement the optical proximity correction method provided in this embodiment of the present invention.

[0185] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.

[0186] This invention also provides a storage medium storing one or more computer instructions, which are used to implement the layout structure design method provided in this invention.

[0187] In the layout structure design method provided by this invention, multiple gate plug patterns are allocated to each initial layout layer to form different digital unit layouts. The digital unit layout includes a first digital unit layout and a second digital unit layout. The layout of the gate plug patterns includes one or two of the following: the number of gate plug patterns in the N-type active region of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the P-type active region of the first digital unit layout and the second digital unit layout are not equal; in the digital unit, when the unit area of ​​the digital unit is equal, the gate plugs formed on the gate structure of the N-type active region and the gate plugs formed on the P-type active region are... The different ratios of gate plugs on the gate structure of the source region will have a corresponding impact on the performance of the digital cell. Therefore, in the embodiment of the present invention, when designing the digital cell layout, in the step of allocating multiple gate plug patterns to each initial layout layer, the number of gate plug patterns allocated to the N-type active region and the P-type active region in each initial layout layer can be adjusted according to the application scenario requirements of the corresponding digital cell. Under the condition of satisfying the design rules, as many gate plug patterns as possible can be allocated in the N-type active region, or as many gate plug patterns as possible can be allocated in the P-type active region, forming a digital cell layout that meets the requirements of various application scenarios, thereby improving the flexibility of the digital cell layout design.

[0188] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, the elements or features described are optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not expressly referenced to each other may be combined to form embodiments of the present invention, or may be included as new claims in amendments made after the filing of this application.

[0189] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in memory units and executed by a processor. The memory units are located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0190] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0191] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of designing a layout structure, characterized by, include: Provided are multiple initial layout layers for forming different digital units, each initial layout layer including an active region, the active region including an N-type active region and a P-type active region adjacent along a first direction, the initial layout layer also including a multiple gate patterns extending along the first direction and arranged parallel to each other along a second direction, the gate patterns spanning the N-type active region and the P-type active region, the first direction being perpendicular to the second direction; Multiple gate plug patterns are allocated according to the digital cells corresponding to each initial layout layer to form different digital cell layouts. The digital cell layout includes a first digital cell layout and a second digital cell layout. In each digital cell layout, multiple gate plug patterns are located above the gate pattern, and the gate plug patterns are at least located above the active region. The layout of the gate plug patterns includes one or more of the following: the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital cell layout and the second digital cell layout are equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital cell layout and the second digital cell layout are equal.

2. The design method of layout structure according to claim 1, wherein, In the step of providing multiple initial layer templates for forming different digital units, the unit area of ​​each initial layer template is equal.

3. The layout structure design method as described in claim 1 or 2, characterized in that, Before allocating multiple gate plug patterns according to the digital units corresponding to each of the initial version layers, the method further includes: determining the application scenario of the digital units corresponding to each of the initial version layers; Based on the application scenario of the digital unit corresponding to each initial version layer, multiple gate plug patterns are assigned to each initial version layer.

4. The layout structure design method as described in claim 3, characterized in that, In the step of providing multiple initial layout layers, the initial layout layers also include passive regions located between adjacent N-type active regions and P-type active regions, and the gate pattern also spans the passive regions; In the step of assigning multiple gate plug patterns to each of the initial layer, the gate plug patterns are also located above the gate patterns of the passive region.

5. The layout structure design method as described in claim 4, characterized in that, The digital unit includes a first type of digital unit and a second type of digital unit. In the step of determining the application scenario of the digital unit corresponding to each initial version layer, the frequency of the application scenario of the first type of digital unit is greater than the frequency of the application scenario of the second type of digital unit. In the step of assigning multiple gate plug patterns to each initial layout layer, the first digital cell layout is used to form a first type of digital cell, and the second digital cell layout is used to form a second type of digital cell. In the N-type active region, the number of gate plug patterns in the first digital cell layout is greater than the number of gate plug patterns in the second digital cell layout.

6. The layout structure design method as described in claim 4, characterized in that, The digital unit includes a first type of digital unit and a second type of digital unit. In the step of determining the application scenario of the digital unit corresponding to each initial version layer, the power consumption of the second type of digital unit application scenario is less than the power consumption of the first type of digital unit application scenario. In the step of assigning multiple gate plug patterns to each initial layout layer: the first digital cell layout is used to form a first type of digital cell, the second digital cell layout is used to form a second type of digital cell, and in the P-type active region, the number of gate plug patterns in the second digital cell layout is greater than the number of gate plug patterns in the first digital cell layout.

7. The layout structure design method as described in claim 5 or 6, characterized in that, In the second digital cell layout and the first digital cell layout, the total number of gate plug patterns located in the N-type active region and the P-type active region is equal.

8. The layout structure design method as described in claim 1, characterized in that, In the step of providing multiple initial layered templates for forming different digital units, the types of digital units include NAND gates, AND gates, flip-flops, data selectors, or inverters.

9. A layout structure, characterized in that, include: Multiple digital unit layouts for forming different digital units, including a first digital unit layout and a second digital unit layout, each of the digital unit layouts includes an active region, the active region including an N-type active region and a P-type active region adjacent along a first direction; The digital unit layout includes: A gate pattern layer, the gate pattern layer comprising a plurality of gate patterns extending along a first direction and arranged parallel to a second direction, the gate patterns spanning the N-type active region and the P-type active region, the first direction being perpendicular to the second direction; A gate plug pattern layer is located above the gate pattern layer. The gate plug pattern layer includes multiple gate plug patterns, which are located above the gate patterns and are located at least in the active region. Depending on the application scenario of the digital unit corresponding to each of the digital unit layouts, the layout of the gate plug pattern includes one or more of the following situations: the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are equal.

10. The layout structure as described in claim 9, characterized in that, Each digital unit layout has an equal unit area.

11. The layout structure as described in claim 10, characterized in that, The digital unit layout also includes passive regions located between adjacent N-type active regions and P-type active regions; In the gate plate layer, the gate pattern also spans the passive region; In the gate plug pattern layer, the gate plug pattern is also located above the gate pattern of the passive region.

12. The layout structure as described in claim 11, characterized in that, The first digital cell layout is used to form a first type of digital cell, and the second digital cell layout is used to form a second type of digital cell. The frequency of the application scenario of the first type of digital cell is greater than the frequency of the application scenario of the second type of digital cell. In the N-type active region, the number of gate plug patterns in the first digital cell layout is greater than the number of gate plug patterns in the second digital cell layout.

13. The layout structure as described in claim 11, characterized in that, The first digital cell layout is used to form a first type of digital cell, and the second digital cell layout is used to form a second type of digital cell. The power consumption of the second type of digital cell application scenario is less than the power consumption of the first type of digital cell application scenario. In the P-type active region, the number of gate plug patterns in the second digital cell layout is greater than the number of gate plug patterns in the first digital cell layout.

14. The layout structure as described in claim 12 or 13, characterized in that, In the second digital cell layout and the first digital cell layout, the total number of gate plug patterns located in the N-type active region and the P-type active region is equal.

15. The layout structure as described in claim 9, characterized in that, The types of digital units corresponding to the digital unit layout include NAND gates, AND gates, flip-flops, data selectors, or inverters.

16. A layout structure design system, characterized in that, include: An initial layout layer providing module is used to provide multiple initial layout layers for forming different digital units. Each initial layout layer includes an active region, which includes an N-type active region and a P-type active region adjacent to each other along a first direction. The initial layout layer also includes multiple gate patterns that extend along the first direction and are arranged in parallel along a second direction. The gate patterns span the N-type active region and the P-type active region. The first direction is perpendicular to the second direction. A pattern allocation module is used to allocate multiple gate plug patterns according to the digital units corresponding to each initial layout layer, forming multiple different digital unit layouts. The digital unit layout includes a first digital unit layout and a second digital unit layout. In each digital unit layout, multiple gate plug patterns are located above the gate pattern, and the gate plug patterns are at least located above the active region. The layout of the gate plug patterns includes one or two of the following: the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the N-type active regions of the first digital unit layout and the second digital unit layout are equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are not equal; the number of gate plug patterns in the P-type active regions of the first digital unit layout and the second digital unit layout are equal.

17. A digital unit library, characterized in that, Includes the layout structure as described in any one of claims 9-15.

18. A device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the layout structure design method as described in any one of claims 1-8.

19. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which are used to implement the layout structure design method as described in any one of claims 1-8.

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