Feedback circuit of voltage stabilizer and feedback control method suitable for voltage stabilizer

Abstract

The present application provides a feedback circuit of a voltage regulator and a feedback control method applicable to a voltage regulator, which can provide improved AVP performance. In one embodiment, the present application provides a feedback circuit of a voltage regulator, which can include: a first sensing circuit arranged to generate a first feedback signal for providing information of an inductor current of an inductor of the voltage regulator; a second sensing circuit arranged to generate a second feedback signal for providing information of an output voltage of the voltage regulator; a third sensing circuit arranged to generate a third feedback signal for providing information of a capacitor current of an output capacitor of the voltage regulator; and a processing circuit arranged to generate a control voltage signal according to the first feedback signal, the second feedback signal and the third feedback signal, and output the control voltage signal to a controller circuit of the voltage regulator for adjusting the output voltage of the voltage regulator.

Description

TECHNICAL FIELD

[0001] The present invention relates to voltage regulator design, and more particularly, to feedback circuit of voltage regulator and related feedback control method. BACKGROUND

[0002] In electronic devices, voltage regulators are used to provide stable power supply for electronic loads. Voltage regulators are usually designed to maintain the output voltage within a specified range. In some applications, the voltage regulator can support Adaptive Voltage Positioning (AVP) function. Therefore, in addition to the output voltage of the voltage regulator, the load current provided to the load can be considered in the feedback loop control. For example, the load can be a microprocessor. However, it can not be feasible to sense the load current. In order to obtain the load information, the inductor current is usually sensed and used as an approximation of the load current. In some cases, this approximation can fail and affect the performance of the output voltage regulation. Therefore, there is a need to provide innovative compensation design for voltage regulators with AVP. SUMMARY

[0003] The present invention provides feedback circuit of voltage regulator and feedback control method applicable to voltage regulator, which can provide improved AVP performance.

[0004] In one embodiment, the present invention provides feedback circuit of voltage regulator, which can include: a first sensing circuit arranged to generate a first feedback signal, the first feedback signal being used to provide information of an inductor current of an inductor of the voltage regulator; a second sensing circuit arranged to generate a second feedback signal, the second feedback signal being used to provide information of an output voltage of the voltage regulator; a third sensing circuit arranged to generate a third feedback signal, the third feedback signal being used to provide information of a capacitor current of an output capacitor of the voltage regulator; and a processing circuit arranged to generate a control voltage signal according to the first feedback signal, the second feedback signal and the third feedback signal, and output the control voltage signal to a controller circuit of the voltage regulator, for regulating the output voltage of the voltage regulator.

[0005] In one embodiment, the feedback control method for a voltage regulator provided by the present invention includes: generating a first feedback signal for providing information on the inductor current of an inductor of the voltage regulator; generating a second feedback signal for providing information on the output voltage of the voltage regulator; generating a third feedback signal for providing information on the capacitor current of an output capacitor of the voltage regulator; generating a control voltage signal based on the first feedback signal, the second feedback signal, and the third feedback signal; and outputting the control voltage signal to a controller circuit of the voltage regulator for adjusting the output voltage of the voltage regulator. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the feedback circuit of a regulator with adaptive voltage positioning (AVP) according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram of a voltage regulator with an AVP according to an embodiment of the present invention. Detailed Implementation

[0008] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but by differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." "Substantially" or "approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error. Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following description is a preferred mode for carrying out the invention and is intended to illustrate the spirit of the invention rather than to limit the scope of protection of the invention. The scope of protection of the invention shall be determined by the appended claims.

[0009] The following description represents the preferred embodiments of the present invention. These descriptions are intended to illustrate the general principles of the invention and not to limit it. The scope of protection of the invention should be determined based on the claims.

[0010] Figure 1A schematic diagram of a feedback circuit of a regulator with adaptive voltage positioning (AVP) according to an embodiment of the present application. The feedback circuit 100 comprises a first sensing circuit 102, a second sensing circuit 104, a third sensing circuit 106, and a processing circuit 108. The first sensing circuit 102 is arranged to generate a first feedback signal FB1 for providing information of an inductor current I L of an inductor L of a regulator (e.g. a switched- mode buck converter). The second sensing circuit 104 is arranged to generate a second feedback signal FB2 for providing information of an output voltage Vo of the regulator. The third sensing circuit 106 is arranged to generate a third feedback signal FB3 for providing information of a capacitor current Ic of an output capacitor Co of the regulator. The processing circuit 108 is arranged to generate a control voltage signal Vc from the first feedback signal FB1, the second feedback signal FB2, and the third feedback signal FB3, and to output the control voltage signal Vc to a controller circuit of the regulator for regulating the output voltage Vo of the regulator. In this embodiment, the third sensing circuit 106 acts as a compensation circuit to compensate for a deviation of the inductor current I L . As an example, the third sensing circuit 106 acts as the compensation circuit to compensate for a deviation of the inductor current I L caused by a Dynamic Voltage Scaling (DVS) event (e.g. a DVS up event or a DVS down event). The DVS up event is a change of the output voltage Vo from a current voltage setting to a next voltage setting, where the next voltage setting is higher than the current voltage setting. The DVS down event is a change of the output voltage Vo from a current voltage setting to a next voltage setting, where the next voltage setting is lower than the current voltage setting.

[0011] As shown in Figure 1 , an average inductor current ave(I L ) of the inductor L is equal to a sum of an average capacitor current ave(Ic) of the output capacitor Co and an average load current ave(Io) of the load 101 (i.e. ave(I L ) = ave(Io) + ave(Ic)). In a steady state, since ave(Ic) = 0, the average inductor current ave(I L is equal to the average load current ave(Io). The inductor current I L can be detected as an approximation of the load current Io. Therefore, the first sensing circuit 102 is arranged to provide information of the inductor current I Lsensing current signal of the information generates a first feedback signal FB1 and outputs the first feedback signal FB1 to the processing circuit 108. However, the above approximation fails in some cases. If the inaccurate load current approximation based on the inductor current I L is not compensated, the AVP performance of the regulator will be degraded.

[0012] For example, assume that the proposed compensation circuit (i.e., the third sensing circuit 106) is not enabled, a deviation of the output voltage Vo can be caused by a DVS up event. The DVS up event is to change the output voltage Vo from a current voltage setting to a next voltage setting, where the next voltage setting is higher than the current voltage setting. As a result, an increase of the inductor current I L is used to charge the output capacitor Co, so that the output voltage Vo can be correspondingly up. Specifically, the capacitor current Ic of the output capacitor Co is a non-zero charging current, and the extra charging current will be considered as an increase of the inductor current I L in the AVP loop. As a result, the output voltage Vo has an undesired offset AV = AI L x R i , where R i is the resistance value of the first sensing circuit 102. Specifically, since the inductor current I L cannot be approximated to the load current Io during the DVS up event, the output voltage Vo is wrongly adjusted to a lower voltage level by the AVP loop.

[0013] In another example, assume that the proposed compensation circuit (i.e., the third sensing circuit 106) is not enabled, a deviation of the output voltage Vo can be caused by a DVS down event. The DVS down event is to change the output voltage Vo from a current voltage setting to a next voltage setting, where the next voltage setting is lower than the current voltage setting. As a result, a decrease of the inductor current I L is used to discharge the output capacitor Co, so that the output voltage Vo can be correspondingly ramp down. Specifically, the capacitor current Ic of the output capacitor Co is a non-zero discharging current, and the extra discharging current will be considered as a decrease of the inductor current I L in the AVP loop. As a result, the output voltage Vo has an undesired offset AV = AI L x R i , where R i is the resistance value of the first sensing circuit 102. Specifically, since the inductor current I L cannot be approximated to the load current Io during the DVS down event, the output voltage Vo is wrongly adjusted to a higher voltage level by the AVP loop.

[0014] To address the above issues, the present application proposes to use a compensation circuit (i.e., the third sensing circuit 106) to generate a third feedback signal FB3 that provides information of the capacitor current Icof the output capacitor Co. The third feedback signal FB3 is derived from the output capacitor current sensing and can be used as a compensation signal to compensate the deviation of the inductor current I L from the target inductor current Itargetin response to a DVS event (e.g., a DVS up event or a DVS down event). Thus, the compensation circuit (i.e., the third sensing circuit 106) can be enabled to generate the third feedback signal FB3 in response to a DVS event. The increase of the first feedback signal FB1 during a DVS up event can be compensated by the third feedback signal FB3 obtained by sensing the non-zero charging current Icof the output capacitor Co. The decrease of the first feedback signal FB1 during a DVS down event can be compensated by the third feedback signal FB3 obtained by sensing the non-zero discharging current Icof the output capacitor Co.

[0015] Figure 2 A schematic diagram of a voltage regulator with AVP according to one embodiment of the present application. The voltage regulator 200 can be a switching buck converter with AVP. The voltage regulator 200 is capable of regulating an output voltage Vo provided to a load 101 according to an input voltage VIN. For example, the input voltage VIN can be a direct current (DC) voltage provided by a battery device, the load 101 can be a microprocessor, and the output voltage Vo can be a DC voltage provided to the microprocessor. Note that the load current Io provided to the load 101 can vary depending on different load conditions of the load 101. As shown in FIG. 1, the voltage regulator 200 can include a controller circuit 202, a power stage circuit 204, an inductor L, an output capacitor Co, and a feedback circuit 206. The feedback circuit 206 is designed to provide improved AVP performance for the voltage regulator 200 during DVS. Figure 2

[0016] The controller circuit 202 can include a comparator circuit (labeled as "CMP") 208 and a logic AND gate driver block 210. In this embodiment, a control voltage signal Vc fed into the comparator circuit 208 is output from the feedback circuit 206, which is part of the AVP loop for regulating the output voltage Vo. As shown in FIG. 2, the control voltage signal Vc can be a function of the output voltage Vo and the input voltage VIN. For example, the control voltage signal Vc can be a difference between the output voltage Vo and the input voltage VIN. Figure 2 ​As shown, the comparator circuit 208 has an inverting node (-) for receiving the ramp signal Vramp and a non-inverting node (+) for receiving the control voltage signal Vc. Thus, the comparator circuit 208 compares the control voltage signal Vc with the ramp signal Vramp, generating a comparison result for subsequent Pulse-Width Modulation (PWM) control. The logic and gate driver block 210 includes circuitry arranged to handle the PWM control of the power stage circuit 204 and / or additional functions. For example, the logic and gate driver block 210 can also support over-voltage protection, over-current protection, etc. With respect to the PWM control, the logic and gate driver block 210 can adjust the output voltage signal Vo delivered to the load 101 by controlling the PWM pulses applied to the power stage circuit 204. By way of example, the power stage circuit 204 can include high-side and low-side switches controlled by the PWM pulses generated by the logic and gate driver block 210.

[0017] The feedback circuit 206 is responsible for generating and outputting the control voltage signal Vc to the controller circuit 202 (specifically, the comparator circuit 208 of the controller circuit 202). In this embodiment, the feedback circuit 206 enables the AVP feature of the regulator 200, allowing the regulator 200 to position the output voltage Vo for light loads just below the maximum voltage of the tolerance window and to position the output voltage Vo for heavy loads just above the minimum voltage of the tolerance window. Thus, the regulator 200 with AVP can reduce the output capacitor Co (e.g., reduce the capacitance value of the output capacitor Co) and improve power efficiency.

[0018] In this embodiment, the implementation of the feedback circuit 206 follows the architecture of the feedback circuit 100 shown in Figure 1 FIG. 1. The feedback circuit 206 includes a first sensing circuit with a resistor R i to generate a first feedback signal FB1 (providing information of the inductor current I L ), a second sensing circuit to generate a second feedback signal FB2 (providing information of the output voltage Vo), a third sensing circuit to provide a third feedback signal FB3 (providing information of the capacitor current Ic), and a processing circuit (including a combine circuit 212 and an error amplifier circuit 214) to generate the control voltage signal Vc from the first feedback signal FB1, the second feedback signal FB2, and the third feedback signal FB3.

[0019] In this embodiment, the third sensing circuit includes a current-sensing resistor Rsen and a switching circuit SW. The current-sensing resistor Rsen is connected in series with the output capacitor Co (which has an equivalent series resistance ESR). The switching circuit SW is coupled between the combination circuit 212 and the current-sensing resistor Rsen and is turned on in response to a DVS event (labeled "DVS"). Specifically, during a DVS event (e.g., a DVS rise event or a DVS fall event), the third feedback signal FB3 received by the combination circuit 212 is set by the voltage at one end of the current-sensing resistor Rsen coupled to the switching circuit SW. Since the other end of the current-sensing resistor Rsen is coupled to ground (e.g., 0V), the voltage at one end of the current-sensing resistor Rsen is equal to the voltage across the current-sensing resistor Rsen. However, the use of a current-sensing resistor Rsen connected in series with ground is for illustrative purposes only, and the invention is not limited thereto. In practice, the feedback circuit 206 can employ any method capable of measuring or estimating the capacitor current Ic of the output capacitor Co. These alternative capacitor current sensing designs all fall within the scope of the invention.

[0020] Combination circuit 212 is used to combine the first feedback signal FB1, the second feedback signal FB2, and the third feedback signal FB3 to generate a feedback voltage signal V. FB In this embodiment, the combinational circuit 212 is arranged to add the first feedback signal FB1 to the second feedback signal FB2 for typical AVP control, and is also arranged to subtract the third feedback signal FB3 from the second feedback signal FB2 for proposed AVP compensation, thereby generating a feedback voltage signal V. FB Due to the deviation of the first feedback signal FB1 (reflecting the inductor current I during DVS), L The deviation can be compensated by the third feedback signal FB3, therefore the feedback voltage signal V FB It will not be affected by the inductor current I during DVS. L The effect of deviation. Therefore, during DVS events (e.g., DVS rise events or DVS fall events), the feedback voltage signal V FB Set by FB2+FB1–FB3. The error amplifier circuit 214 is arranged to receive the feedback voltage signal V. FB With reference voltage signal V REF (Set by DVS), and based on the feedback voltage signal V received at the inverting node (-) of the error amplifier circuit 214. FB The reference voltage signal V received at the non-inverting node (+) of the error amplifier circuit 214 REF The voltage difference between them generates a control voltage signal Vc. The third feedback signal FB3 prevents the feedback voltage signal Vc from being fed back. FB Inductor current I Lthe output voltage Vo can not suffer from an undesired shift ΔV = ΔI L × R i .

[0021] For a typical AVP implementation, the feedback voltage signal V FB is generated according to the output voltage and the sensed inductor current. One compensation design can apply a constant current predefined according to the nominal capacitance value of the output capacitor Co to compensate the feedback voltage signal V FB However, due to the variations, voltage drop, temperature coefficient, and other factors of the output capacitor Co, the actual capacitance value of the output capacitor Co can deviate from the nominal capacitance value. Therefore, the compensation design based on the constant current cannot cover all conditions of the output capacitor Co, and the output voltage Vo can still suffer from an undesired shift ΔV = ΔI L × R i during DVS. In contrast to the compensation design using a constant current to compensate the feedback voltage signal V FB during DVS, the proposed compensation design uses the sensing of the output capacitor current to compensate the feedback voltage signal V FB during DVS. Since the third feedback signal FB3 is obtained by sensing the capacitor current Icof the output capacitor Co, the third feedback signal FB3 provides real-time information of the capacitor current Icwithout considering the actual capacitance value of the output capacitor Co. Therefore, the third feedback signal FB3 can cover all conditions of the output capacitor Co, and minimize the undesired shift ΔV = ΔI L × R i .

[0022] Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application thereto, and any person skilled in the art, without departing from the spirit and scope of the present application, can make some changes and modifications. Therefore, the scope of protection of the present application should be defined by the appended claims.

Claims

1. A feedback circuit for a voltage regulator, characterized by comprising: a first sensing circuit arranged to generate a first feedback signal for providing information of an inductor current of an inductor of the voltage regulator; a second sensing circuit arranged to generate a second feedback signal for providing information of an output voltage of the voltage regulator; a third sensing circuit arranged to generate a third feedback signal for providing information of a capacitor current of an output capacitor of the voltage regulator; and a processing circuit arranged to generate a control voltage signal from the first feedback signal, the second feedback signal and the third feedback signal, and output the control voltage signal to a controller circuit of the voltage regulator for regulating the output voltage of the voltage regulator; wherein the processing circuit comprises: a combination circuit arranged to combine the first feedback signal, the second feedback signal and the third feedback signal which are sensed at the same time to generate a feedback voltage signal; and an error amplifier circuit arranged to receive the feedback voltage signal and a reference voltage signal, and generate the control voltage signal from a voltage difference between the feedback voltage signal and the reference voltage signal. The combination circuit is arranged to add the first feedback signal to the second feedback signal and subtract the third feedback signal from the added result to generate the feedback voltage signal.

2. The feedback circuit of claim 1, wherein, The third sensing circuit is arranged to generate the third feedback signal in response to a dynamic voltage scaling event.

3. The feedback circuit of claim 1, wherein, The third sensing circuit comprises:

4. The feedback circuit of claim 1, wherein, a current sense resistor connected in series with the output capacitor. The third sensing circuit further comprises:

5. The feedback circuit of claim 4, wherein, a switch circuit coupled between the processing circuit and the current sense resistor, wherein the switch circuit is turned on in response to a dynamic voltage scaling event. comprising:

6. A feedback control method suitable for use in a voltage regulator, characterized by, generating a first feedback signal for providing information of an inductor current of an inductor of the voltage regulator; generating a second feedback signal for providing information of an output voltage of the voltage regulator; generating a third feedback signal for providing information of a capacitor current of an output capacitor of the voltage regulator; generating a control voltage signal from the first feedback signal, the second feedback signal and the third feedback signal; and outputting the control voltage signal to a controller circuit of the voltage regulator for regulating the output voltage of the voltage regulator; wherein generating a control voltage signal from the first feedback signal, the second feedback signal and the third feedback signal comprises: combining the first feedback signal, the second feedback signal and the third feedback signal which are sensed at the same time to generate a feedback voltage signal; and generating the control voltage signal from a voltage difference between the feedback voltage signal and a reference voltage signal. combining the first feedback signal, the second feedback signal and the third feedback signal which are sensed at the same time to generate a feedback voltage signal comprises: adding the first feedback signal to the second feedback signal and subtracting the third feedback signal from the added result to generate the feedback voltage signal.

7. The feedback control method according to claim 6, wherein generating a third feedback signal comprises: generating the third feedback signal in response to a dynamic voltage scaling event.

8. The feedback control method according to claim 6, wherein generating a third feedback signal comprises: ​ 9. The feedback control method according to claim 6, wherein ​ The third feedback signal is set by a current sense resistor in series with the output capacitor.

10. The feedback control method according to claim 9, wherein Generating the third feedback signal further comprises: turning on a switching circuit in response to a dynamic voltage scaling event, wherein the third feedback signal is set by a voltage coupled to one end of the current sense resistor of the switching circuit.

Images