A broadband radio frequency amplifier impedance matching network topology design method

Abstract

This invention discloses an impedance matching network topology design method for a broadband RF amplifier. Starting with the equivalent model of a transistor, it utilizes the Z-axis obtained from load-pull simulation at P1dB. opt Extract the actual required R opt Parallel parasitic capacitance C out The numerical value, and thus the thorny frequency-varying Z that must be addressed within the framework of existing technical solutions. opt The matching problem is simplified to impedance transformation between single points, reducing implementation difficulty and eliminating tedious iterative optimization processes, thus improving design efficiency. Furthermore, this invention provides a complete compensation network design process, which can effectively reduce parallel parasitic capacitance C within any specified bandwidth and in the desired implementation form. out For the terminal impedance Z load To a constant optimal intrinsic load resistance R opt The effects of the transformation and the parameters of the undetermined components all have clear derivations to facilitate rapid solutions.

Description

Technical Field

[0001] This invention relates to the technical field of broadband radio frequency amplifier design, and more particularly to an impedance matching network topology design method for broadband radio frequency amplifiers. Background Technology

[0002] Effective, flexible, and cost-effective spectrum coverage solutions are one of the main evolutionary directions in the industry. Due to the rapid expansion and network deployment of mobile and wireless communication systems, current communication networks are, and will continue to be, in a state of multi-mode and multi-standard coexistence. Furthermore, to achieve the goals of high capacity, high speed, and low latency, the next generation of 5G systems will inevitably extend from Sub-6GHz to millimeter-wave bands that provide greater bandwidth resources. Therefore, the research and development and promotion of broadband RF front-end modules that support multiple modes and frequencies has become inevitable. The core components involved are power amplifiers (PAs) and low-noise amplifiers (LNAs) used to amplify signals in the transmit and receive channels.

[0003] The essence of broadband RF amplifier design lies in constructing a broadband impedance matching network to achieve a series of optimal fundamental load impedances Z required to modulate the transistor within a specified continuous wide bandwidth. opt This allows the transistor to operate in the desired state at different frequencies. Generally, Z at discrete frequencies... opt This was determined through load-pull simulation of the transistors, and the obtained Z values ​​were used to determine the Z values. opt The optimal impedance trajectory formed by connecting the components in ascending frequency order is the impedance matching effect that the matching network should strive to achieve.

[0004] The mainstream matching design approach is to first match a series of Z... opt Choose one from the middle options or according to Z opt The distribution is redefined to determine a central impedance Z. ctr This approximates the performance balance matching point within the broadband. Let the selected impedance be expressed as R + jX, then its quality factor Q = X / R. If this Q is less than the value calculated by the formula Q... max =f0 / BW to calculate the upper limit Q value of the undetermined matching network, i.e., Q max Where f0 is the center frequency of the design frequency band BW, the entire design frequency band BW can be covered by a multi-stage cascaded matching circuit. Then, at the implementation level, the Smith chart can be used to achieve this at frequencies less than Q. max Within the line area, the network topology is determined in a visually intuitive way, completing the process from terminal Z. load For an accurate impedance transformation from (e.g., a standard system load of 50Ω) to R+jX, see the example. Figure 1 .

[0005] Existing technical solutions are suitable for RF amplifier applications with low bandwidth requirements, i.e., Z opt It has good applicability in cases with low discreteness. However, for the increasingly popular high-bandwidth communication systems that are compatible with multiple frequency bands and multiple standards, amplifier design will face challenges at low and high sideband frequencies. opt The problem of long distances between components highlights the limitations of compromise impedance matching strategies, as this inevitably sacrifices performance in a certain frequency domain within the band. Although this deficiency can be alleviated to some extent by repeatedly tuning, optimizing, or adding more matching components to the initially constructed matching structure using CAD software, this approach relies on past practical experience and is not universally applicable. It also cannot quickly and cost-effectively achieve the expected broadband flat response.

[0006] In fact, Z opt The frequency-dependent discreteness is mainly caused by the transistor's output parasitic capacitance C. out Function. Existing publicly available literature has indicated that the equivalent output impedance model of a transistor can be established as a parallel R... opt C out The network form, but the equivalent model contains the optimal intrinsic load resistance R of the active device. opt Often, based on the classic load line theory, which relies on many ideal assumptions and neglects to consider the bias level, the resulting R... opt It will be relatively large. Device parasitic parameter C out This is then extracted using small-signal simulation or actual measurement methods; however, C out It is a nonlinear quantity and has different values ​​under different excitation conditions; on the other hand, real-world base stations and other equipment are often in a large signal output state, so the traditional small signal parameter extraction method will produce certain errors in amplifier design. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for designing the impedance matching network topology of a broadband radio frequency amplifier.

[0008] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0009] A method for designing the impedance matching network topology of a broadband RF amplifier includes:

[0010] A series of optimal fundamental load impedances Z over the broadband will be obtained based on load-pull simulation. opt Equivalent to parallel R opt C out Network model;

[0011] Based on parallel R opt C outThe network model is based on the optimal fundamental load impedance Z obtained from load-pull simulation at the 1dB gain compression point. opt Extract the optimal intrinsic load resistance R that is actually required. opt Parallel parasitic capacitance C out ;

[0012] Design a compensation network to reduce the parallel parasitic capacitance C. out The impact on impedance matching changes the target of broadband impedance matching from following the optimal fundamental load impedance Z that varies with frequency. opt The trajectory is simplified to the self-terminating impedance Z load To a constant optimal intrinsic load resistance R opt The impedance transformation between single points is obtained, thus enabling the determination of the impedance matching network topology using the Smith chart trajectory method.

[0013] Furthermore, based on the optimal fundamental load impedance Z opt Extract the optimal intrinsic load resistance R that is actually required. opt Parallel parasitic capacitance C out ,include:

[0014] Z from the center frequency point f0 opt The optimal intrinsic load resistance R required by the transistor in the P1dB state is derived by reverse derivation. opt Parasitic capacitance C in parallel with itself out The formula is as follows:

[0015]

[0016]

[0017] In the above formula, Re() is the function for taking the real part, and Im() is the function for taking the imaginary part. To obtain Z opt . conjugate.

[0018] Furthermore, a compensation network is designed, including:

[0019] A1. Obtain the transmission matrix of the compensation network;

[0020] A2. Find the solution of the transmission matrix when the signal travels from the compensation network to the matching network without loss;

[0021] A3. Obtain the network N to be designed by solving the transfer matrix. s The design parameters are determined to obtain the compensation network.

[0022] Furthermore, obtaining the transmission matrix of the compensation network includes:

[0023] According to the principle of conjugate matching, the compensation network has symmetric properties. Based on the topology of the schematic diagram, the transfer matrix of the compensation network can then be obtained.

[0024]

[0025] in, Parallel parasitic capacitance C out The transfer matrix, where j represents the imaginary number and ω is the angular frequency. For the network N to be designed s The transmission matrix, where A1, B1, and C1 are design parameters. Let be the transmission matrix of the jb parallel elements, and b be the susceptance.

[0026] Furthermore, when the signal reaches the matching network without loss from the compensation network, Z out =Z mn =R opt Z out To compensate for the impedance obtained from the network, terminal Z load R is the impedance after transformation by the matching network. opt To compensate for the optimal intrinsic load resistance of the equivalent double-ended network connection, the following relationship holds:

[0027]

[0028]

[0029] Γ out This is the reflection coefficient.

[0030] Furthermore, the conditions for the validity of a relation include:

[0031] If and only if the constraint conditions B = C = 0 or are satisfied, When, the equation Established.

[0032] Furthermore, the susceptance b of the parallel element jb is numerically equal to the angular frequency ω and the parallel parasitic capacitance C. out The product of, i.e., b = ωC out Thus, we can summarize as follows:

[0033] A = A1 + jB1b

[0034] B = B1

[0035] C = j2A1b - B1b 2 +C1.

[0036] Furthermore, the network N to be designed is obtained by solving the transfer matrix. s When designing the parameters, given A, B, and C, the constraints B = C = 0 and... They are equivalent to: B1 = j2A1b - B1b 2 +C1=0、 Thus, the network N to be designed is obtained. s Design parameters.

[0037] Compared with existing technologies, the principles and advantages of this solution are as follows:

[0038] This approach offers a different broadband design strategy, starting with the equivalent model of the transistor and using Z-axis values ​​obtained from load-pull simulations at the 1dB gain compression point (i.e., the boundary between linear and nonlinearity). opt Extract the actual required R opt Parallel parasitic capacitance C out The numerical value, and thus the thorny frequency-varying Z that must be addressed within the framework of existing technical solutions. opt The matching problem is simplified to impedance transformation between single points, which reduces the implementation difficulty and eliminates the tedious iterative optimization process, thus improving design efficiency.

[0039] The implementation of this strategy requires proper handling of the parallel parasitic capacitance C. out Therefore, this solution provides a complete design process for the compensation network, which can effectively reduce the parallel parasitic capacitance C within any specified bandwidth and in the required implementation form. out For the terminal impedance Z load To a constant optimal intrinsic load resistance R opt The effects of the transformation and the parameters of the undetermined components all have clear derivations to facilitate rapid solutions. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the services required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 Using the Smith chart to demonstrate existing technologies in applications smaller than Q max A diagram showing the matching network topology within the area defined by the line;

[0042] Figure 2 A schematic diagram of the die output circuit with compensation network;

[0043] Figure 3 A schematic diagram of a lumped low-pass compensation network;

[0044] Figure 4 This is a schematic diagram of a distributed low-pass compensation network;

[0045] Figure 5 The reflection coefficient Γ of lumped low-pass compensation network and distributed low-pass compensation network out Comparison chart;

[0046] Figure 6 S is the forward transmission coefficient between the two ports of the lumped low-pass compensation network and the distributed low-pass compensation network. 21 Comparison chart;

[0047] Figure 7 A schematic diagram of a lumped bandpass compensation network;

[0048] Figure 8 The reflection coefficient Γ of the lumped bandpass compensation network out A schematic diagram;

[0049] Figure 9 S is the forward transmission coefficient of the lumped bandpass compensation network. 21 A schematic diagram. Detailed Implementation

[0050] The present invention will be further described below with reference to specific embodiments:

[0051] The impedance matching network topology design method for a broadband RF amplifier described in this embodiment includes the following steps:

[0052] S1. Based on load-pull simulation, a series of optimal fundamental load impedances Z within the broadband will be obtained. opt Equivalent to parallel R opt C out Network model;

[0053] S2, Based on parallel R opt C out The network model is based on the optimal fundamental load impedance Z obtained from load-pull simulation at the 1dB gain compression point. opt Extract the optimal intrinsic load resistance R that is actually required. opt Parallel parasitic capacitance C out The process is as follows:

[0054] Z from the center frequency point f0 opt The optimal intrinsic load resistance R required by the transistor in the P1dB state is derived by reverse derivation. opt Parasitic capacitance C in parallel with itself out The formula is as follows:

[0055]

[0056]

[0057] In the above formula, Re() is the function for taking the real part, and Im() is the function for taking the imaginary part. To obtain Z opt . conjugate.

[0058] S3. Design a compensation network to reduce the parallel parasitic capacitance C. out The impact on impedance matching changes the target of broadband impedance matching from following the optimal fundamental load impedance Z that varies with frequency. opt The trajectory is simplified to the self-terminating impedance Z load To a constant optimal intrinsic load resistance R opt The impedance transformation between single points allows the impedance matching network topology to be determined using the Smith chart trajectory method (the Smith chart can only achieve transformation between two fixed impedances; traditional methods face transformations from a single point to a series of frequency-varying impedances, i.e., from a single point to multiple points). This invention compensates for the parallel parasitic capacitance C. out Broadband matching is simplified to one-to-one, so the entire design can be completed using the simplest and most intuitive pie chart method.

[0059] This step uses a field-effect transistor (FET) as a typical device for explanation, and the die output circuit with compensation network is shown in the diagram. Figure 2 The output section of the FET itself consists of an ideal voltage-controlled current source VCCS and a parallel parasitic capacitance C. out Parallel approximation; the compensation network with transmission matrix components A, B, C, and D absorbs C. out Let Z be the impedance obtained from the VCCS plane looking towards the compensation network. out The corresponding reflection coefficient is denoted as Γ. out ; Termination impedance Z load The impedance after transformation by the matching network is Z. mn When the compensation network has the same equivalent load R connected at both ends. opt To ensure maximum energy transfer between ports, the compensation network must possess symmetry (A=D) according to the conjugate matching principle. Therefore, the susceptance b of the parallel element jb is numerically equal to the angular frequency ω and C. out The product of the two networks, N, is to be designed. s It must also be symmetrical, and accordingly, its four parameters for the transfer matrix are defined as A1, B1, C1, and A1, respectively. If a parasitic capacitance C is connected in parallel... out The effects are perfectly compensated, allowing the RF amplified signal to be transmitted from one end of the VCCS to the input side of the matching network without any mismatch loss, while the transistor can see the required R. opt That is, Z out =Z mn =R opt When, the following relationship holds:

[0060]

[0061]

[0062] Equation (5) holds if and only if constraints (7) or (8) are satisfied.

[0063] R = C = 0 (7)

[0064]

[0065] In summary, the transmission matrix of the compensation network can be specifically expressed as:

[0066]

[0067] Given b = ωC out After sorting, we get:

[0068] A = A1 + jB1b

[0069] B = B1

[0070] C = j2A1b - B1b 2 +C1 (10)

[0071] Constraints (7) and (8) are further equivalent to:

[0072] B1=j2A1b-B1b 2 +C1=0 (11)

[0073]

[0074] Thus, the network N to be designed is obtained. s Design parameters.

[0075] The following are three examples, all based on R. opt and C out The examples provided are 26Ω and 0.27pF respectively, so that those skilled in the art can better understand the present invention and make reasonable use and extensions.

[0076] 1) Lumped low-pass compensation network, N s It is a series inductor;

[0077] When the simplest series inductor L is selected s To achieve N s ,like Figure 3 As shown, we have:

[0078] A1 = 1

[0079] B1=jωL s

[0080] C1 = 0 (13)

[0081] Substituting the data from equation (13) into constraints (11) and (12), and simplifying, we obtain the following result:

[0082]

[0083]

[0084] Obviously, equation (14) holds when ω = 0. In fact, at the DC point, the parallel parasitic capacitance C out This is equivalent to an open circuit without introducing any disturbance. Another compensation frequency point is defined, for example, 32GHz. The series inductance L can be calculated according to analytical formula (15). s The pH is 122.

[0085] 2) Distributed low-pass compensation network, N s It is a series transmission line;

[0086] When the frequency rises to the millimeter-wave band, lumped inductors are no longer suitable for implementation and must be replaced by transmission lines. Corresponding to Case 1), N s Replace it with a segment of characteristic impedance Z 01 A transmission line with an electrical length of θ1 at angular frequency ω; additionally, the equivalent parallel parasitic capacitance C. out The symmetrical parallel elements were also changed to have a characteristic impedance of Z. 02 An open-circuit transmission line with an electrical length of θ2 at angular frequency ω can be used as an approximation, such as... Figure 4 As shown, at this time:

[0087]

[0088]

[0089] Substituting the data from equation (17) into constraints (11) and (12), and simplifying, we obtain the following result:

[0090]

[0091]

[0092] Since θ1 can be further expressed as equation (20), where v p Let l1 be the phase velocity and l1 be the physical length of the transmission line. Combining equation (16), we know that relation (18) holds when ω = 0.

[0093]

[0094] In addition, to ensure the design of the network N sFor the feasibility of this, the denominator of equation (19) must be positive, therefore the selected Z... 01 It shall not be less than Z as given in constraint (21) 01,min .

[0095]

[0096] Similarly, another compensation frequency point is defined, here also for example 32GHz, at which point Z 01,min =15Ω; Assuming Z is chosen 01 =Z 02 =50Ω. According to the analytical formulas (16) and (19), θ1 and θ2 can be calculated to be 28.3° and 69.8° respectively.

[0097] The reflection coefficient Γ of cases 1) and 2) out and the forward transmission coefficient S between the two ports 21 The situations are shown separately. Figure 5 and Figure 6 This clearly demonstrates that the proposed compensation network can reduce the parallel parasitic capacitance C across the entire low bandwidth frequency range from DC to a specified 32 GHz. out The impact; and as designed, achieving conjugate matching at 0 and 32 GHz to maximize energy transfer (Γ) out <<0,S 21 =0), these two frequencies are also known as the perfect compensation point.

[0098] It should be mentioned that, to further expand the compensation bandwidth or enhance the compensation effect, the network N to be designed needs to be further improved. s The topology can be made more complex as needed, such as a 3-element T-type LCL network. Due to the symmetric structure, the number of elements can only be a positive odd number n, so (n+3) / 2 perfect compensation points are introduced. Therefore, in addition to the zero-frequency point that satisfies constraint (11), (n+1) / 2 more perfect compensation points can be defined and substituted into constraint (12), that is, (n+1) / 2 nonlinear equations can be established, and then (n+1) / 2 undetermined element parameters can be obtained, thus completing the design of the network N. s The design.

[0099] 3) Centralized bandpass compensation network

[0100] Based on the aforementioned low-pass compensation network design method and combined with filter theory, a band-pass compensation network can be obtained. A brief explanation is given using a bandwidth of 22-32 GHz as an example. The band-pass network originates from the low-pass prototype, by replacing the series and parallel components with a series and parallel LC resonant network that resonates at an angular frequency ω0, where ω0 is the geometric mean of the low and high side frequencies ω1 and ω2 of the design bandwidth.

[0101]

[0102] According to filter theory, the identity transformation between low-pass and band-pass networks should satisfy the relationship (23), where ω c It is the corner frequency of the low-pass prototype network.

[0103] ω c L=(ω2-ω1)L (23)

[0104] In other words, designing a bandpass compensation network for 22-32 GHz requires first obtaining a low-pass compensation network for DC-10 GHz, and then converting it to a bandpass type via resonance, i.e., according to calculation formula (23). The network topology and component parameters are shown in... Figure 7 The corresponding frequency response characteristics are determined by Figure 8 , 9 Provided.

[0105] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for designing the impedance matching network topology of a broadband radio frequency amplifier, characterized in that, Comprise: based on a series of optimal fundamental load impedances in a wide band are obtained by simulation equivalent to parallel network model; Based on parallel Network model, based on 1 dB gain compression point Optimal fundamental load impedance obtained from simulation Extracting the optimal intrinsic load resistance actually needed With parallel parasitic capacitance ; Designing compensation networks to reduce parallel parasitic capacitance The impact on impedance matching is such that the goal of broadband impedance matching is to follow the frequency-dependent optimal fundamental load impedance Trajectories are reduced to self-termination impedance to a constant optimal intrinsic load resistance Single-point impedance transformation, so that the impedance matching network topology can be obtained by Smith chart trajectory method; Design to compensate network, comprising: A1, obtain the transmission matrix of compensation network; A2, to obtain the solution of transmission matrix when signal losslessly reaches matching network from compensation network; A3. Solving the design parameters of the network to be designed by the solution of the transmission matrix, thereby obtaining the compensation network. A3. Solving the design parameters of the network to be designed by the solution of the transmission matrix, thereby obtaining the compensation network. Obtain the transmission matrix of compensation network, comprising: From the conjugate matching principle, the compensation network has the symmetry property, and then the transmission matrix of the compensation network is obtained according to the topology of the schematic diagram: ； wherein is the transmission matrix of the parallel parasitic capacitance , represents the imaginary unit, is the angular frequency, is the transmission matrix of the network to be designed, , are design parameters, is the transmission matrix of the series element, is the transmission matrix of the parallel element, is the susceptance; When the signal reaches the matching network from the compensation network without loss, , The terminal impedance for the compensation network, The impedance transformed by the matching network, The optimal intrinsic load resistance of the two-terminal equivalent load of the compensation network has the following relationship: ； ； is the reflection coefficient; Parallel element of the parallel element numerically equal to the angular frequency of the parallel element of the parallel element , so that we have: 。 2. The method of claim 1, wherein the topology of the impedance matching network of the wideband radio frequency amplifier is designed by, According to the optimal fundamental load impedance Extracting the optimal intrinsic load resistance actually needed With parallel parasitic capacitance , comprising: from the center frequency The optimal intrinsic load resistance required by the transistor at P1dB state is derived by back-calculation and its own parallel parasitic capacitance , as follows:​ ； ； In the above formula, To take the real part of the function, To take the imaginary part of the function, To obtain . conjugate.

3. The method of claim 1, wherein the topology of the impedance matching network of the wideband radio frequency power amplifier is designed by, The establishment condition of relational expression includes: The equality holds if and only if the constraint or is satisfied.

4. The method of claim 1, wherein, The network to be designed is obtained by solving the transfer matrix. When determining the design parameters, in order to obtain In this case, the constraints and They are respectively equivalent to: , Thus, the network to be designed is obtained. Design parameters.

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