Pixel circuit, analog-to-digital converter and infrared imager based on image processing algorithm

Abstract

The present invention provides a pixel circuit based on an image processing algorithm, an analog-to-digital converter with image processing, and an infrared imager, and relates to the field of integrated circuits. The detector is used to sample each pixel, obtain the pixel current corresponding to each pixel and output it to the operation unit; the operation unit is used to operate the pixel current using the image processing algorithm, obtain the signal current and output it to the analog front end; the analog front end is used to amplify and filter the signal current, obtain the front end current and output it to the integration unit; the integration unit is used to generate an integrated voltage according to the front end current; wherein the pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels. The present invention adds an operation unit to the pixel circuit to realize intelligent image processing at the pixel level, and no longer needs to be output to a digital processing chip outside the component for processing, which greatly reduces the data throughput requirements and well realizes the improvement of infrared imaging performance.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a pixel circuit based on an image processing algorithm, an analog-to-digital converter with image processing, and an infrared imager. Background Art

[0002] In the past few years, infrared imaging has been applied to a wide range of fields, such as biomedicine, space exploration, firefighting, etc. As the core of infrared imaging systems, the design of infrared focal plane circuits and ADCs in circuits has attracted more and more attention.

[0003] As the application of cooled infrared components and intelligent image processing algorithms becomes more widespread, the combination of intelligent image processing algorithms and cooled infrared components is imminent. It is particularly important to implement intelligent image processing algorithms in cooled infrared imaging.

[0004] The current method to achieve the above goal is to output the cooled infrared imaging information to a digital processing chip outside the component for processing. However, this processing method places too high a data throughput requirement on the cooled infrared component and does not allow for a better improvement in infrared imaging performance. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a pixel circuit based on an image processing algorithm, an analog-to-digital converter with image processing, and an infrared imager that solve the above problems or partially solve the above problems.

[0006] A first aspect of an embodiment of the present invention provides a pixel circuit based on an image processing algorithm, the pixel circuit comprising: a detector, a computing unit, an analog front end and an integration unit;

[0007] The detector is connected to the operation unit, and the detector is used to sample each pixel, obtain a pixel current corresponding to each pixel, and output the pixel current to the operation unit;

[0008] The operation unit is connected to the analog front end, and the operation unit is used to operate the pixel current using an image processing algorithm to obtain a signal current and output it to the analog front end;

[0009] The analog front end is connected to the integration unit, and the analog front end is used to amplify and filter the signal current to obtain the front end current and output it to the integration unit;

[0010] The integration unit is used to generate an integration voltage according to the front-end current;

[0011] The pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels, and for any pixel:

[0012] The signal current obtained by the operation unit in the pixel circuit corresponding to any pixel is added with the signal current obtained by the operation units in the pixel circuits corresponding to the surrounding pixels, and then output to the analog front end in the pixel circuit;

[0013] The computing unit in the pixel circuit corresponding to any pixel uses an image processing algorithm to calculate the pixel current within a target time. The target time is obtained based on: according to the size of the convolution kernel in the image processing algorithm, one frame time is divided into multiple parts, each time part is a target time, and the number of parts of one frame time is equal to the size of the convolution kernel.

[0014] Optionally, the operation unit includes: a current mirror structure and a plurality of switch bridge arm structures;

[0015] Each switch bridge arm structure includes: two MOS tubes and two switches, wherein the two MOS tubes are connected via two switches connected in series.

[0016] Optionally, the number of the plurality of switch bridge arm structures is determined by a coefficient of a single pixel, and the coefficient is determined by a size of the convolution kernel.

[0017] Optionally, when the size of the convolution kernel is 3×3, the coefficient of the single pixel is ±1, ±2, ±4 and 0, then the current mirror structure includes: a first MOS tube, a second MOS tube; the multiple switch bridge arm structures include: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a plurality of switches;

[0018] The first end of the first MOS tube, the first end of the second MOS tube, the first end of the third MOS tube, and the first end of the fourth MOS tube all receive the pixel current;

[0019] The second end of the first MOS tube is connected to the second end of the second MOS tube, the second end of the third MOS tube, the second end of the fourth MOS tube, and the second end of the fifth MOS tube respectively, and the second end of the first MOS tube is connected to its third end and grounded;

[0020] The third end of the second MOS tube is connected to the first end and the second end of the sixth MOS tube, the second end of the seventh MOS tube, the second end of the eighth MOS tube, and the second end of the ninth MOS tube respectively;

[0021] The third end of the sixth MOS tube, the third end of the seventh MOS tube, the third end of the eighth MOS tube, and the third end of the ninth MOS tube are all grounded;

[0022] The first end of the fifth MOS tube receives twice the pixel current;

[0023] The third end of the third MOS and the first end of the seventh MOS, the third end of the fourth MOS and the first end of the eighth MOS, and the third end of the fifth MOS and the first end of the ninth MOS are all connected through two series switches, wherein the connection between the two series switches outputs the signal current.

[0024] Optionally, the on and off of the multiple switches are determined by the coefficients of the corresponding positions of the convolution kernel.

[0025] Optionally, the signal current I obtained by the operation unit in the pixel circuit corresponding to any pixel INT for:

[0026] I INT = k × I DET

[0027] In the above formula, k represents the coefficient, I DET represents the pixel current.

[0028] Optionally, the integration unit includes: a sampling capacitor;

[0029] The front-end current corresponding to a single pixel is integrated on the sampling capacitor within a target time corresponding to the single pixel to obtain an integrated voltage corresponding to the single pixel;

[0030] All pixels corresponding to the convolution kernel size of one frame time obtain their own integrated voltage.

[0031] Optionally, the integral voltage V generated by the integral unit in one frame time is INT for:

[0032]

[0033] In the above formula, t INT represents a fixed time, n represents the convolution kernel size, j represents the number of pixels, k represents the coefficient, I DET represents the pixel current, C INT Indicates the size of the integrating capacitor.

[0034] A second aspect of an embodiment of the present invention provides an analog-to-digital converter with image processing, wherein the analog-to-digital converter with image processing includes a pixel circuit based on an image processing algorithm as described in any one of the first aspects.

[0035] A third aspect of an embodiment of the present invention provides an infrared imager, comprising: a pixel circuit based on an image processing algorithm as described in any one of the first aspects.

[0036] The pixel circuit based on the image processing algorithm provided by the present invention comprises the following steps: the detector samples each pixel, obtains the pixel current corresponding to each pixel and outputs it to the operation unit; the operation unit operates the pixel current using the image processing algorithm, obtains the signal current and outputs it to the analog front end; the analog front end amplifies and filters the signal current, obtains the front end current and outputs it to the integration unit; the integration unit generates an integration voltage according to the front end current.

[0037] The pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels. For any pixel: the signal current obtained by the operation unit in the pixel circuit corresponding to any pixel is added with the signal current obtained by the operation unit in the pixel circuit corresponding to the surrounding pixels, and then output to the analog front end in the pixel circuit; the operation unit in the pixel circuit corresponding to any pixel uses an image processing algorithm to calculate the pixel current within the target time.

[0038] The present invention creatively adds a computing unit to the pixel circuit, and uses an image processing algorithm to calculate the pixel current, thereby realizing intelligent image processing at the pixel level. There is no need to output to a digital processing chip outside the component for processing, which greatly reduces the data throughput requirements, and well realizes the improvement of infrared imaging performance, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0040] Figure 1 It is a traditional pixel circuit structure;

[0041] Figure 2 is a schematic diagram of a preferred structure of a computing unit in an embodiment of the present invention;

[0042] Figure 3 This is the preferred structure of the pixel circuit mentioned in the embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The pixel circuit based on the image processing algorithm of the present invention is newly designed on the basis of the results of the current traditional pixel circuit. An operation unit is added to the pixel circuit, and a path connecting the pixel circuit corresponding to the surrounding pixels is added. The rest of the structure is the same as the traditional pixel circuit.

[0045] The pixel circuit based on the image processing algorithm of the present invention comprises: a detector, a computing unit, an analog front end and an integration unit. The detector is connected to the computing unit, and the detector is used to sample each pixel, obtain the pixel current corresponding to each pixel and output it to the computing unit.

[0046] The operation unit is connected to the analog front end, and the operation unit is used to use the image processing algorithm to operate the pixel current, obtain the signal current and output it to the analog front end; the analog front end is connected to the integration unit, and the analog front end is used to amplify and filter the signal current, obtain the front-end current and output it to the integration unit; the integration unit is used to generate an integral voltage according to the front-end current.

[0047] Among them, the pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels, and for any pixel:

[0048] The signal current obtained by the operation unit in the pixel circuit corresponding to any pixel is added with the signal current obtained by the operation unit in the pixel circuit corresponding to the surrounding pixels, and then output to the analog front end in the pixel circuit. For example, if the pixel in the second row and second column has 8 periodic pixels, the signal current obtained by the operation unit in the pixel circuit corresponding to the second row and second column needs to be added with the signal current obtained by each operation unit in the 8 pixel circuits corresponding to the surrounding 8 pixels, and then output to the analog front end in the pixel circuit of the second row and second column.

[0049] The computing unit in the pixel circuit corresponding to any pixel uses the image processing algorithm to calculate the pixel current within the target time. The target time is obtained based on: according to the size of the convolution kernel in the image processing algorithm, one frame time is divided into multiple parts, each time is a target time, and the number of parts of one frame time is equal to the size of the convolution kernel. For example: if the convolution kernel is 3×3, the size of the convolution kernel is 9, then one frame time is divided into 9 parts, each time is: one frame time / 9, which is a target time.

[0050] Due to the image processing algorithm, it is necessary to perform simple calculations on the imaging unit. Generally, a small convolution kernel, such as 3x3, is used to calculate the image. The pixel level is mainly processed by one-dimensional differential operators, such as Roberts, Prewitt, Sobel, Canny, etc., second-order differential edge operators, LOG edge detection operators, etc.

[0051] Because the algorithm needs to be designed based on the pixel circuit, a single pixel circuit needs to have a connection path with the surrounding pixels, and a single pixel needs to have a basic operation unit. Taking the 3×3 convolution kernel as an example, through the analysis of the operator of the image algorithm, it can be known that the coefficients of a single pixel are mainly ±1, ±2, ±4, 0. Therefore, it is necessary to design an operation unit that can use the image processing algorithm to calculate the pixel current.

[0052] The traditional pixel circuit structure is as follows Figure 1 As shown. Detector D generates pixel current I DET , through the analog front end ( Figure 1 AFE is used to represent the fixed time t INT Internal integrating capacitance C INT The integrated voltage V INT The integrated voltage V is output by the subsequent analog channel. INT Therefore, the integrated voltage V INT The expression is as follows:

[0053]

[0054] Based on the above theory, the designed operation unit includes: a current mirror structure and multiple switch bridge arm structures; each switch bridge arm structure includes: two MOS tubes and two switches, and the two MOS tubes are connected by two switches in series. The number of multiple switch bridge arm structures is determined by the coefficient of a single pixel, which is determined by the size of the convolution kernel. For example: refer to Figure 2 The preferred structure of the operation unit in the embodiment of the present invention shown is based on a convolution kernel of size 3×3 and seven coefficients of ±1, ±2, ±4, and 0 as an example, and can implement an operation unit structure with seven coefficients.

[0055] The current mirror structure includes: a first MOS tube M1 and a second MOS tube M2; multiple switch bridge arm structures include: a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and multiple switches S1, S2, S3, S4, S5, S6.

[0056] A first end of the first MOSFET M1, a first end of the second MOSFET M2, a first end of the third MOSFET M3, a first end of the fourth MOSFET M4, and a first end of the fifth MOSFET M5 all receive a power supply voltage VDD; a second end of the first MOSFET M1 is respectively connected to a second end of the second MOSFET M2, a second end of the third MOSFET M3, a second end of the fourth MOSFET M4, and a second end of the fifth MOSFET M5, and a second end of the first MOSFET M1 is connected to its own third end and grounded.

[0057] The third end of the second MOSFET M2 is connected to the first end and the second end of the sixth MOSFET M6 , the second end of the seventh MOSFET M7 , the second end of the eighth MOSFET M8 , and the second end of the ninth MOSFET M9 , respectively.

[0058] A third end of the sixth MOSFET M6 , a third end of the seventh MOSFET M7 , a third end of the eighth MOSFET M8 , and a third end of the ninth MOSFET M9 are all grounded.

[0059] The third end of the third MOSFET M3 is connected to the first end of the seventh MOSFET M7 through two series switches S1 and S2; the third end of the fourth MOSFET M4 is connected to the first end of the eighth MOSFET M8 through two series switches S3 and S4; the third end of the fifth MOSFET M5 is connected to the first end of the ninth MOSFET M9 through two series switches S5 and S6. The connection points of the two series switches, i.e., the connection points of the switches S1 and S2, the connection points of the switches S3 and S4, and the connection points of the switches S5 and S6, all output a signal current I INT .Depend on Figure 2 It can be seen that under this structure, except for the fifth MOS tube M5 and the ninth MOS tube M9, the current flowing through the switch bridge arm structure is twice the pixel current: 2×I DET Except for the above, the current flowing through the other switch bridge arm structures is equal to the pixel current I DET .

[0060] The on and off of multiple switches are determined by the coefficients of the corresponding positions of the convolution kernel. The addition of circuit coefficients is realized through external control signals, thereby completing the operation of the convolution kernel. The signal current I obtained by the operation unit in the pixel circuit corresponding to any pixel INT for:

[0061] I INT = k × I DET

[0062] In the above formula, k represents a coefficient.

[0063] In the specific working process, for example, the three switches S1, S3, and S5 are all closed and turned on, and the three switches S2, S4, and S6 are all opened, then IINT = -4×I DET , that is, the coefficient is -4. It is understandable that if the size of the convolution kernel changes, the coefficient changes, and the computing unit of the above structure cannot realize all the coefficients, then it is necessary to add a switch bridge arm structure, that is, after the fifth MOS tube M5 and the ninth MOS tube M9, add a few more switch bridge arm structures to realize each coefficient. How many switch bridge arm structures to add specifically, those skilled in the art will know. Figure 2 Based on the operation unit structure shown, a simple combination experiment can be carried out to obtain the result.

[0064] Figure 2 In order to more clearly illustrate the structure of the operation unit proposed in the present invention, a specific p-type MOS tube and an n-type MOS tube are used as examples to illustrate the structure. Those skilled in the art can easily replace the structure with other transistors or other components, so other forms of structures are not described in detail.

[0065] Based on the above 3×3 convolution kernel operation unit structure, the preferred structural diagram of the pixel circuit proposed in the present invention can be referred to Figure 3 As shown. The integration unit includes: sampling capacitor C INT ; Front-end current I corresponding to a single pixel DET , in the target time corresponding to a single pixel, the sampling capacitor C INT After the integration, the integrated voltage corresponding to a single pixel is obtained; then all pixels corresponding to the convolution kernel size of one frame time obtain their own integrated voltages.

[0066] Figure 3 In the example, the fifth pixel is integrated and the pixel circuit corresponding to the fifth pixel is used. The operation unit ( Figure 3 AU is used in the target time: the pixel current I corresponding to the 5th pixel is processed by the image processing algorithm. DET Perform calculation to obtain the signal current I INT＜5＞ At the same time, the pixel circuit corresponding to the fifth pixel obtains the signal current I INT＜5＞ , and the signal current I obtained by each operation unit in the pixel circuit corresponding to the surrounding 8 pixels INT＜1:4＞ ,I INT＜6:9＞ After addition, it is output to the analog front end in the pixel circuit corresponding to the fifth pixel ( Figure 3 AFE is used in the representation).

[0067] It should be noted that the signal current I INT＜5＞ It will also output current to the eight surrounding pixel circuits. For example, the pixel circuit corresponding to the sixth pixel will output I INT＜6＞ ,I INT＜1:5＞ ,IINT＜7:9＞ After addition, it is output to the analog front end of the pixel circuit corresponding to the sixth pixel, and the working conditions of the remaining pixel circuits can be obtained by analogy. The addition of multiple signal currents can be implemented in a variety of ways, such as using an adder circuit or a device with an addition function, which will not be described in detail.

[0068] The remaining pixels can be understood by referring to the pixel circuit structure and working principle corresponding to the fifth pixel, and no further description is given. It can be understood that, assuming that there are not 8 pixels around a certain pixel, for example, the first pixel in the first row has only 3 pixels around it, then the pixel circuit corresponding to the first pixel in the first row will only receive the signal current in the surrounding 3 pixel circuits, which will be added to the 3 signal currents and then output to the analog front end in the pixel circuit corresponding to the first pixel in the first row.

[0069] Finally, all nine pixels are sampled and integrated in the same way. Then, after nine target times, the integral voltage V generated by the time integration unit for one frame is INT for:

[0070]

[0071] In the above formula, t INT represents a fixed time, n represents the convolution kernel size, j represents the number of pixels, k represents the coefficient, and I DET Represents the pixel current, C INT Indicates the integral capacitor C INT size.

[0072] From this we can also know that the final integrating capacitor C INT The voltage after the operator processing (that is, the operation unit uses the image processing algorithm to process) will be obtained. However, in one operation, only 3×3 data can be integrated into one pixel. If only one processing is performed, the resolution of the image will be reduced.

[0073] However, in infrared detection, the pixel current is approximately stable in the same frame, so the frame time can be divided into nine equal parts, and the data of each pixel in the nine-square grid can be processed in turn, so as to complete the convolution kernel processing of the overall data in the same frame and complete the preliminary algorithm processing of the image at the readout circuit level.

[0074] Based on the above pixel circuit based on the image processing algorithm, an embodiment of the present invention further provides an analog-to-digital converter with image processing, and the analog-to-digital converter with image processing includes: any pixel circuit based on the image processing algorithm as described above.

[0075] Based on the above pixel circuit based on the image processing algorithm, an embodiment of the present invention further provides an infrared imager, and the infrared imager includes: any pixel circuit based on the image processing algorithm as described above.

[0076] Through the above embodiments, in the pixel circuit based on the image processing algorithm of the present invention, the detector samples each pixel, obtains the pixel current corresponding to each pixel and outputs it to the operation unit; the operation unit uses the image processing algorithm to operate on the pixel current, obtains the signal current and outputs it to the analog front end; the analog front end amplifies and filters the signal current, obtains the front-end current and outputs it to the integration unit; the integration unit generates an integration voltage according to the front-end current.

[0077] The pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels. For any pixel: the signal current obtained by the operation unit in the pixel circuit corresponding to any pixel is added with the signal current obtained by the operation unit in the pixel circuit corresponding to the surrounding pixels, and then output to the analog front end in the pixel circuit; the operation unit in the pixel circuit corresponding to any pixel uses an image processing algorithm to calculate the pixel current within the target time.

[0078] The present invention creatively adds a computing unit to the pixel circuit, and uses an image processing algorithm to calculate the pixel current, thereby realizing intelligent image processing at the pixel level. There is no need to output to a digital processing chip outside the component for processing, which greatly reduces the data throughput requirements, and well realizes the improvement of infrared imaging performance, and has high practicality.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A pixel circuit based on an image processing algorithm, characterized in that: The pixel circuit includes: a detector, a computing unit, an analog front end and an integration unit; The detector is connected to the operation unit, and the detector is used to sample each pixel, obtain a pixel current corresponding to each pixel, and output the pixel current to the operation unit; The operation unit is connected to the analog front end, and the operation unit is used to operate the pixel current using an image processing algorithm to obtain a signal current and output it to the analog front end; The analog front end is connected to the integration unit, and the analog front end is used to amplify and filter the signal current to obtain the front end current and output it to the integration unit; The integration unit is used to generate an integration voltage according to the front-end current; The pixel circuit corresponding to each pixel has a connection path with the pixel circuits corresponding to the surrounding pixels, and for any pixel: The signal current obtained by the operation unit in the pixel circuit corresponding to any pixel is added with the signal current obtained by the operation units in the pixel circuits corresponding to the surrounding pixels, and then output to the analog front end in the pixel circuit; The computing unit in the pixel circuit corresponding to any pixel uses an image processing algorithm to calculate the pixel current within a target time. The target time is obtained based on: according to the size of the convolution kernel in the image processing algorithm, one frame time is divided into multiple parts, each time part is a target time, and the number of parts of one frame time is equal to the size of the convolution kernel.

2. The pixel circuit according to claim 1, characterized in that: The operation unit comprises: a current mirror structure and a plurality of switch bridge arm structures; Each switch bridge arm structure includes: two MOS tubes and two switches, wherein the two MOS tubes are connected via two switches connected in series.

3. The pixel circuit according to claim 2, characterized in that: The number of the plurality of switch bridge arm structures is determined by a coefficient of a single pixel, and the coefficient is determined by a size of the convolution kernel.

4. The pixel circuit according to claim 3, characterized in that: When the size of the convolution kernel is 3×3, the coefficients of the single pixel are ±1, ±2, ±4 and 0, then the current mirror structure includes: a first MOS tube and a second MOS tube; the multiple switch bridge arm structures include: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a plurality of switches; The first end of the first MOS tube, the first end of the second MOS tube, the first end of the third MOS tube, and the first end of the fourth MOS tube all receive the pixel current; The second end of the first MOS tube is connected to the second end of the second MOS tube, the second end of the third MOS tube, the second end of the fourth MOS tube, and the second end of the fifth MOS tube respectively, and the second end of the first MOS tube is connected to its third end and grounded; The third end of the second MOS tube is connected to the first end and the second end of the sixth MOS tube, the second end of the seventh MOS tube, the second end of the eighth MOS tube, and the second end of the ninth MOS tube respectively; The third end of the sixth MOS tube, the third end of the seventh MOS tube, the third end of the eighth MOS tube, and the third end of the ninth MOS tube are all grounded; The first end of the fifth MOS tube receives twice the pixel current; The third end of the third MOS and the first end of the seventh MOS, the third end of the fourth MOS and the first end of the eighth MOS, and the third end of the fifth MOS and the first end of the ninth MOS are all connected through two series switches, wherein the connection between the two series switches outputs the signal current.

5. The pixel circuit according to claim 3, characterized in that: The on and off of the multiple switches are determined by the coefficients of the corresponding positions of the convolution kernel.

6. The pixel circuit according to claim 3, characterized in that: The signal current I obtained by the operation unit in the pixel circuit corresponding to any pixel INT for: I INT =k×I DET In the above formula, k represents the coefficient, I DET represents the pixel current.

7. The pixel circuit according to claim 1, characterized in that: The integration unit comprises: a sampling capacitor; The front-end current corresponding to a single pixel is integrated on the sampling capacitor within a target time corresponding to the single pixel to obtain an integrated voltage corresponding to the single pixel; All pixels corresponding to the convolution kernel size of one frame time obtain their own integrated voltage.

8. The pixel circuit according to claim 6, characterized in that: The integral voltage V generated by the integral unit in one frame time is INT for: In the above formula, t INT represents a fixed time, n represents the convolution kernel size, j represents the number of pixels, k represents the coefficient, I DET represents the pixel current, C INT Indicates the size of the integrating capacitor.

9. An analog-to-digital converter with image processing function, characterized in that: The analog-to-digital converter with image processing function comprises: a pixel circuit based on an image processing algorithm as described in any one of claims 1-8.

10. An infrared imager, characterized in that: The infrared imager comprises: a pixel circuit based on an image processing algorithm as described in any one of claims 1-8.

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