A temperature detection circuit

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a temperature detection circuit, which comprises an external temperature detection resistance network, a temperature detection operational amplifier, a level shift circuit and a temperature detection module; the external temperature detection resistance network generates a voltage signal changing with temperature according to the external temperature, and inputs the voltage signal into the temperature detection operational amplifier; the temperature detection operational amplifier converts the voltage signal into a current signal changing with temperature; the level shift circuit converts the current signal into a voltage signal, superimposes the converted voltage signal with a basic signal, inputs the superimposed signal into the temperature detection module, and obtains a temperature detection result; the temperature detection circuit structure of the application is different from the traditional device using a triode VBE as a temperature detection device, and through external connection of a special linear temperature-sensitive resistance sampling network, the precision of sampling is ensured.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and particularly relates to a temperature detection circuit. BACKGROUND

[0002] In a power integrated circuit, when a device works at different temperatures, a relatively accurate temperature detection is involved, which aims to compensate for the drift of the stability or performance of the circuit caused by different temperatures. Therefore, a relatively accurate temperature detection circuit is needed, which is converted into a temperature-varying current signal or voltage signal and transmitted to the later stage.

[0003] A traditional temperature detection circuit passes a bias current through a transistor Q1, and then passes the voltage difference between the base and the emitter of the transistor, and obtains the detected temperature according to the characteristics of the transistor; the voltage of VBE is a negative temperature coefficient, usually-2mV / ℃. The traditional temperature detection method of VBE voltage is generally simple in circuit implementation, and can be used as an over-temperature protection circuit.

[0004] However, in the traditional temperature detection method, the temperature coefficient of VBE varies with the manufacturing process, which causes poor accuracy of the temperature detection circuit, and thus is not conducive to application in circuits with high temperature variation requirements. SUMMARY

[0005] To solve the above problems existing in the prior art, the present application provides a relatively accurate temperature detection circuit for temperature compensation of peak current limit points at different temperatures in a PWM controller.

[0006] A temperature detection circuit, comprising: an external temperature detection resistance network, a temperature detection operational amplifier, a level shift circuit, and a temperature detection module; the external temperature detection resistance network generates a temperature-varying voltage signal according to the external temperature, and inputs the voltage signal to the temperature detection operational amplifier; the temperature detection operational amplifier converts the voltage signal into a temperature-varying current signal; the level shift circuit converts the current signal into a voltage signal, and superimposes the converted voltage signal with a basic signal, and inputs the superimposed signal into the temperature detection module to obtain a temperature detection result.

[0007] The temperature detection operational amplifier includes PMOS tubes M21, M22, M23, M24, M25, resistors R1, R2, NPN tubes Q21, Q22, Q23, LPNP tubes Q24, Q25, constant current source bias Is, IB1; the source of M21 is connected to the power supply terminal VIN, the gate and drain are short-circuited and connected to the gate of M22 and the gate of M23 respectively, the drain is connected to one end of the constant current source bias IB1; the other end of the constant current source bias IB1 is grounded; the source of M22 is connected to the power supply terminal VIN, the drain is connected to the base of Q21, the collector of Q21 and the base of Q22 respectively; the emitter of Q21 is connected to one end of the resistor R1 The first end of M23 is connected to the emitter of Q23; the other end of resistor R1 is connected to the emitter of Q24; the collector of Q24 is grounded, and the base is connected to port ITEMP and constant current source Is respectively; the source of M23 is connected to the power supply terminal VIN, and the drain is connected to the base of Q23 and the collector of Q22 respectively; the emitter of Q22 is connected to one end of resistor R2, and the other end of resistor R2 is connected to the emitter of Q25 and the drain of M25 respectively; the base of Q25 is connected to the reference voltage input port, and the collector is grounded; the source of M24 is connected to the power supply terminal VIN, and the gate and drain of M24 are connected and then connected to the gate of M25 and the collector of Q23 respectively.

[0008] Preferably, the external temperature detection resistor network includes an NTC thermistor R NTC , resistor R3 and resistor R4; NTC thermistor R NTC It is connected in parallel with resistor R4 and then in series with resistor R3; the other end of resistor R3 is connected to the temperature detection operational amplifier.

[0009] Preferably, the level shift circuit includes PMOS tubes M26 and M27, a resistor R5, and NPN tubes Q26 and Q27; the source of the PMOS tube M26 is connected to the power supply terminal VIN, the gate is connected to the gate of M27, and the drain is respectively connected to the collector of Q26, the base of Q26, and the base of Q27; the emitter of Q26 is grounded; the source of M27 is connected to the power supply terminal VIN, the drain of M27 is connected to one end of the resistor R5; the other end of the resistor R5 is connected to the collector of Q27; and the emitter of Q27 is grounded.

[0010] Furthermore, the drain of the PMOS transistor M27 in the level shift circuit serves as the signal output terminal V1 of the level shift circuit; the collector of the NPN transistor Q27 serves as the bidirectional port Vbase of the level shift circuit.

[0011] Beneficial effects of the present invention:

[0012] The temperature detection circuit structure of the present invention is different from the traditional device that uses a triode VBE as a temperature detection device. The sampling accuracy is guaranteed by an external dedicated linearized temperature-sensitive resistor sampling network. The present invention converts the sampled temperature information into a current signal in the form of negative feedback from an operational amplifier, and converts it through a complex ADC circuit. While ensuring accuracy, the structure is also relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of an external linear resistor network of the present invention;

[0014] Figure 2 is a structural diagram of the temperature detection circuit of the present invention;

[0015] Figure 3 This is a diagram showing the relationship between the port voltage and temperature of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] A temperature detection circuit includes: an external temperature detection resistor network, a temperature detection operational amplifier, a level shift circuit, and a temperature detection module; the external temperature detection resistor network generates a temperature-varying voltage signal based on the external temperature, and inputs the voltage signal into the temperature detection operational amplifier; the temperature detection operational amplifier converts the voltage signal into a temperature-varying current signal; the level shift circuit converts the current signal into a voltage signal, superimposes the converted voltage signal with a basic signal, and inputs the superimposed signal into the temperature detection module to obtain a temperature detection result.

[0018] Figure 1 This paper describes the application environment of a temperature sensing circuit, which is used in a PWM controller circuit to compensate for the peak current limit of a DC-DC converter circuit at different temperatures. The converter uses an external temperature compensation network, also known as an external temperature sensing resistor network 1, connected to the ITEMP pin to detect temperature.

[0019] In this embodiment, the external temperature detection resistor network includes an NTC thermistor R NTC , resistor R3 and resistor R4; NTC thermistor R NTC After being connected in parallel with the resistor R4, it is connected in series with the resistor R3; the NTC thermistor R NTCThe other end of the resistor R3 connected in parallel with the resistor R4 is grounded. The other end of the resistor R3 is connected to the temperature detection amplifier.

[0020] For the "external temperature detection resistor network" circuit, the sampling of the RNTC resistor is linearized through resistors R3 and R4 to ensure the accuracy of the temperature sampling information.

[0021] The resistance expression of NTC thermistor at temperature T is:

[0022]

[0023] where R T0 When the temperature is T0=25℃, R NTC The resistance value of the temperature sensitive resistor; β is the material characteristic constant of the temperature sensitive resistor, the unit is K, and T represents the current temperature.

[0024] The outgoing constant current source Is inside the ITEMP port flows into the external temperature detection resistor network 1, and the resulting port voltage VTEMP is:

[0025]

[0026] In the above formula, the linearization of VTEMP is achieved by introducing the resistor R4. Specifically, the formula of VTEMP is expanded by Taylor formula to make its high-order minima with respect to temperature zero. The required resistance values ​​of R4 and R3 can be calculated.

[0027] In this embodiment, if Figure 2As shown, the temperature detection operational amplifier includes PMOS tubes M21, M22, M23, M24, and M25, resistors R1 and R2, NPN tubes Q21, Q22, and Q23, LPNP tubes Q24 and Q25, and constant current source bias Is and IB1; the source of M21 is connected to the power supply terminal VIN, the gate and the drain are short-circuited and connected to the gate of M22 and the gate of M23 respectively, and the drain is connected to one end of the constant current source bias IB1; the other end of the constant current source bias IB1 is grounded; the source of M22 is connected to the power supply terminal VIN, and the drain is connected to the base of Q21, the collector of Q21, and the base of Q22 respectively; the emitter of Q21 is connected to the resistor R1 One end of the resistor R1 is connected to the emitter of Q23; the other end of the resistor R1 is connected to the emitter of Q24; the collector of Q24 is grounded, and the base is connected to the port ITEMP and the constant current source Is respectively; the source of M23 is connected to the power supply terminal VIN, and the drain is connected to the base of Q23 and the collector of Q22 respectively; the emitter of Q22 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the emitter of Q25 and the drain of M25 respectively; the base of Q25 is connected to the reference voltage input port, and the collector is grounded; the source of M24 is connected to the power supply terminal VIN, and the gate and drain of M24 are connected and then connected to the gate of M25 and the collector of Q23 respectively.

[0028] For the "VITEMP temperature detection op amp" circuit, Q24 and Q25 are the positive and negative input terminals of the op amp respectively. PMOS tubes M22 and M23 mirror the bias current of the M21 branch, and the mirror ratio is 1:1. Q21 and Q22 tubes form a clamping circuit, clamping their emitter voltages to be equal, that is, Figure 2 The voltages at points A and B are equal. The emitter of Q23 is fed back to one end of the resistor in the input branch of Q24, forming a negative feedback structure.

[0029] For the branch where Q21 is located, the voltage node equation is:

[0030] V A =V ITEMP +Vbe Q24 +(I SET +I DM22 )·R

[0031] Among them, V ITEMP Indicates the voltage signal converted from the temperature sampling signal outside the device, Vbe Q24 represents the emitter junction voltage drop of Q24, I SET It represents the current fed back from Q23 to the emitter of Q21, I DM22 Represents the current flowing through M22, and R represents the resistance value of resistor R1.

[0032] For the branch where Q22 is located, the voltage node equation is:

[0033] V B =V+Vbe Q25 +I DM23 ·R x

[0034] Where V represents the reference voltage, Vbe Q25 represents the emitter junction voltage drop of Q25, I DM23 Represents the current flowing through M23, R x Indicates the resistance value of resistor R2.

[0035] Because PMOS transistors M22 and M23 mirror the bias current of branch M21 at a 1:1 ratio, the currents flowing through M22 and M23 are equal. Furthermore, M24 and M25 are also mirror transistors, with a 1:1 ratio. This results in equal emitter currents through Q24 and Q25, and their VBE voltages are also equal. Based on the voltages of the branch Q21 and Q22, the emitter current ISET flowing through Q23 is:

[0036]

[0037] The premise for temperature compensation to occur is that VITEMP should be less than the 0.5V reference voltage.

[0038] In this embodiment, the level shift circuit includes PMOS transistors M26 and M27, a resistor R5, and NPN transistors Q26 and Q27; the source of the PMOS transistor M26 is connected to the power supply terminal VIN, the gate is connected to the gate of M27, and the drain is connected to the collector of Q26, the base of Q26, and the base of Q27 respectively; the emitter of Q26 is grounded; the source of M27 is connected to the power supply terminal VIN, and the drain of M27 is connected to one end of the resistor R5; the other end of the resistor R5 is connected to the collector of Q27; and the emitter of Q27 is grounded.

[0039] For the "VITEMP level shift circuit" part of the circuit, the current signal ISET mapped by VITEMP is mirrored to the VITEMP level shift circuit composed of M26, M27, Q26, and Q27 through M24, and its output voltage V1 is:

[0040]

[0041] Among them, Vbase is an externally given constant bias voltage with a small temperature coefficient.

[0042] Simplifying the output voltage V1 according to the emitter current ISET flowing through Q23, we get:

[0043]

[0044] According to the above expression, it can be concluded that the external linearized temperature-varying voltage signal VTEMP is converted into a temperature-varying current signal ISET through the negative feedback structure of the op amp. Then, through the VITEMP level shift circuit, the ISET current signal is converted into a voltage signal and superimposed on a basic signal before being sent to the subsequent control circuit.

[0045] like Figure 3 As shown in the figure, the linearization results of an NTC resistor with a constant temperature resistance of 275kΩ are shown. As the temperature rises, the detected voltage VTEMP decreases linearly, consistent with the theoretical calculation. The deviation is mainly caused by the difference between the actual value of the temperature sensitive resistor RNTC and the theoretical value.

[0046] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation plans of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A temperature detection circuit, characterized in that: include: External temperature detection resistor network, temperature detection operational amplifier, level shift circuit and temperature detection module; The external temperature detection resistor network generates a temperature-varying voltage signal based on the external temperature, and inputs the voltage signal into the temperature detection op amp; the temperature detection op amp converts the voltage signal into a temperature-varying current signal; The level shift circuit converts the current signal into a voltage signal, superimposes the converted voltage signal with the basic signal, and inputs the superimposed signal into the temperature detection module to obtain the temperature detection result; The temperature detection operational amplifier includes PMOS tubes M21, M22, M23, M24, and M25, resistors R1 and R2, NPN tubes Q21, Q22, and Q23, LPNP tubes Q24 and Q25, and constant current source bias Is and IB1; the source of M21 is connected to the power supply terminal VIN, the gate and drain are short-circuited and connected to the gate of M22 and the gate of M23 respectively, and the drain is connected to one end of the constant current source bias IB1; The other end of the constant current source bias IB1 is grounded; the source of M22 is connected to the power supply terminal VIN, and the drain is connected to the base of Q21, the collector of Q21 and the base of Q22 respectively; the emitter of Q21 is connected to one end of the resistor R1 and the emitter of Q23 respectively; the other end of the resistor R1 is connected to the emitter of Q24; the collector of Q24 is grounded, and the base is connected to the port ITEMP and the constant current source Is respectively; the source of M23 is connected to the power supply terminal VIN, and the drain is connected to the base of Q23 and the collector of Q22 respectively; the emitter of Q22 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the emitter of Q25 and the drain of M25 respectively; the base of Q25 is connected to the reference voltage input port, and the collector is grounded; the source of M24 is connected to the power supply terminal VIN, and the gate and drain of M24 are connected and then connected to the gate of M25 and the collector of Q23 respectively.

2. A temperature detection circuit according to claim 1, characterized in that: The external temperature detection resistor network includes an NTC thermistor R NTC , resistor R3 and resistor R4; NTC thermistor R NTC It is connected in parallel with resistor R4 and then in series with resistor R3; the other end of resistor R3 is connected to the temperature detection op amp.

3. A temperature detection circuit according to claim 1, characterized in that: NTC thermistor R NTC The resistance value is: Among them, R T0 Indicates that the temperature is at T0. NTC The resistance value of the temperature sensitive resistor is β, which represents the material characteristic constant of the temperature sensitive resistor, and T represents the current temperature.

4. A temperature detection circuit according to claim 1, characterized in that: The level shift circuit includes PMOS transistors M26 and M27, a resistor R5, and NPN transistors Q26 and Q27. The source of the PMOS transistor M26 is connected to the power supply terminal VIN, the gate is connected to the gate of M27, and the drain is connected to the collector of Q26, the base of Q26, and the base of Q27 respectively. The emitter of Q26 is grounded. The source of M27 is connected to the power supply terminal VIN, and the drain of M27 is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the collector of Q27. The emitter of Q27 is grounded.

5. A temperature detection circuit according to claim 4, characterized in that: The drain of the PMOS transistor M27 in the level shift circuit serves as the signal output terminal V1 of the level shift circuit; the collector of the NPN transistor Q27 serves as the bidirectional port Vbase terminal of the level shift circuit.

6. A temperature detection circuit according to claim 5, characterized in that: The output voltage of the signal output terminal V1 of the level shift circuit is: V1=V base +I SET ×R m . Among them, V base is an externally given constant bias voltage, I SET is the current output by the temperature detection amplifier, R m Indicates the resistance value of resistor R5.

7. A temperature detection circuit according to claim 4, characterized in that: The level shift circuit and the temperature detection operational amplifier are connected to each other including: connecting the M26 gate and the M27 gate of the level shift circuit and then connecting the M24 gate and the drain of the temperature detection operational amplifier to form a current mirror structure.

8. The temperature detection circuit according to claim 1, characterized in that: The voltage calculation formula for the branch where Q21 is located of the temperature detection op amp is: V A =V ITEMP +Vbe Q24 +(I SET +I DM22 )·R Among them, V ITEMP Indicates the voltage signal converted from the temperature sampling signal outside the device, Vbe Q24 represents the emitter junction voltage drop of Q24, I SET It represents the current fed back from Q23 to the emitter of Q21, I DM22 Represents the current flowing through M22, and R represents the resistance value of resistor R1.

9. The temperature detection circuit according to claim 1, characterized in that: The voltage calculation formula for the branch where Q22 is located of the temperature detection op amp is: V B =V+Vbe Q25 +I DM23 ·R x Where V represents the reference voltage, Vbe Q25 represents the emitter junction voltage drop of Q25, I DM23 Represents the current flowing through M23, R x Indicates the resistance value of resistor R2.

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