Capacitive Linear Phase Interpolator

Abstract

The present application relates to variable linear phase interpolators. A system includes: a sampler; a receiver phase-locked loop circuit configured to provide one or more input clock signals; and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler. The phase interpolation circuit further includes: a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal, wherein the outputs of the first phase interpolator and the second phase interpolator are configured to be combined.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for addressing errors introduced by nonlinearities in phase interpolators. Background Art

[0004] Phase interpolators (PIs), also commonly called "phase rotators," are core components that implement basic transceiver functions such as clock and data recovery (CDR), loop timing modes, and spread spectrum clocking (SSC). Transceiver performance is affected by integral nonlinearity (INL) in the PI, which introduces jitter to the recovered clock.

[0005] Jitter is very important in systems with advanced modulation, such as Pulse Amplitude Modulation 4-level (PAM4) and Quadrature Amplitude Modulation 16-level (QAM16) / Quadrature Amplitude Modulation 64-level (QAM64), which are the main modulation schemes for links at speeds of 100G and above. The timing and noise margins of modulated signals are significantly smaller than non-return-to-zero (NRZ) signals. For analog-to-digital converter (ADC)-based receivers with advanced modulation, inaccurate sampling clock timing can degrade ADC performance. For high-speed input signals, the degradation effect becomes even greater.

[0006] Therefore, methods, systems, and apparatus for a variation tolerant linear phase interpolator are provided. Summary of the invention

[0007] On the one hand, the present application provides a method, which includes: obtaining one or more input clock signals; generating a first recovered clock signal via a first phase interpolator based on the one or more input clock signals and a first code; generating a second recovered clock signal via a second phase interpolator based on the one or more input clock signals and a second code, wherein the second code has an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; and combining the first recovered clock signal and the second recovered clock signal, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal.

[0008] On the other hand, the present application provides a circuit comprising: a first phase interpolator, which is configured to obtain one or more input clock signals and generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator, which is configured to obtain the one or more input clock signals and generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; wherein the outputs of the first phase interpolator and the second phase interpolator are configured to be combined.

[0009] On the other hand, the present application provides a system comprising: a sampler configured to convert an input signal into a digital output signal; a receiver phase-locked loop circuit configured to provide one or more input clock signals; a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler, wherein the phase interpolation circuit is configured to provide a combined recovered clock signal to the sampler, wherein the phase interpolation circuit further comprises: a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; wherein the outputs of the first phase interpolator and the second phase interpolator are configured to be combined, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of certain embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0011] Figure 1 is a schematic block diagram of a receiver system according to various embodiments;

[0012] Figure 2 is a schematic block diagram of a transmitter system according to various embodiments;

[0013] Figure 3 is a schematic block diagram of a variable-capacitive linear phase interpolator circuit according to various embodiments;

[0014] Figure 4 is a schematic diagram illustrating a process of INL elimination according to various embodiments; and

[0015] Figure 5 is a flow chart of a variable-tolerant linear phase interpolation method according to various embodiments. DETAILED DESCRIPTION

[0016] Various embodiments provide tools and techniques for variable-tolerant linear phase interpolators.

[0017] In some embodiments, a method for variable-tolerant linear phase interpolation is provided. The method may include obtaining one or more input clock signals, and generating a first recovered clock signal via a first phase interpolator based on the one or more input clock signals and a first code. The method may continue by generating a second recovered clock signal via a second phase interpolator based on the one or more input clock signals and a second code. The second code may have an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal. The method may further include combining the first recovered clock signal and the second recovered clock signal, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal.

[0018] In some embodiments, an apparatus for a variable linear phase interpolator is provided. The apparatus may include a first phase interpolator configured to obtain one or more input clock signals and generate a first recovered clock signal based on the one or more input clock signals and a first code. The apparatus may further include a second phase interpolator configured to obtain the one or more input clock signals and generate a second recovered clock signal based on the one or more input clock signals and a second code. The second code may have an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal. The outputs of the first phase interpolator and the second phase interpolator may be configured to be combined.

[0019] In another embodiment, a system for a variable linear phase interpolator is provided. The system may include: a sampler configured to convert an input signal into a digital output signal; a receiver phase-locked loop circuit configured to provide one or more input clock signals; and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler, wherein the phase interpolation circuit is configured to provide a combined recovered clock signal to the sampler. The phase interpolation circuit may further include: a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code. The second code may have an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal. The outputs of the first phase interpolator and the second phase interpolator are configured to be combined, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal.

[0020] In the following description, for the purpose of explanation, many details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be appreciated by those skilled in the art that other embodiments may be practiced without some of the specific details. In other examples, structures and devices are shown in block diagram form. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be appreciated that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, any single feature or multiple features of any described embodiment should not be considered necessary for each embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0021] Similarly, when an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or there may be an intervening element between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0022] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise dictates, intermediary processes may occur before and / or after any portion of the described processes, and further various procedures may be reordered, added, and / or omitted according to various embodiments.

[0023] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". In addition, the use of the term "including" and other forms, such as "includes" and "included", should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" cover both elements and components that include one unit and elements and components that include more than one unit.

[0024] Conventional approaches to mitigate INL attempt to adjust transistor size and input amplitude combinations to linearize the phase-to-input control relationship. However, conventional approaches fail to achieve good linearity under different process corner, voltage, and temperature (PVT) conditions. These approaches typically result in excessive power consumption and / or area overhead, leading to larger transistor sizes or larger input amplitudes. Another conventional approach attempts to shape the PI current bias digital-to-analog converter (DAC) with non-uniform weighting to equalize the nonlinear phase-to-PI code relationship. Similarly, this process cannot be applied to different PVT conditions because the PI nonlinear shape (e.g., the shape of the PI nonlinear profile, which plots the INL on the PI code) varies with PVT. The PI nonlinear shape may also vary with input signal amplitude variations and rise / fall times, which cannot be compensated by non-uniform weighting of the PI current bias DAC. In addition, shaping of the PI current bias DAC (e.g., current DAC) may result in larger amplitude variations on the PI code (e.g., the amplitude of the PI output varies depending on the PI code).

[0025] The embodiments set forth below may allow for a more robust, scalable approach to mitigate INL. Specifically, the embodiments below describe a PI architecture for INL cancellation. In some embodiments, using an 8-bit code phase interpolator, the proposed architecture can effectively achieve INL suppression from more than 6 least significant bits (LSBs) to approximately 1 LSB, and less than 1 / 5 of the peak-to-peak INL (INL) before INL cancellation. pp )'s worst-case INL PP Furthermore, the worst-case jitter during PI rotation can be reduced by more than 1 picosecond (ps) in a 28 GHz clock. Furthermore, the proposed technique can tolerate a wide range of operating conditions, including PVT variations and a wide range of frequency variations.

[0026] Therefore, excellent PI linearity and robust performance to PVT variations and mismatches can be achieved without the additional power / area overhead caused by transistor size and input amplitude adjustment methods, and without the loading overhead of downstream circuit stages (e.g., CML to CMOS conversion circuits or buffers) caused by the large output amplitude variation of the current bias DAC method. In addition, the INL elimination method can be extended to higher frequencies. The improvement of PI linearity can also lead to improvements in receive (Rx) jitter tolerance, effective number of bits (ENOB), and transmit (Tx) output jitter. In addition, INL elimination can be implemented without the need for background calibration. These improvements can have the effect of enhancing data rate / speed and extending channel coverage by reducing clock jitter.

[0027] Figure 1 1 is a schematic block diagram of a receiver system 100 according to various embodiments. The system 100 includes an equalizer 105, a sampler 110, a phase interpolator 115, a receiver (Rx) phase locked loop (PLL) 120, a PI phase controller 125, a phase detector and loop filter 130, and a deserializer 135. It should be noted that the various components of the system 100 are described in detail in detail. Figure 1 Modifications to the various components and other arrangements of system 100 are shown schematically in FIG. 1 , and are possible according to various embodiments.

[0028] In various embodiments, the system 100 may be configured to receive a signal to be converted into a digital output signal D out Input signal V of [n] in In various examples, V in may be an analog signal received by the receiver system 100. In some examples, the equalizer 105 may be configured to equalize the input signal V in . In some examples, the equalizer 105 may include a linear equalizer, such as a continuous time linear equalizer (CTLE), while in other embodiments, the equalizer 105 may include a nonlinear equalizer, such as a decision feedback equalizer (DFE), or a combination of a CTLE and / or a DFE. In some examples, the equalizer 105 may include one or more equalizers in a multi-stage arrangement. The equalizer 105 may include, but is not limited to, a digital equalizer and / or a hybrid equalizer. The equalizer 105 may further include an adjustable amplifier with automatic gain control (AGC). According to some examples, the equalizer 105 may be configured to equalize the input signal V in , to take into account channel characteristics (e.g., channel loss) and noise.

[0029] The equalized signal from the equalizer 105 may be provided to the sampler 110. In some examples, the sampler 110 may include an ADC and / or one or more slicers. According to various embodiments, the sampler 110 may be configured to perform a sampling operation on the equalized input signal V inIn some examples, the input signal may be a demodulated signal, for which the sampler 110 sequentially outputs sampled signals to the deserializer 135. In various embodiments, the sampler 110 may be clocked by a clock signal generated by the PI 115. The sampler 110 may sample serial data of the input signal that is equalized by the equalizer 105 and synchronized with the clock signal output by the PI 115. Thus, the deserializer 135 may convert the serial samples of the sampler 110 into a plurality of parallel samples to be passed to the downstream digital block as an output digital signal D out [n] In one example, the deserializer 135 can include a demultiplexer circuit.

[0030] In some examples, to generate the clock signals, the PI 115 may receive a set of quadrature clock signals (e.g., in-phase clock signals (I / IB) and quadrature clock signals (Q / QB)) from the Rx PLL 120. In various examples, each of the clock signals may be phase-shifted from a reference clock signal, wherein the four clock signals I, IB, Q, and QB are evenly spaced. In some examples, I and Q may be 90 degrees apart in phase, IB is 90 degrees phase-shifted from Q, and QB is 90 degrees phase-shifted from IB. Although the clock signals are described herein as four-phase quadrature clock signals with respect to various examples for purposes of explanation, it should be understood that the clock signals are not limited to four-phase quadrature clock signals, and in other embodiments, different numbers of clock signals may be used. Therefore, in various examples, the clock signals may include a multi-phase clock signal having m phases (e.g., four phases, eight phases), where m is an integer. In some examples, the multi-phase clock signal may be provided by a PLL, such as the Rx PLL 120. A PLL such as Rx PLL 120 (and Tx PLL 220 below) may be a circuit configured to generate a clock signal based on a reference input signal, with a feedback mechanism that accurately tracks the frequency of the reference signal. In other examples, PI 115 may be configured to generate a multi-phase clock signal directly from a reference clock signal, rather than receiving the multi-phase clock signal from a PLL.

[0031] In some examples, the PI 115 may generate complementary recovered clock signals CK and CKb, which may be sampling clock signals for the sampler 110. In various examples, the PI 115 may adjust or interpolate the phase of the clock signal from the Rx PLL 120 based on the phase control signal generated by the PI phase controller 125. Thus, the recovered clock signal may be a clock signal generated by the PI 115 based on the phase error extracted from the output digital signal. Thus, in some examples, the PI phase controller 125 may be further coupled to a phase detector (PD) and loop filter 130 circuit. The PD and loop filter 130 may be configured to detect the phase error extracted from the output digital signal D. out[n] The phase error information extracted is filtered and tracks the phase of the input signal. Therefore, the PI phase controller 125 can receive the phase error information extracted from the output digital signal from the PD and the loop filter 130.

[0032] Therefore, while the PI phase controller 125 may mitigate some timing errors through, for example, a clock data recovery (CDR) loop, it may not address the nonlinearity of the PI 115. Therefore, the PI 115 implementing the INL cancellation architecture will be described below with respect to Figure 3 State and describe in further detail.

[0033] Figure 2 2 is a schematic block diagram of a transmitter system 200 according to various embodiments. The system 200 includes a serializer 205, a retimer 210, a PI 215, a Tx PLL 220, a PI phase controller 225, and a driver 230. It should be noted that the various components of the system 200 are Figure 2 Modifications to the various components and other arrangements of system 200 are shown schematically in FIG. 2 , and are possible according to various embodiments.

[0034] In various embodiments, the system 200 may be configured to receive a signal that will be converted into an analog output signal V out The digital input signal D in [n] The serializer 205 can be configured to convert the digital input signal D in [n] into a plurality of parallel bits of a serial stream of corresponding bits. In one example, the serializer 135 may include a multiplexer circuit. The retimer 210 may be configured to recover the data from the serializer 205, extract the embedded clock from the digital input signal, and retransmit the data using the clock signal provided by the PI 215. Thus, the retimer 210 may be configured to synchronize the output from the serializer to the correct clock phase.

[0035] Driver 230 can receive the output of retimer 210 and convert the data stream into an analog signal and drive the analog signal into the appropriate channel. In various examples, driver 230 can be implemented as a voltage mode driver circuit system, a current mode driver circuit system, or a DAC. For example, serializer 205 and retimer 210 can be combined into a single circuit element. Similarly, in some examples, retimer 210 and driver 230 can also be combined into a single circuit element. Tx PLL can include circuit systems for providing a low noise clock signal for retimer 210.

[0036] In various examples, the transmitter system 200 may transmit data at a rate slightly different from the clock signal from the Tx PLL 220 frequency. Therefore, the transmitter system 200 may employ the PI 215 to introduce a frequency offset from the Tx PLL 220. In various examples, the PI code may be generated (or controlled) via the PI phase control circuit 225. Therefore, the PI phase control circuit 225 may be configured to generate (or control) the PI code according to a given frequency offset (F offset The phase of the PI output clock signal may be shifted and / or rotated by the PI phase control circuit 225 to introduce a desired frequency offset to the Tx PLL 220 clock signal.

[0037] In the transmitter system 200, PI nonlinearity can cause jitter, which can degrade the performance of the retimer 210 and distort the output of the driver 230. Therefore, the PI 215 implementing the INL cancellation architecture will be described below with respect to Figure 3 State and describe in further detail.

[0038] Figure 3 is a schematic block diagram of a variable-tolerant linear phase interpolator circuit 300 according to various embodiments. The variable-tolerant phase interpolator circuit 300 includes an IQ adjustment circuit 305, a first phase interpolator (PI0) 310 and a second phase interpolator (PI1) 315, and a buffer 320. It should be noted that the various components of the circuit 300 are Figure 3 Modifications to the various components and other arrangements of circuit 300 are schematically shown in FIG. 3 and are possible according to various embodiments.

[0039] According to various embodiments, the IQ adjustment circuit 305 may be configured to receive a clock signal, for example, from an Rx PLL (e.g., Rx PLL 120), as described above. The clock signal may include I, IB, Q, and QB. The IQ adjustment circuit 305 may be configured to adjust the clock signal based on an IQ control signal (IQ ctrl.) to mitigate errors in the input IQ clock signal. In some instances, IQ ctrl. may be provided via a PI phase control circuit (e.g., PI phase control circuit 125), while in other instances, a separate control block (e.g., a separate control circuit that detects multi-phase errors (IQ errors in this instance) in the input clock) may generate IQ ctrl. Thus, in various instances, the IQ adjustment circuit 305 may be an input phase control circuit that is configured to adjust the phase of a multi-phase input clock signal (in this instance, an IQ clock signal, and therefore referred to as the IQ adjustment circuit 305) and / or the amplitude of the multi-phase input clock signal. Thus, in some instances, the IQ adjustment circuit 305 may include an adjustable amplifier. Thus, the adjusted input clock signal may be provided to each of PI0 310 and PI1 315, respectively.

[0040] Thus, in various embodiments, the IQ adjustment circuit 305 may be coupled to both PI0 310 and PI1 315. In various embodiments, PI0 310 and PI1 315 may be referred to as the PI core of the variable phase interpolator circuit 300. Thus, in various instances, the variable phase interpolator circuit 300 may utilize a dual PI core architecture for INL elimination. In other instances, the variable phase interpolator circuit 300 may include more than two PI cores. For example, a multipath, multi-PI core architecture may be utilized, wherein multiple PI cores have a given phase offset. The phase offset may be determined, for example, based at least in part on the INL profile of the PI core. In some instances, the phase offset at which the INL is minimized when combining the outputs of multiple PI cores may be determined and set as the phase offset between multiple PI cores. In yet further instances, multiple phase offsets may be utilized between multiple PI cores, wherein the corresponding phase offsets between the PI cores may vary.

[0041] Thus, in one set of examples, phase interpolators PI0 310 and PI1 315 may be phase interpolators configured with a 45 degree code offset (corresponding to a four-phase quadrature clock input). For example, PI0 310 may have a code offset of θ, and PI1 315 may have a code offset of θ−45°. Given the code offset of the PI core, the respective INLs of PI0 310 and PI1 315 may be averaged and cancelled by combining (e.g., adding and / or averaging) the outputs of PI0 310 and PI1 315.

[0042] For example, in various embodiments, PI0 310 and PI1 315 may be configured to generate respective recovered clock signals based on a code (e.g., a PI code), wherein respective phases of the recovered clock signals may be shifted according to the code. Thus, in various embodiments, PI0 310 and PI1 315 may first be configured to generate respective recovered clock signals based on a code from a phase control circuit (e.g., a PI code). Figure 1 The PI code is obtained (or in some instances generated) by feedback from the PI phase control circuit 125 of the PI00 3100001000100010001000100010002 ...

[0043] In some examples, the merging of the outputs may be implemented directly at the outputs of PI0 310 and PI1 315. In other examples, the merging may be performed after the outputs of PI0 310 and PI1 315 have passed through one or more buffer stages. The merging may include, but is not limited to, summing and / or averaging the outputs of the PI cores (e.g., PI0 310 and PI1 315) to produce a combined recovered clock signal (e.g., an INL-cancelled recovered clock signal). Figure 4 The effect of INL cancellation is described in more detail. In yet further embodiments, the phase offset between the two PI cores may be set according to the number of input phases of the input clock signal. For example, for an 8-phase clock input, a phase offset of 22.5° between PI0 310 and PI1 315 may be utilized, where the INL profile of the PI may repeat every eighth (45°) of a complete PI code.

[0044] Because the INL profile of a phase interpolator may vary with PVT conditions, in some examples, PI0 310 and PI1 315 may (and may have) been subjected to similar process corners, and further, may be implemented in the variable-capacitance phase interpolator circuit 300 to be subjected to similar voltage and temperature conditions.

[0045] In some further examples, the output of each PI can be adjusted to minimize the amplitude phase error conversion. Specifically, the output of the PI at different code offsets can show different amplitude trends. For example, the amplitude of the output of the PI at the code offset θ can be different from the output at the code offset θ-45°. In some examples, the amplitude mismatch can be manifested as an additional phase nonlinearity due to the amplitude phase conversion error. Therefore, the output amplitude of PI0 310 and PI1 315 can be adjusted to avoid amplitude mismatch. In some examples, the DAC units of the PIs such as PI0 310 and PI1 315 can be segmented into groups with different code offsets. In one set of examples, each section of the DAC unit can include three DAC units, each DAC unit having a corresponding code offset (e.g., code-45°, code and code+45°). In various examples, each section of the DAC unit can be controlled by a corresponding PI code. In some examples, the output of each corresponding DAC unit can be weighted. For example, a DAC unit with a code offset of code-45° and code+45° may be weighted 0.25x, while a DAC unit without a code offset (e.g., code) may be weighted 0.5x. Thus, the amplitude mismatch at different code offsets may be averaged. In this way, in some instances, a phase constellation (e.g., an octagonal constellation) with good amplitude matching may be created. In some further embodiments, an amplitude limiting buffer may be employed at the output of each of the respective PI cores (PI0 310 and PI1 315) to ensure amplitude matching. For example, the limiting buffer may be a buffer configured to limit the output amplitude of the respective PI at a threshold voltage (e.g., limiting the PI output at a maximum positive voltage and / or a maximum negative voltage).

[0046] In various embodiments, the input IQ error may also be adjusted, for example, by the IQ adjustment circuit 305. The IQ error at the PI input may cause the INL profiles between the two PIs (PI0 310 and PI1 315) to not match. This may introduce residual nonlinearity after the INL cancellation between the two PIs. Therefore, in some examples, the input IQ error may be adjusted to improve the INL cancellation performance and avoid residual INL. In various embodiments, the IQ adjustment circuit 305 may adjust the input IQ signal (e.g., the input clock signal from the Rx PLL), for example, by adjusting the phase and / or amplitude of the input IQ signal. In some examples, the IQ adjustment circuit 305 may include a buffer with a tunable capacitor and / or resistor network for appropriate adjustment. In some further examples, the adjustment may be controlled based on an IQ control signal. Although described as an input IQ error relative to an IQ clock, it should be understood that in other embodiments using a multi-phase clock signal, the IQ error may be replaced by a multi-phase error. As used herein, multiple phase errors (including IQ errors) may include phase errors in the input clock signals, such as relative phase errors (phase imbalance) between clock signals, and other IQ imbalances (such as gain imbalance). Therefore, the IQ adjustment circuit 305 may also be referred to as an input phase control circuit, which is configured to adjust the respective phases of the multi-phase input clock signals.

[0047] Figure 4 4 is a schematic diagram illustrating a process 400 of INL elimination according to various embodiments. Specifically, Figure 4 4 shows the INL profile of the phase interpolator, which can vary with the code. For a quadrature input clock, the INL profile of the PI can be repeated every quarter (90°) of the complete PI code. As shown, for example, PI0 310 can have a first INL profile 405. In contrast, PI1 315 can have a second INL profile 410 with a phase shift of 45°. Therefore, the same (or nearly the same) PI with a 45° offset can have an out-of-phase INL profile, where the INL can be cancelled by averaging (or in some instances, adding or combining) the two out-of-phase INL profiles. The average of the INL profiles is shown in the combined INL profile 415.

[0048] In various examples, the shape of the INL profile may vary based on a specific PI implementation and architecture. For example, the INL profile may include, but is not limited to, a sinusoidal (as shown) shape, a sawtooth shape, a square wave shape, etc. However, the INL profile of the PI may be cyclic in nature and repeat a given number of times over the entire PI code (e.g., 360°) depending on the number of phases of the multi-phase input clock signal. For example, as described above, for an 8-phase input clock signal, the INL profile of the PI may be repeated approximately every 45°. Therefore, when two PIs are offset by half of the INL profile period (e.g., 22.5°), the INL profile may be out of phase. As used herein, out of phase may mean eliminating (partially or completely) a waveform (e.g., INL) by a phase offset. In some examples, out of phase may include eliminating a waveform (e.g., INL) so that the INL is minimized (or substantially minimized to a measurable degree) in the case of a non-ideal waveform.

[0049] Figure 5 5 is a flow chart of a method 500 for variable-tolerant linear phase interpolation according to various embodiments. At block 505, the method 500 may begin by obtaining an input IQ clock signal. In various examples, the input IQ clock signal may include a four-phase quadrature input clock signal (e.g., I, Q, IB, and QB) separated by 90° phases. In further embodiments, the input clock signal may include additional phases, such as an 8-phase clock input. As previously described, the input IQ clock signal may be obtained from the Rx PLL circuit by a phase interpolator.

[0050] At block 510, the method 500 may continue by adjusting the input IQ clock signal for the input IQ error. As previously described, the input IQ error may be adjusted, for example, by an IQ adjustment circuit. In various embodiments, the IQ adjustment circuit may adjust the input IQ clock signal by adjusting the phase and / or amplitude of the input IQ clock signal. In some examples, the IQ adjustment circuit may include a buffer with a tunable capacitor (e.g., an adjustable amplifier) ​​and / or a resistor network to make appropriate adjustments. In some further examples, the adjustment may be controlled based on an IQ control signal. In further embodiments, the input IQ clock signal may be adjusted based on an IQ control signal (IQ ctrl.). As previously described, in some examples, IQ ctrl. may be provided via a PI phase control circuit.

[0051] At block 515, the method 500 may continue by generating respective first and second recovered clock signals based on the input IQ clock signal. In various embodiments, the input IQ clock signal may be provided to first and second phase interpolators (PI0 and PI1). As previously described, the input IQ clock signal may be adjusted for input IQ error. In some instances, the first and second phase interpolators may be configured to have a 45 degree code offset relative to each other, corresponding to a four-phase quadrature clock input. In other instances, the first and second phase interpolators may be configured to have a code offset (relative to each other) based on the number of input phases of the input clock signal. For example, for an 8-phase clock input, the first and second phase interpolators may be configured to have a 22.5 degree code offset.

[0052] In various embodiments, each phase interpolator PI0 and PI1 may be configured to generate a corresponding recovered clock signal (e.g., a first recovered clock signal and a second recovered clock signal, respectively). The respective phases of the first and second clock signals may be shifted according to the respective PI codes. Thus, in various examples, the first phase interpolator PI0 may generate a first recovered clock signal having a first phase based on the first code. The second phase interpolator PI1 may generate a second recovered clock signal having a second phase based on the second code. Thus, the second code may be offset 45 degrees from the first code (e.g., a code that generates a 45 degree offset (e.g., a 45 degree phase shift) in the second recovered clock signal relative to the first recovered clock signal).

[0053] At block 520, the method continues by adjusting the output amplitude of the first and second phase interpolators. As described above, the output of each PI can be adjusted to minimize the amplitude phase error conversion. For example, the amplitude of the output of the PI at the code offset θ may be different from the output at the code offset θ-45°. Therefore, in some examples, the output amplitude of PI0 and PI1 can be adjusted to avoid amplitude mismatch. In some examples, each PI core (PI0, PI1) may include multiple DAC units. DAC units (e.g., current control DACs) can be segmented into groups of DAC units with different code offsets. In one set of examples, each section of the DAC unit may include three DAC units, each DAC unit having a corresponding code offset (e.g., code-45°, code and code+45°) control signal for controlling the corresponding current source. In various examples, each section of the DAC unit can be controlled by a corresponding PI code. Therefore, by combining the outputs of the corresponding DAC units of the sections, an interpolated signal can be generated, in which the amplitude mismatch at different code offsets is averaged. In this way, in some examples, a phase constellation (e.g., an octagonal constellation) with good amplitude matching can be created. In some further embodiments, an amplitude limiting buffer may be employed at the output of each of the respective PI cores to create matched output amplitudes.

[0054] At block 525, method 500 further includes merging the first and second recovered clock signals to produce a combined recovered clock. As described above, in various examples, the outputs of the first and second phase interpolators may be merged to average and eliminate the corresponding INL of the PI cores (e.g., PI0 and PI1). In some examples, as described above, the first and second recovered clock signals may be amplitude-adjusted outputs of the corresponding PI cores (PI0 and PI1). In some examples, the outputs may be merged directly at the outputs of PI0 and PI1. In other examples, the merge may be performed after the outputs of PI0 and PI1 have passed through one or more corresponding buffer stages. The merge may include, but is not limited to, summing and / or averaging the outputs of the PI cores. Therefore, by merging the outputs of the code offset phase interpolators, the INL may be averaged and / or eliminated, and timing errors and jitter may be reduced.

[0055] The techniques and processes described above with respect to various embodiments may be performed by one or more systems 100, 200 and / or their subsystems and components, such as those described above with respect to Figures 1 to 3 The variable-tolerant linear phase interpolator circuit 300 is described and may perform methods provided by various other embodiments as described herein.

[0056] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is assigned to one or more system components, unless the context dictates otherwise, this functionality may be distributed among various other system components according to several embodiments.

[0057] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, unless the context dictates otherwise, various procedures may be reordered, added, and / or omitted according to various embodiments. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to a system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without some features are described to facilitate description and explanation of aspects of these embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments, unless the context dictates otherwise. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims

1. A method comprising: obtaining one or more input clock signals; generating a first recovered clock signal via a first phase interpolator based on the one or more input clock signals and a first code; generating, via a second phase interpolator, a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; and An output of the first phase interpolator and an output of the second phase interpolator are combined, wherein when combined, the first and second recovered clock signals are combined to form a combined recovered clock signal.

2. The method according to claim 1, further comprising: The one or more input clock signals are adjusted, wherein adjusting the one or more input clock signals includes adjusting at least one of a phase or an amplitude of the at least one of the one or more input clock signals based on a multi-phase error of the at least one of the one or more input clock signals.

3. The method according to claim 1, further comprising: A respective output amplitude of at least one of the first phase interpolator and the second phase interpolator is adjusted.

4. The method of claim 3, wherein the at least one of the first phase interpolator and the second phase interpolator further comprises a plurality of digital-to-analog converters (DACs), wherein the plurality of DACs are segmented into DAC cell groups, wherein each DAC cell in a respective DAC cell group is controlled by a respective at least one of the first code or the second code, wherein adjusting the respective output amplitude comprises: At least one of the first recovered clock or the second recovered clock is generated based on the combined output of each DAC cell in a respective group of DAC cells.

5. The method of claim 3, wherein adjusting the output amplitude comprises: The voltage of the respective output of the at least one of the first and second phase interpolators is clipped via a clipping buffer.

6. The method of claim 1, wherein the interpolated code offset corresponding to the phase shift in the second recovered clock signal is a 45 degree code offset corresponding to a 45 degree phase shift in the second recovered clock signal relative to the first recovered clock signal.

7. The method of claim 1 , wherein the first phase interpolator has a first nonlinear profile relating an integral nonlinearity (INL) of the first phase interpolator to a phase interpolator code, and wherein the second phase interpolator has a second nonlinear profile relating the INL of the second phase interpolator to the phase interpolator code, wherein the second nonlinear profile is offset in phase from the first nonlinear profile by the interpolation code offset.

8. The method according to claim 7, wherein the method further comprises: The interpolation code is set via a phase interpolation circuit so that the first nonlinear profile and the second nonlinear profile are out of phase, thereby canceling the first nonlinear profile of the first phase interpolator and the second nonlinear profile of the second phase interpolator.

9. A circuit comprising: a first phase interpolator configured to obtain one or more input clock signals and generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator configured to obtain the one or more input clock signals and generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; Wherein the outputs of the first phase interpolator and the second phase interpolator are configured to be combined, wherein when combined, the first and second recovered clock signals are combined to form a combined recovered clock signal.

10. The circuit of claim 9, further comprising an input phase control circuit configured to adjust the one or more input clock signals, wherein adjusting the one or more input clock signals comprises adjusting at least one of a phase or an amplitude of the at least one of the one or more input clock signals based on a multi-phase error of at least one of the one or more input clock signals.

11. The circuit of claim 9, wherein at least one of the first and second phase interpolators further comprises a plurality of digital-to-analog converters (DACs), wherein the plurality of DACs are segmented into DAC cell groups, wherein each DAC cell in a respective DAC cell group is controlled by a respective at least one of the first code or the second code, and wherein the at least one of the first and second phase interpolators is configured to generate at least one of the first recovered clock or the second recovered clock based on a combined output of each DAC cell in a respective DAC cell group.

12. The circuit of claim 9, further comprising one or more clipping buffers configured to clip a voltage of a respective output of at least one of the first and second phase interpolators.

13. The circuit of claim 9, wherein the interpolated code offset corresponding to the phase shift in the second recovered clock signal is a 45 degree code offset corresponding to a 45 degree phase shift in the second recovered clock signal relative to the first recovered clock signal.

14. The circuit of claim 9 , wherein the first phase interpolator has a first nonlinear profile correlating an integral nonlinearity (INL) of the first phase interpolator to a phase interpolator code, and wherein the second phase interpolator has a second nonlinear profile correlating the INL of the second phase interpolator to the phase interpolator code, wherein the second nonlinear profile is offset in phase from the first nonlinear profile by the interpolation code offset, wherein the interpolation code offset is set such that the first and second nonlinear profiles are out of phase.

15. A system comprising: a sampler configured to convert an input signal into a digital output signal; a receiver phase-locked loop circuit configured to provide one or more input clock signals; a phase interpolation circuit coupled to the receiver phase locked loop circuit and the sampler, wherein the phase interpolation circuit is configured to provide a combined recovered clock signal to the sampler, wherein the phase interpolation circuit further comprises: a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code; and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolated code offset from the first code, wherein the interpolated code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal; Wherein the outputs of the first phase interpolator and the second phase interpolator are configured to be combined, wherein when combined, the first and second recovered clock signals form a combined recovered clock signal.

16. The system of claim 15, wherein the phase interpolation circuit further comprises an input phase control circuit configured to adjust the one or more input clock signals, wherein adjusting the one or more input clock signals comprises adjusting at least one of a phase or an amplitude of the at least one of the one or more input clock signals based on a multi-phase error of at least one of the one or more input clock signals.

17. The system of claim 15, wherein at least one of the first and second phase interpolators further comprises a plurality of digital-to-analog converters (DACs), wherein the plurality of DACs are segmented into DAC unit groups, wherein each DAC unit in a respective DAC unit group is controlled by a respective at least one of the first code or the second code, and wherein the at least one of the first and second phase interpolators is configured to generate at least one of the first recovered clock or the second recovered clock based on a combined output of each DAC unit in a respective DAC unit group.

18. The system of claim 15, wherein the phase interpolation circuit further comprises one or more clipping buffers configured to clip a voltage of a respective output of at least one of the first and second phase interpolators.

19. The system of claim 15, wherein the interpolated code offset corresponding to the phase shift in the second recovered clock signal is a 45 degree code offset corresponding to a 45 degree phase shift in the second recovered clock signal relative to the first recovered clock signal.

20. The system of claim 15, wherein the first phase interpolator has a first nonlinear profile correlating an integral nonlinearity (INL) of the first phase interpolator to a phase interpolator code, and wherein the second phase interpolator has a second nonlinear profile correlating the INL of the second phase interpolator to the phase interpolator code, wherein the second nonlinear profile is offset in phase from the first nonlinear profile by the interpolation code offset, wherein the interpolation code offset is set such that the first nonlinear profile and the second nonlinear profile are out of phase.

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