Audio processing device and audio processing method for dynamically adjusting audio clock

Abstract

The application discloses an audio processing device and method for dynamically adjusting an audio clock. The audio processing device comprises a first interface, a buffer, a clock generator, a processor and a second interface. The first interface receives audio data from a host. The buffer stores the audio data to generate a first audio data packet and determine the relationship between the data amount of the first audio data packet and a first upper threshold value and a first lower threshold value. The clock generator generates a clock signal. The second interface outputs the first audio data packet and the clock signal to a codec device. When the data amount of the first audio data packet is less than the first lower threshold value, the buffer outputs an underflow interrupt signal to reduce the frequency of the clock signal. When the data amount of the first audio data packet is greater than the first upper threshold value, the buffer outputs an overflow interrupt signal to increase the frequency of the clock signal.

Description

TECHNICAL FIELD

[0001] The present application relates to an audio processing device and an audio processing method, and particularly relates to an audio processing device and an audio processing method capable of dynamically adjusting an audio clock. BACKGROUND

[0002] In existing audio applications, a universal series bus (USB) is often used for audio playing. However, when using a USB audio class (Audio Device Class) output function of a USB audio device, overflow or underflow of an Inter-IC Sound (I2S) interface of the audio device is caused when a data amount of audio data transmitted by a host to the audio device does not match a bit clock (BCLK) signal of the I2S interface, so that the audio data is lost and cannot be normally played.

[0003] In detail, assuming that the BCLK signal is fixed, if the audio data transmitted by the host is delayed for a period of time, the audio device will generate an empty interrupt; if the audio data transmitted by the host is advanced for a period of time, the audio device will generate an overflow interrupt.

[0004] Therefore, a processing mechanism capable of dynamically adjusting an audio clock according to a data amount of audio data is needed. SUMMARY

[0005] The present application aims at providing an audio processing device and an audio processing method capable of dynamically adjusting an audio clock.

[0006] To solve the above technical problems, one of the technical solutions adopted by the present application is to provide an audio processing device for dynamically adjusting audio clock, which comprises a first interface, a buffer, a clock generator, a processor and a second interface. The first interface is configured to receive audio data from a host. The buffer is coupled to the first interface and is configured to store the audio data in a first sampling stage to generate a first audio data packet. The buffer is configured to determine the relationship between the data amount of the first audio data packet and a first upper threshold value and a first lower threshold value. The clock generator is configured to generate a clock signal. The processor is configured to control the clock generator to adjust the frequency of the clock signal. The second interface is coupled to the buffer and is configured to output the first audio data packet from the buffer and the clock signal from the clock generator to a codec device, so that the codec device reads the first audio data packet according to the clock signal and processes it. In response to the buffer determining that the data amount of the first audio data packet is less than the first lower threshold value, the buffer outputs an underflow interrupt signal to the processor, and the processor controls the clock generator to reduce the frequency of the clock signal according to the underflow interrupt signal. In response to the buffer determining that the data amount of the first audio data packet is greater than the first upper threshold value, the buffer outputs an overflow interrupt signal to the processor, and the processor controls the clock generator to increase the frequency of the clock signal according to the overflow interrupt signal.

[0007] To solve the above technical problems, another technical solution adopted by the present application is to provide an audio processing method for dynamically adjusting audio clock, which comprises: receiving audio data from a host through a first interface; configuring a buffer to store the audio data in a first sampling stage to generate a first audio data packet, and determining the relationship between the data amount of the first audio data packet and a first upper threshold value and a first lower threshold value; configuring a clock generator to generate a clock signal; configuring a processor to control the clock generator to adjust the frequency of the clock signal; configuring a second interface to output the first audio data packet from the buffer and the clock signal from the clock generator to a codec device, so that the codec device reads the first audio data packet according to the clock signal and processes it; in response to the buffer determining that the data amount of the first audio data packet is less than the first lower threshold value, configuring the buffer to output an underflow interrupt signal to the processor, and configuring the processor to control the clock generator to reduce the frequency of the clock signal according to the underflow interrupt signal; and in response to the buffer determining that the data amount of the first audio data packet is greater than the first upper threshold value, configuring the buffer to output an overflow interrupt signal to the processor, and configuring the processor to control the clock generator to increase the frequency of the clock signal according to the overflow interrupt signal.

[0008] One of the beneficial effects of the present application is that the audio processing device and the audio processing method provided by the present application can effectively avoid the overflow or underflow of audio data by monitoring the data amount of audio data output by the host and dynamically adjusting the clock signal, thus ensuring the integrity of audio data transmission.

[0009] In addition, the audio processing device and the audio processing method provided by the present application can appropriately increase the adjustment range when the data amount is small or large to improve efficiency, and set an upper limit value to avoid the frequency of the clock signal changing too much to cause the device to work abnormally.

[0010] To enable a further understanding of the features and technical contents of the present application, reference can be made to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 The functional block diagram of the audio processing device of an embodiment of the present application.

[0012] Figure 2 The flowchart of the audio processing method of an embodiment of the present application.

[0013] Figure 3 Another flowchart of the audio processing method of an embodiment of the present application.

[0014] Figure 4 Still another flowchart of the audio processing method of an embodiment of the present application.

[0015] Figure 5 The curve diagram of the frequency increase / decrease range of the first step function and the second step function versus the data amount of the first audio data packet. DETAILED DESCRIPTION

[0016] The following embodiments of the disclosed "audio processing device and audio processing method for dynamically adjusting audio clock" are illustrated by way of example only and other embodiments of the disclosed application can be used instead. The disclosed embodiments of the application have advantages and effects that will be apparent to those skilled in the art from the disclosure herein. The disclosed embodiments of the application can be implemented or applied in other different embodiments, and the details in the disclosure can be modified and changed in various ways based on different views and applications without departing from the spirit and scope of the disclosed application. In addition, the drawings of the disclosed application are only simple schematic illustrations and are not drawn to scale. The following embodiments will further illustrate the technical content of the disclosed application, but the disclosed content is not intended to limit the scope of protection of the disclosed application. In addition, the term "or" used herein can include a combination of any one or more of the associated listed items as appropriate.

[0017] Referring to Figure 1 As shown in the drawings, the first embodiment of the disclosed application provides an audio processing device 12 for dynamically adjusting audio clock, which is connected between a host 10 and a codec device 14. The audio processing device 12 includes a first interface 120, a buffer 122, a clock generator 124, a processor 126, and a second interface 128.

[0018] The first interface 120 can be, for example, a universal serial bus (USB) interface for receiving audio data S1 from the host 10 and coupled to the buffer 122. The second interface 128 can be, for example, an Inter-IC Sound (I2S) interface for outputting the audio data S1 to the codec device 14. In some embodiments, the host 10 can be provided in a computer, and the codec device 14 can be a speaker connected to a USB port of the computer.

[0019] The clock generator 124 can be, for example, a phase lock loop (PLL) circuit configured to generate a clock signal S2.

[0020] It should be noted that since the host 10 and the codec device 14 use independent clock signals, the host 10 can have an oscillator built-in as a clock source, and the codec device 14 uses the clock signal S2 provided by the clock generator 124 as its clock source. Therefore, the processing speed of the codec device 14 for decoding is not synchronized with the generation speed of the audio data packets, which can easily cause data overflow interruption or hole interruption, and thus generate the problem of broken sound.

[0021] Therefore, the audio processing device 12 of the disclosed application is further configured with the buffer 122, which can be, for example, a first-in-first-out (FIFO) buffer. The buffer 122 is coupled to the first interface 120 and configured to store the audio data S1 in a first sampling stage to generate a first audio data packet S3.

[0022] The second interface 128 is further coupled to the buffer 122 to output the first audio data packet S3 from the buffer 122 and the clock signal S2 from the clock generator to the codec device 14, so that the codec device 14 reads the first audio data packet S3 from the buffer 122 and processes it according to the clock signal S2.

[0023] As shown in Figure 1 , the processor 126 is configured to control the clock generator 124 to adjust the frequency of the clock signal S2 through the control signal S4. In some embodiments, the processor 126 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like, and the processor 126 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor executing other instruction sets, or a processor executing a combination of instruction sets. The processor 126 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like.

[0024] It should be noted that the present application provides a processing mechanism capable of dynamically adjusting the audio clock according to the data volume of the audio data, and is particularly implemented by the above-mentioned buffer 122, processor 126, and clock generator 124. Please further refer to Figure 2 , which is a flowchart of an audio processing method according to an embodiment of the present application.

[0025] Referring to Figure 2 , an embodiment of the present application provides an audio processing method for dynamically adjusting the audio clock, which is applicable to the host 10, the audio processing device 12, and the codec device 14 of Figure 1 , but is only an example, and the present application is not limited to the implementation manner. The audio processing method at least includes the following steps:

[0026] Step S20: receiving the audio data from the host through the first interface.

[0027] Step S21: configuring the buffer to store the audio data in the first sampling stage to generate the first audio data packet.

[0028] Step S22: configuring the buffer to determine the relationship between the first data volume (data volume 1, DV1) of the first audio data packet and the first upper threshold (1UTH) and the first lower threshold (1LTH).

[0029] It is to be noted that the 1UTH and the 1LTH can be set according to requirements. For example, the data packet size can be calculated by the following formula (1):

[0030] Data packet size = resolution (in bits) * (sampling rate / 1000) * number of channels … Formula (1);

[0031] And the following formulas (2), (3) can be used, and the 1UTH and the 1LTH can be set according to requirements:

[0032] 1UTH = data packet size * TH1 … Formula (2);

[0033] 1LTH = data packet size * TH2 … Formula (3),

[0034] Wherein, TH1 and TH2 can be critical values set by users according to requirements.

[0035] In response to the buffer determining that the data amount of the first audio data packet is less than the first lower threshold in step S22, the audio processing method proceeds to step S23 and step S24.

[0036] Step S23: configuring the buffer to output an underflow interrupt signal to the processor.

[0037] Step S24: configuring the processor to control the clock generator to reduce the frequency of the clock signal according to the underflow interrupt signal.

[0038] In response to the buffer determining that the data amount of the first audio data packet is greater than the first upper threshold in step S22, the audio processing method proceeds to step S25 and step S26.

[0039] Step S25: configuring the buffer to output an overflow interrupt signal to the processor.

[0040] Step S26: configuring the processor to control the clock generator to increase the frequency of the clock signal according to the overflow interrupt signal.

[0041] In response to the buffer determining that the data amount of the first audio data packet is between the first upper threshold and the first lower threshold in step S22, it means that overflow or underflow will not occur, and the audio processing method proceeds to step S27: maintaining the frequency of the clock signal.

[0042] Therefore, in the above process, the buffer can monitor the data amount of the audio data output by the host, and the clock signal can be dynamically adjusted accordingly, which can effectively avoid the occurrence of audio data overflow or underflow, and ensure the integrity of audio data transmission.

[0043] However, in the above procedure, the hysteresis after adjusting the clock signal needs to be further considered to avoid over-adjusting the frequency of the clock signal, resulting in the data volume of the first audio data packet always failing to correctly locate between the first upper threshold and the first lower threshold.

[0044] Reference can be made to Figure 3 which is another flowchart of the audio processing method of an embodiment of the present application. Continuing from steps S24, S26 of Figure 2 the audio processing method further comprises the following steps:

[0045] Step S30: configuring the buffer to store the audio data in the second sampling stage to generate a second audio data packet.

[0046] Unlike the procedure of Figure 2 the difference is that, Figure 3 the audio processing method of the present application is to enter step S31: configuring the processor to determine whether the data volume (DV2) of the second audio data packet is different from the data volume (DV1) of the first audio data packet after the frequency of the clock signal is adjusted by the processor according to the underflow interrupt signal or the overflow interrupt signal before the processor controls the clock generator to adjust the frequency of the clock signal.

[0047] If yes, enter step S32: configuring the processor to ignore the underflow interrupt signal or the overflow interrupt signal corresponding to the second audio data packet. In this way, the protection mechanism can be used to avoid over-adjusting the frequency of the clock signal, resulting in the data volume of the first audio data packet always failing to correctly locate between the first upper threshold and the first lower threshold.

[0048] If no, enter step S33: configuring the processor to control the clock generator to adjust the clock signal according to the underflow interrupt signal or the overflow interrupt signal corresponding to the second audio data packet.

[0049] Step S34: determining the relationship between the data volume (data volume 2, DV2) of the second audio data packet and the first upper threshold (1UTH) and the first lower threshold (1LTH).

[0050] Similar to step S22, when the buffer determines that the data volume of the second audio data packet is less than the first lower threshold, enter step S35: the buffer outputs the underflow interrupt signal to the processor. When the buffer determines that the data volume of the second audio data packet is greater than the first upper threshold, enter step S36: the buffer outputs the overflow interrupt signal to the processor. It should be noted that steps S35 and S36 still maintain the mechanism of the buffer detecting the data volume of the audio data packet.

[0051] Reference can be made to Figure 4 and Figure 5 . Figure 4This is another flowchart of an audio processing method according to an embodiment of the present invention. Figure 5 This is a graph showing the frequency rise / fall of the first step distance function and the second step distance function in accordance with the data volume of the first audio data packet, according to an embodiment of the present invention.

[0052] like Figure 4 As shown, after step S23, in response to receiving an underflow interrupt signal, the audio processing method proceeds to step S40: configuring the processor to substitute the data amount of the first audio data packet into the first step distance function to calculate the frequency drop of the clock signal, and controlling the clock generator according to the frequency drop.

[0053] by Figure 5 For example, when DV1 is between the first lower threshold (1LTH) and the second lower threshold (2LTH), the frequency reduction calculated by the first step distance function f1(DV1) is the first amplitude Step1. When DV1 is between the second lower threshold (2LTH) and the third lower threshold (3LTH), the frequency reduction calculated by the first step distance function f1(DV1) increases linearly, rising from the first amplitude Step1 to the second amplitude Step2. When DV1 is less than the third lower threshold (3LTH), the frequency reduction calculated by the first step distance function f1(DV1) no longer increases. In other words, this invention further limits the frequency reduction calculated by the first step distance function f(DV1) to no greater than the upper limit of the frequency reduction (the second amplitude Step2). Therefore, when the data volume is small, the adjustment amplitude (reduction) can be appropriately increased to improve efficiency, while an upper limit is set to avoid excessive frequency fluctuations of the clock signal causing abnormal device operation.

[0054] On the other hand, after step S25, in response to receiving an overflow interrupt signal, the audio processing method proceeds to step S41: configuring the processor to substitute the data amount of the first audio data packet into the second step function to calculate the frequency rise of the clock signal, and controlling the clock generator according to the frequency rise.

[0055] Similarly, with Figure 5For example, when DV1 is between the first upper threshold 1UTH and the second upper threshold 2UTH, the frequency increase calculated by the second step function f2(DV1) is the first amplitude Step1; when DV1 is between the second upper threshold 2UTH and the third upper threshold 3UTH, the frequency increase calculated by the second step function f2(DV1) is linearly increased, and is increased from the first amplitude Step1 to the second amplitude Step2; when DV1 is greater than the third upper threshold 3UTH, the frequency increase calculated by the second step function f2(DV1) is no longer increased. In other words, the application further limits the frequency increase calculated by the second step function f2(DV1) to be no greater than the upper limit of the frequency increase (the second amplitude Step2). Therefore, when the data volume is large, the adjustment amplitude (the increase) can be appropriately increased to improve efficiency, and the upper limit value is also set to avoid the frequency of the clock signal changing too much to cause the device to work abnormally.

[0056] Therefore, after the steps S40, S41, the process can return to the step S30 to perform the subsequent protection mechanism.

[0057] Advantages of the embodiments

[0058] One of the advantages of the application is that the audio processing device and the audio processing method for dynamically adjusting the audio clock can effectively avoid the overflow or underflow of the audio data by monitoring the data volume of the audio data output by the host and dynamically adjusting the clock signal, and ensure the integrity of the audio data transmission.

[0059] In addition, the audio processing device and the audio processing method for dynamically adjusting the audio clock can appropriately increase the adjustment amplitude when the data volume is small or large to improve efficiency, and set the upper limit value to avoid the frequency of the clock signal changing too much to cause the device to work abnormally.

[0060] The above disclosure is only the preferred and feasible embodiments of the application, and does not limit the patent application range of the application, so any equivalent technical changes made according to the content of the application specification and drawings are included in the patent application range of the application.

[0061] Explanation of reference signs:

[0062] 10: host

[0063] 12: audio processing device

[0064] 14: codec device

[0065] 120: first interface

[0066] 122: buffer

[0067] 124: clock generator

[0068] 126: processor

[0069] 128: second interface

[0070] 1LTH: first lower threshold

[0071] 1UTH: first upper threshold

[0072] 2LTH: second lower threshold

[0073] 2UTH: second upper threshold

[0074] 3LTH: third lower threshold

[0075] 3UTH: third upper threshold

[0076] f1(DV1): first step function

[0077] f2(DV1): second step function

[0078] S1: audio data

[0079] S2: clock signal

[0080] S3: first audio data packet

[0081] S4: control signal

[0082] Step1: first amplitude

[0083] Step2: second amplitude

Claims

1. An audio processing device for dynamically adjusting an audio clock, comprising: a first interface configured to receive audio data from a host; a buffer coupled to the first interface and configured to store the audio data in a first sampling phase to generate a first audio data packet, wherein the buffer is configured to determine a relationship between a data amount of the first audio data packet and a first upper threshold and a first lower threshold; a clock generator configured to generate a clock signal; a processor configured to control the clock generator to adjust a frequency of the clock signal; a second interface coupled to the buffer and configured to output the first audio data packet from the buffer and the clock signal from the clock generator to a codec device, such that the codec device reads and processes the first audio data packet according to the clock signal, wherein in response to the buffer determining that the data amount of the first audio data packet is less than the first lower threshold, the buffer outputs an underflow interrupt signal to the processor, and the processor controls the clock generator to decrease the frequency of the clock signal according to the underflow interrupt signal, wherein in response to the buffer determining that the data amount of the first audio data packet is greater than the first upper threshold, the buffer outputs an overflow interrupt signal to the processor, and the processor controls the clock generator to increase the frequency of the clock signal according to the overflow interrupt signal.

2. The audio processing device of claim 1, wherein, the buffer is further configured to store the audio data in a second sampling phase to generate a second audio data packet, wherein the buffer is configured to determine a relationship between a data amount of the second audio data packet and the first upper threshold and the first lower threshold, wherein in response to the buffer determining that the data amount of the second audio data packet is less than the first lower threshold, the buffer outputs the underflow interrupt signal to the processor, wherein in response to the buffer determining that the data amount of the second audio data packet is greater than the first upper threshold, the buffer outputs the overflow interrupt signal to the processor.

3. The audio processing device of claim 2, wherein, before the processor controls the clock generator to adjust the frequency of the clock signal according to the underflow interrupt signal or the overflow interrupt signal, the processor is further configured to determine whether the data amount of the second audio data packet is different from the data amount of the first audio data packet after the clock signal is adjusted, and if so, the processor ignores the underflow interrupt signal or the overflow interrupt signal corresponding to the second audio data packet.

4. The audio processing device of claim 1, wherein, in response to receiving the underflow interrupt signal, the processor is further configured to substitute the data amount of the first audio data packet into a first step function to calculate a frequency decrease of the clock signal, and to control the clock generator according to the frequency decrease, wherein in response to receiving the overflow interrupt signal, the processor is further configured to substitute the data amount of the first audio data packet into a second step function to calculate a frequency increase of the clock signal, and to control the clock generator according to the frequency increase.

5. The audio processing device of claim 4, wherein, the frequency decrease is not greater than an upper limit of frequency decrease, and the frequency increase is not greater than an upper limit of frequency increase.

6. The audio processing device of claim 1, wherein the buffer is a first-in-first-out buffer.

7. The audio processing device of claim 1, wherein, the first interface is a universal serial bus interface.

8. The audio processing device of claim 1, wherein, the second interface is an inter-integrated circuit audio interface.

9. An audio processing method for dynamically adjusting an audio clock, comprising: receiving audio data from a host through a first interface; configuring a buffer to store the audio data in a first sampling stage to generate a first audio data packet, and determining a relationship between a data amount of the first audio data packet and a first upper threshold and a first lower threshold; configuring a clock generator to generate a clock signal; configuring a processor to control the clock generator to adjust a frequency of the clock signal; configuring a second interface to output the first audio data packet from the buffer and the clock signal from the clock generator to a codec device, so that the codec device reads and processes the first audio data packet according to the clock signal; in response to the buffer determining that the data amount of the first audio data packet is less than the first lower threshold, configuring the buffer to output an underflow interrupt signal to the processor, and configuring the processor to control the clock generator to decrease the frequency of the clock signal according to the underflow interrupt signal; and in response to the buffer determining that the data amount of the first audio data packet is greater than the first upper threshold, configuring the buffer to output an overflow interrupt signal to the processor, and configuring the processor to control the clock generator to increase the frequency of the clock signal according to the overflow interrupt signal.

10. The audio processing method of claim 9, further comprising: configuring the buffer to store the audio data in a second sampling stage to generate a second audio data packet, and determining a relationship between a data amount of the second audio data packet and the first upper threshold and the first lower threshold; in response to the buffer determining that the data amount of the second audio data packet is less than the first lower threshold, the buffer outputting the underflow interrupt signal to the processor; and in response to the buffer determining that the data amount of the second audio data packet is greater than the first upper threshold, the buffer outputting the overflow interrupt signal to the processor. ​

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