Method for forming a mask and a chip

Abstract

A method for forming a photomask and a chip, wherein the photomask includes: a plurality of central exposure areas, each central exposure area including a plurality of central circuit patterns; a plurality of peripheral exposure areas, each peripheral exposure area including a dicing exposure area and a first splicing exposure area surrounding the dicing exposure area, the first splicing exposure area including a first splicing exposure edge area and a second splicing exposure edge area located on opposite sides of the dicing exposure area; a first identifier located in the first splicing exposure edge area and a second identifier located in the second splicing exposure edge area, the second identifier and the first identifier corresponding to each other, the size of the formed chip is not limited by the size of the photomask, improving the manufacturing capability of large-size chips, and can also form complete and regularly distributed overlay alignment marks in the dicing area of ​​the formed chip for overlay accuracy detection of the device, improving the overlay level.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a photomask and a chip. Background Technology

[0002] Due to the diversified needs of current chip applications, large-area chips are often required. For example, the application fields of large-area CMOS image sensors are becoming increasingly widespread. In high-end applications such as medical and industrial X-ray flat panel detectors and scientific research, the demand for large-area image sensors is increasing.

[0003] When the chip size exceeds the maximum size of the photomask (i.e., the maximum exposure size of a single lithography machine, typically less than 3cm × 3cm), it cannot be obtained using conventional single-step lithography processes. In this case, a multi-regional lithography stitching process is required. This stitching process refers to dividing the chip pattern into sections during chip manufacturing, using several smaller photomasks for multiple step-by-step exposures, and finally stitching them together to form a larger chip.

[0004] However, existing technologies for forming large-size chips using splicing processes need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a photomask and a chip, so as to improve the performance of the formed chip.

[0006] To solve the above-mentioned technical problems, the present invention provides a photomask, comprising: a plurality of central exposure areas, each central exposure area including a plurality of central circuit patterns; a plurality of peripheral exposure areas, each peripheral exposure area including a cut-out exposure area and a first splicing exposure area surrounding the cut-out exposure area, the first splicing exposure area including a first splicing exposure edge area and a second splicing exposure edge area respectively located on opposite sides of the cut-out exposure area; a first identifier located in the first splicing exposure edge area and a second identifier located in the second splicing exposure edge area, the second identifier and the first identifier corresponding to each other.

[0007] Optionally, it also includes: a light-shielding strip located between two adjacent central exposure areas, two adjacent peripheral exposure areas, and between adjacent central exposure areas and peripheral exposure areas.

[0008] Optionally, the material of the light-shielding strip includes chromium.

[0009] Optionally, the width of the light-shielding strip ranges from 750 μm to 1500 μm.

[0010] Optionally, the peripheral exposure area further includes a peripheral circuit exposure area, which is located on both sides of the cutting track exposure area and between the cutting track exposure area and the first splicing exposure area. The peripheral circuit exposure area includes several peripheral circuit patterns.

[0011] Optionally, each central exposure area may further include a second splicing exposure area located around the plurality of central circuit patterns. The second splicing exposure area includes a third splicing exposure edge area and a fourth splicing exposure edge area. A third identifier is located in the third splicing exposure edge area, and a fourth identifier is located in the fourth splicing exposure edge area. The fourth identifier and the third identifier correspond to each other.

[0012] Accordingly, the present invention also provides a chip forming method, comprising: providing a wafer to be processed, the wafer to be processed comprising a plurality of chip regions, each chip region comprising a plurality of repeatedly distributed core circuit setting regions and a plurality of repeatedly distributed external circuit setting regions, each of the external circuit setting regions comprising a dicing region, and adjacent dicing regions having a first splicing region; providing a mask, the mask comprising: a plurality of central exposure regions, each central exposure region comprising a plurality of central circuit patterns; a plurality of peripheral exposure regions, each of the peripheral exposure regions comprising a dicing exposure region and a first splicing exposure region located around the dicing exposure region, the first splicing exposure region comprising a first splicing exposure edge region and a second splicing exposure edge region respectively located on opposite sides of the dicing exposure region; a first identifier located in the first splicing exposure edge region and a second identifier located in the second splicing exposure edge region, the second identifier and the first identifier corresponding to each other; performing multiple exposure processing on the wafer to be processed using the mask, forming a central circuit pattern in the core circuit setting region, forming a peripheral circuit pattern in the external circuit setting region, and forming a first set of alignment marks in the first splicing region.

[0013] Optionally, the method for forming the first set of alignment marks in the first stitching area includes: forming a first mark pattern in the first stitching area after a first exposure process; and forming a second mark pattern in the first stitching area after a second exposure process, wherein the second mark pattern coincides with the first mark pattern.

[0014] Optionally, the method for forming the first set of alignment marks in the first stitching area includes: forming a first mark pattern in the first stitching area after the first exposure process; and forming a second mark pattern in the first stitching area after the second exposure process, wherein the second mark pattern is adjacent to the first mark pattern.

[0015] Optionally, the mask further includes: the peripheral exposure area further includes a peripheral circuit exposure area, the peripheral circuit exposure area is located on both sides of the cut track exposure area and between the cut track exposure area and the first splicing exposure area, the peripheral circuit exposure area includes a plurality of peripheral circuit patterns.

[0016] Optionally, the mask further includes: each central exposure area also includes a second splicing exposure area located around the plurality of central circuit patterns, the second splicing exposure area including a third splicing exposure edge area and a fourth splicing exposure edge area; a third identifier is located in the third splicing exposure edge area and a fourth identifier is located in the fourth splicing exposure edge area, the fourth identifier and the third identifier corresponding to each other.

[0017] Optionally, a second splicing area is provided between adjacent core circuit setting areas, and the method further includes: forming a second set of engraving alignment marks in the second splicing area after the multiple exposure process.

[0018] Optionally, the method for forming the second set of alignment marks in the second stitching area includes: forming a third mark pattern in the second stitching area after a third exposure process; and forming a fourth mark pattern in the second stitching area after a fourth exposure process, wherein the third mark pattern and the fourth mark pattern coincide.

[0019] Optionally, the method for forming the second set of alignment marks in the second stitching area includes: forming a third mark pattern in the second stitching area after a third exposure process; and forming a fourth mark pattern in the second stitching area after a fourth exposure process, wherein the fourth mark pattern is adjacent to the third mark pattern.

[0020] Optionally, the width of the first splicing area ranges from 0.1 μm to 0.5 μm.

[0021] Optionally, the central circuit pattern is formed by the plurality of central exposure areas of the mask, and the peripheral circuit pattern is formed by the plurality of peripheral exposure areas of the mask.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] The mask provided by this invention, on the one hand, divides the mask into several central exposure areas and several peripheral exposure areas. Using one mask, different exposure areas are selected to expose the wafer separately, forming a region of the target chip and ultimately forming a large-size chip. The size of the formed chip is not limited by the size of the mask, thus improving the manufacturing capability of large-size chips. On the other hand, the first splicing exposure area includes a first splicing exposure edge area and a second splicing exposure edge area located on opposite sides of the dicing exposure area. A first mark is set in the first splicing exposure edge area, and a second mark is set in the second splicing exposure edge area. The second mark and the first mark correspond to each other. After multiple exposures using the mask, complete and regularly distributed overlay alignment marks can be formed in the dicing area of ​​the formed chip, which is used to detect the overlay accuracy of the device and improve the overlay level.

[0024] Furthermore, the setting of the light-shielding strip can reduce the occurrence of light diffraction caused by the edge of the baffle above the mask during the exposure process, which would lead to the exposure of non-exposed areas.

[0025] Furthermore, each central exposure area also includes a second splicing exposure area located around the plurality of central circuit patterns. The second splicing exposure area includes opposing third and fourth splicing exposure edge areas. A third identifier is located within the third splicing exposure edge area, and a fourth identifier is located within the fourth splicing exposure edge area. The fourth identifier and the third identifier correspond to each other. The third and fourth identifiers can form a second set of alignment marks for the chip's core circuit setting area.

[0026] In the chip formation method provided by the present invention, a mask is used, and different exposure areas are selected to expose the wafer to form a region of the target chip, ultimately forming a large-size chip. The size of the formed chip is not limited by the size of the mask, thus improving the manufacturing capability of large-size chips. In addition, after multiple exposures using the mask, a complete and regularly distributed first set of alignment marks can be formed in the dicing area of ​​the formed chip, which is used to detect the alignment accuracy of the device and improve the alignment level.

[0027] Furthermore, the method for forming the second set of alignment marks in the second splicing area includes: forming a third mark pattern in the second splicing area after the third exposure process; forming a fourth mark pattern in the second splicing area after the fourth exposure process, wherein the third mark pattern and the fourth mark pattern coincide. The second splicing area adopts a two-exposure formation method, which is beneficial to improve the connection of the circuits in two adjacent core circuit setting areas and avoid the occurrence of situations such as metal wire breakage caused by poor splicing. Attached Figure Description

[0028] Figure 1 This is a flowchart of the steps of a chip forming method according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0030] Figures 3 to 7 This is a schematic diagram of the structure of each step in a chip forming method according to an embodiment of the present invention;

[0031] Figures 8 to 9 This is a schematic diagram of the structure of each step in the method for forming the second set of alignment marks according to another embodiment of the present invention. Detailed Implementation

[0032] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0033] As described in the background section, existing technologies for forming large-size chips using splicing processes need further improvement.

[0034] The method for forming a chip using a mask provided by this invention, on the one hand, divides the mask into several central exposure areas and several peripheral exposure areas. Using a single mask, different exposure areas are selected to expose the wafer, forming a region of the target chip and ultimately forming a large-size chip. The size of the formed chip is not limited by the size of the mask, thus improving the manufacturing capability of large-size chips. On the other hand, the first splicing exposure area includes a first splicing exposure edge area and a second splicing exposure edge area located on opposite sides of the dicing exposure area. A first mark is set in the first splicing exposure edge area, and a second mark is set in the second splicing exposure edge area. The second mark and the first mark correspond to each other. After multiple exposures using the mask, complete and regularly distributed overlay alignment marks can be formed in the dicing area of ​​the formed chip, which is used to detect the overlay accuracy of the device and improve the overlay level.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a flowchart of the steps of a chip forming method according to an embodiment of the present invention.

[0037] Please refer to Figure 1 The method for forming the chip includes the following steps:

[0038] Step S101: Provide a wafer to be processed. The wafer to be processed includes a plurality of chip regions. Each chip region includes a plurality of repeatedly distributed core circuit setting regions and a plurality of repeatedly distributed external circuit setting regions. Each external circuit setting region includes a dicing channel region and a first splicing region located around the dicing channel region.

[0039] Step S102: Provide a photomask, the photomask comprising: a plurality of central exposure areas, each central exposure area comprising a plurality of central circuit patterns; a plurality of peripheral exposure areas, each peripheral exposure area comprising a cut-out exposure area and a first splicing exposure area surrounding the cut-out exposure area, the first splicing exposure area comprising a first splicing exposure edge area and a second splicing exposure edge area respectively located on opposite sides of the cut-out exposure area; a first identifier located in the first splicing exposure edge area and a second identifier located in the second splicing exposure edge area, the second identifier and the first identifier corresponding to each other;

[0040] Step S103: The wafer to be processed is subjected to multiple exposures using the mask to form a central circuit pattern in the core circuit setting area, a peripheral circuit pattern in the outer circuit setting area, and a first set of alignment marks in the first splicing area.

[0041] The following will be described in detail with reference to the accompanying drawings.

[0042] Figure 2 This is a schematic diagram of the structure of a chip according to an embodiment of the present invention.

[0043] Please refer to Figure 2 Please continue to refer to Figure 1 The present invention provides a wafer to be processed, the wafer to be processed includes a plurality of chip regions, each chip region including a plurality of repeatedly distributed core circuit setting regions 301 and a plurality of repeatedly distributed external circuit setting regions 302, each external circuit setting region 302 including a dicing channel region 303, and a first splicing region 304 between adjacent dicing channel regions 303.

[0044] The technical solution of this invention can manufacture chips larger than the mask size, and can achieve wafer-level large-size chips. The method is used to form devices such as image sensors and memory that can be divided into several repeating units.

[0045] Specifically, the chip area shown in this embodiment includes four core circuit setting areas 301 located in the center of the chip area and twelve external circuit setting areas 302 surrounding the core circuit setting areas 301. The twelve external circuit setting areas 302, based on their positional distribution, can be divided into three types of repeating units located in the long side area I, corner area II, and short side area III. The division of each region within each chip area is based on the actual repeating unit category; however, the division method is not limited to this. In other embodiments, the division can be carried out according to actual needs.

[0046] In this embodiment, the width of the first splicing area 304 ranges from 0.1μm to 0.5μm.

[0047] In this embodiment, each of the external circuit setting areas 302 includes an external circuit 305, which is located on both sides of the cutting channel area 303. Specifically, a third splicing area 307 is also provided between the external circuit 305 and the core circuit setting area 301.

[0048] In this embodiment, the width of the third splicing area 307 ranges from 0.1μm to 0.5μm.

[0049] In this embodiment, a second splicing area 306 is provided between adjacent core circuit setting areas 301.

[0050] In this embodiment, the width of the second splicing area 306 ranges from 0.1μm to 0.5μm.

[0051] It should be noted that only one chip area is shown in this embodiment, which is used to form an image sensor.

[0052] Figures 3 to 7 This is a schematic diagram of the structure of each step in a chip formation method according to an embodiment of the present invention.

[0053] Please refer to Figures 3 to 5 And continue to refer to Figure 1 , Figure 3 This is a schematic diagram of a photomask. Figure 4 for Figure 3 A partial schematic diagram at point 11 (the middle dashed line). Figure 5 for Figure 3A partial schematic diagram at point 22 (dashed line) shows a photomask. The photomask includes: several central exposure areas 200, each central exposure area 200 including several central circuit patterns 201; several peripheral exposure areas 202, each peripheral exposure area 202 including a cut-out exposure area 203 and a first splicing exposure area 204 surrounding the cut-out exposure area 203. The first splicing exposure area 204 includes a first splicing exposure edge area 205a and a second splicing exposure edge area 205b located on opposite sides of the cut-out exposure area 203, respectively. A first identifier A is located in the first splicing exposure edge area 205a, and a second identifier B is located in the second splicing exposure edge area 205b, with the second identifier B corresponding to the first identifier A.

[0054] The fact that the second identifier B and the first identifier A correspond to each other means that the second identifier B and the first identifier A can form a complete overlay alignment mark.

[0055] In this embodiment, corresponding to the division of the chip area shown, the mask includes a central exposure area 200 and three peripheral exposure areas 202, wherein the three peripheral exposure areas 202 include peripheral exposure area I', peripheral exposure area II' and peripheral exposure area III'. The central exposure area 200 is used to form the core circuit setting area 301 of the chip area, and the peripheral exposure areas I', II' and III' are distributed to form the external circuit setting areas 302 of the long side area I, corner area II and short side area III of the chip area.

[0056] In this embodiment, the mask further includes: the peripheral exposure area 202 further includes a peripheral circuit exposure area 206, the peripheral circuit exposure area 206 is located on both sides of the cutting track exposure area 203, and is located between the cutting track exposure area 203 and the first splicing exposure area 204, the peripheral circuit exposure area 206 includes a plurality of peripheral circuit patterns (not shown in the figure).

[0057] In this embodiment, the mask further includes: each central exposure area 200 also includes a second splicing exposure area 207 located around the plurality of central circuit patterns, the second splicing exposure area 207 including a third splicing exposure edge area 208a and a fourth splicing exposure edge area 208b; a third identifier C is located in the third splicing exposure edge area 208a, and a fourth identifier D is located in the fourth splicing exposure edge area 208b, the fourth identifier D and the third identifier C correspond to each other.

[0058] Specifically, in this embodiment, there is only one central exposure area 200. The plurality of central exposure areas are used to form the core circuit setting area; in other embodiments, the number of central exposure areas is not limited to this.

[0059] The fact that the fourth identifier D and the third identifier C correspond to each other means that the fourth identifier D and the third identifier C can form a complete overlay alignment mark.

[0060] In this embodiment, the mask includes: a light-shielding strip 209, located between two adjacent central exposure areas 200, two adjacent peripheral exposure areas 202, and between adjacent central exposure areas 200 and peripheral exposure areas 202.

[0061] When exposing a wafer to a certain area using a photomask, a baffle needs to be added above the area that does not need to be exposed to block it. The light-blocking strip 209 can reduce the situation where light diffraction occurs at the edge of the baffle above the photomask during the exposure process, causing the non-exposed area to be exposed.

[0062] The material of the light-shielding strip 209 includes chromium.

[0063] The width of the light-shielding strip 209 ranges from 750 μm to 1500 μm.

[0064] Please continue to refer to this. Figure 1 and Figure 2 The wafer to be processed is subjected to multiple exposures using the mask, forming a central circuit pattern (not shown in the figure) in the core circuit setting area 301, a peripheral circuit pattern (not shown in the figure) in the outer circuit setting area 302, and a first set of alignment marks 308 in the first splicing area 304.

[0065] Specifically, the mask is used to perform multiple exposure processes on each of the chip areas to form a central circuit pattern (not shown in the figure) in the core circuit setting area 301 and a peripheral circuit pattern (not shown in the figure) in the outer circuit setting area 302. The central circuit pattern is formed by the plurality of central exposure areas 200 of the mask, and the peripheral circuit pattern is formed by the plurality of peripheral exposure areas 202 of the mask.

[0066] The mask is divided into several central exposure areas 200 and several peripheral exposure areas 202. Using one mask, different exposure areas are selected to expose the wafer to form a region of the target chip, and finally a large-size chip is formed. The size of the formed chip is not limited by the size of the mask, which improves the manufacturing capability of large-size chips.

[0067] After multiple exposures, a complete and regularly distributed first set of alignment marks can be formed in the dicing area of ​​the chip, which is used to detect the alignment accuracy of the device and improve the alignment level.

[0068] In this embodiment, the method for forming the first set of alignment marks 308 in the first stitching area 304 includes: after the first exposure process, forming a first mark pattern in the first stitching area 304; after the second exposure process, forming a second mark pattern in the first stitching area 304, wherein the second mark pattern coincides with the first mark pattern.

[0069] In another embodiment, the method for forming the first set of alignment marks in the first stitching area includes: forming a first mark pattern in the first stitching area after a first exposure process; and forming a second mark pattern in the first stitching area after a second exposure process, wherein the second mark pattern is adjacent to the first mark pattern.

[0070] In this embodiment, after the multiple exposure process, a second set of alignment marks 309 are also formed in the second splicing area 306.

[0071] In this embodiment, the method for forming the second set of alignment marks in the second stitching area 306 includes: forming a third mark pattern in the second stitching area 306 after the third exposure process; and forming a fourth mark pattern in the second stitching area 306 after the fourth exposure process, wherein the third mark pattern and the fourth mark pattern coincide.

[0072] The second splicing area 306 is formed by two exposures, which helps to improve the connection of the circuits in the two adjacent core circuit setting areas and avoids the occurrence of situations such as broken metal wires due to poor splicing.

[0073] In another embodiment, the method for forming the second set of alignment marks in the second stitching area includes: forming a third mark pattern in the second stitching area after a third exposure process; and forming a fourth mark pattern in the second stitching area after a fourth exposure process, wherein the fourth mark pattern is adjacent to the third mark pattern.

[0074] Accordingly, embodiments of the present invention also provide a mask used to form the above-mentioned chip, please refer to... Figure 3 It includes: a plurality of central exposure areas 200, each central exposure area 200 including a plurality of central circuit patterns 201; a plurality of peripheral exposure areas 202, each peripheral exposure area 202 including a cut-out exposure area 203 and a first splicing exposure area 204 surrounding the cut-out exposure area 203, the first splicing exposure area 204 including a first splicing exposure edge area 205a and a second splicing exposure edge area 205b located on opposite sides of the cut-out exposure area 203; a first identifier A is located in the first splicing exposure edge area 205a, and a second identifier B is located in the second splicing exposure edge area 205b, the second identifier B and the first identifier A correspond to each other.

[0075] On the one hand, the mask is divided into several central exposure areas 200 and several peripheral exposure areas 202. Using one mask, different exposure areas are selected to expose the wafer separately to form a region of the target chip, ultimately forming a large-size chip. The size of the formed chip is not limited by the size of the mask, thus improving the manufacturing capability of large-size chips. On the other hand, after multiple exposures using the mask, a complete and regularly distributed first set of alignment marks can be formed in the dicing area of ​​the formed chip, which is used to detect the overlay accuracy of the device and improve the overlay level.

[0076] In this embodiment, the mask includes: a light-shielding strip 209, located between two adjacent central exposure areas 200, two adjacent peripheral exposure areas 202, and between adjacent central exposure areas 200 and peripheral exposure areas 202.

[0077] The setting of the light-shielding strip 209 can reduce the occurrence of light diffraction caused by the edge of the baffle above the mask during the exposure process, which would lead to the exposure of the non-exposed area.

[0078] The material of the light-shielding strip 209 includes chromium.

[0079] The width of the light-shielding strip 209 ranges from 750 μm to 1500 μm.

[0080] In this embodiment, the peripheral exposure area 202 further includes a peripheral circuit exposure area 206, which is located on both sides of the cutting track exposure area 203 and between the cutting track exposure area 203 and the first splicing exposure area 204. The peripheral circuit exposure area 206 includes a plurality of peripheral circuit patterns (not shown in the figure).

[0081] In this embodiment, the mask further includes: each central exposure area 200 also includes a second splicing exposure area 207 located around the plurality of central circuit patterns, the second splicing exposure area 207 including a third splicing exposure edge area 208a and a fourth splicing exposure edge area 208b; a third identifier C is located in the third splicing exposure edge area 208a, and a fourth identifier D is located in the fourth splicing exposure edge area 208b, the fourth identifier D and the third identifier C correspond to each other.

[0082] The third and fourth marks can form the second set of alignment marks for the core circuit setting area of ​​the chip, which is beneficial for alignment detection near the circuit.

[0083] Figures 8 to 9 This is a schematic diagram of the structure of each step in the method for forming the second set of alignment marks according to another embodiment of the present invention.

[0084] The difference between this embodiment and the previous embodiment is that the way the fourth identifier and the third identifier correspond to each other in the provided mask is different; and the method of forming the second set of engraving alignment marks in the second splicing area is different.

[0085] Please refer to Figure 8 The mask is provided, including: the second stitching exposure area includes a third stitching exposure edge area 408a and a fourth stitching exposure edge area 408b; a third identifier E is located in the third stitching exposure edge area 408a, and a fourth identifier F is located in the fourth stitching exposure edge area 408b, the fourth identifier F and the third identifier E correspond to each other.

[0086] This embodiment only shows one shape of the identifier, and it may not be limited to this in actual use.

[0087] The difference between this embodiment and the previous embodiment also includes that the way the first identifier and the second identifier correspond to each other is different. For the way the first identifier and the second identifier correspond to each other, please refer to the way the fourth identifier F and the third identifier E correspond to each other, which will not be repeated here.

[0088] Please Figure 2 Continue to refer to Figure 9 The method for forming the second set of alignment marks 500 in the second stitching area 306 includes: forming a third mark pattern in the second stitching area 306 after a third exposure process; and forming a fourth mark pattern in the second stitching area 306 after a fourth exposure process, wherein the fourth mark pattern is adjacent to the third mark pattern.

[0089] In this embodiment, the method for forming the first set of engraving alignment marks in the first splicing area is the same as the method for forming the second set of engraving alignment marks, and will not be repeated here.

[0090] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photomask, characterized in that, include: A plurality of central exposure areas, the central exposure areas including a plurality of central circuit patterns, and a second splicing exposure area located around the plurality of central circuit patterns, the second splicing exposure area including a third splicing exposure edge area and a fourth splicing exposure edge area; A third identifier is located within the third stitching exposure edge area, and a fourth identifier is located within the fourth stitching exposure edge area, with the fourth identifier and the third identifier corresponding to each other; a plurality of peripheral exposure areas, each of the peripheral exposure areas including a cutting track exposure area and a first stitching exposure area surrounding the cutting track exposure area, the first stitching exposure area including a first stitching exposure edge area and a second stitching exposure edge area located on opposite sides of the cutting track exposure area respectively; The first identifier is located within the first stitching exposure edge area, and the second identifier is located within the second stitching exposure edge area, with the second identifier corresponding to the first identifier.

2. The photomask as described in claim 1, characterized in that, Also includes: The light-shielding strip is located between two adjacent central exposure areas, two adjacent peripheral exposure areas, and between adjacent central exposure areas and peripheral exposure areas.

3. The photomask as described in claim 2, characterized in that, The material of the light-shielding strip includes chromium.

4. The photomask as described in claim 2, characterized in that, The width of the light-shielding strip ranges from 750 µm to 1500 µm.

5. The photomask as described in claim 1, characterized in that, The peripheral exposure area also includes a peripheral circuit exposure area, which is located on both sides of the cutting track exposure area and between the cutting track exposure area and the first splicing exposure area. The peripheral circuit exposure area includes several peripheral circuit patterns.

6. A method for forming a chip, characterized in that, include: A wafer to be processed is provided, the wafer to be processed includes a plurality of chip regions, each chip region includes a plurality of repeatedly distributed core circuit setting regions and a plurality of repeatedly distributed external circuit setting regions, each of the external circuit setting regions includes a dicing channel region, and adjacent dicing channel regions have a first splicing area. A photomask is provided, comprising: a plurality of central exposure areas, each central exposure area including a plurality of central circuit patterns, and a second splicing exposure area surrounding the plurality of central circuit patterns, the second splicing exposure area including opposing third splicing exposure edge areas and fourth splicing exposure edge areas; a third identifier is located within the third splicing exposure edge area, and a fourth identifier is located within the fourth splicing exposure edge area, the fourth identifier and the third identifier corresponding to each other; and a plurality of peripheral exposure areas, each peripheral exposure area including a cut-out exposure area and a first splicing exposure area surrounding the cut-out exposure area, the first splicing exposure area including a first splicing exposure edge area and a second splicing exposure edge area located on opposite sides of the cut-out exposure area; a first identifier is located within the first splicing exposure edge area, and a second identifier is located within the second splicing exposure edge area, the second identifier and the first identifier corresponding to each other; The wafer to be processed is subjected to multiple exposures using the mask to form a central circuit pattern in the core circuit setting area, a peripheral circuit pattern in the outer circuit setting area, and a first set of alignment marks in the first splicing area.

7. The method for forming a chip as described in claim 6, characterized in that, The method for forming the first set of alignment marks in the first stitching area includes: forming a first mark pattern in the first stitching area after a first exposure process; and forming a second mark pattern in the first stitching area after a second exposure process, wherein the second mark pattern coincides with the first mark pattern.

8. The method for forming a chip as described in claim 6, characterized in that, The method for forming the first set of alignment marks in the first stitching area includes: forming a first mark pattern in the first stitching area after a first exposure process; and forming a second mark pattern in the first stitching area after a second exposure process, wherein the second mark pattern is adjacent to the first mark pattern.

9. The method for forming a chip as described in claim 6, characterized in that, The mask also includes: the peripheral exposure area further includes a peripheral circuit exposure area, the peripheral circuit exposure area is located on both sides of the cutting track exposure area and between the cutting track exposure area and the first splicing exposure area, the peripheral circuit exposure area includes several peripheral circuit patterns.

10. The method for forming a chip as described in claim 6, characterized in that, The method further includes forming a second set of alignment marks in the second splicing area after the multiple exposure process, where adjacent core circuit setting areas are connected by a second splicing area.

11. The method for forming a chip as described in claim 10, characterized in that, The method for forming the second set of alignment marks in the second stitching area includes: forming a third mark pattern in the second stitching area after a third exposure process; and forming a fourth mark pattern in the second stitching area after a fourth exposure process, wherein the third mark pattern and the fourth mark pattern coincide.

12. The method for forming a chip as described in claim 10, characterized in that, The method for forming the second set of alignment marks in the second stitching area includes: forming a third mark pattern in the second stitching area after a third exposure process; and forming a fourth mark pattern in the second stitching area after a fourth exposure process, wherein the fourth mark pattern is adjacent to the third mark pattern.

13. The method for forming a chip as described in claim 6, characterized in that, The width of the first splicing area ranges from 0.1 µm to 0.5 µm.

14. The method for forming a chip as described in claim 6, characterized in that, The central circuit pattern is formed by the plurality of central exposure areas of the mask, and the peripheral circuit pattern is formed by the plurality of peripheral exposure areas of the mask.

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