Test methods and systems for gate oxide capacitance of MOS transistors

Abstract

This application relates to a method and system for testing the gate oxide capacitance of a MOS transistor. The method includes: providing a standard MOS transistor and obtaining the standard gate oxide capacitance C corresponding to the standard MOS transistor. ox01 And at the first temperature, the first gate small-signal capacitance C of the standard MOS transistor. gg01 Provide the MOS transistor under test and put it into a strongly inverted state; obtain the second gate small-signal capacitance C of the MOS transistor under test at a first temperature. gg02 According to the standard gate oxide capacitance C ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 This allows us to obtain the true thickness of the gate oxide layer of the MOS transistor under test.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and system for testing the gate oxide capacitance of a MOS transistor. Background Technology

[0002] The gate structure of a MOS transistor includes a gate oxide layer and a polysilicon gate on the gate oxide layer. The depletion phenomenon of the polysilicon gate structure makes it impossible to extract the true thickness of the gate oxide layer from the CV curve of the MOS transistor. The thickness of the gate oxide layer extracted from the CV curve of a typical NMOS transistor is smaller than that extracted from the CV curve of a PMOS transistor. Summary of the Invention

[0003] This application provides a method and system for testing the gate oxide capacitance of a MOS transistor, which can accurately test the gate oxide capacitance of the MOS transistor under test, and thus obtain the thickness of the gate oxide layer.

[0004] This disclosure provides a method for testing the gate oxide capacitance of a MOS transistor, including:

[0005] Provide a standard MOS transistor and obtain the standard gate oxide capacitance C corresponding to the standard MOS transistor. ox01 And at the first temperature, the first gate small-signal capacitance C of the standard MOS transistor. gg01 ;

[0006] Provide the MOS transistor under test and put the MOS transistor under test into a strongly inverted state;

[0007] Obtain the second gate small-signal capacitance C of the MOS transistor under test at the first temperature. gg02 ;

[0008] According to the standard gate oxide capacitance C ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 .

[0009] In one embodiment, a standard MOS transistor is provided, and a standard gate oxide capacitance C corresponding to the standard MOS transistor is obtained. ox01 ,include:

[0010] Provide a standard MOS transistor and put the standard MOS transistor into a strongly inverted state;

[0011] A small-signal alternating current with a preset frequency is applied to the gate of a standard MOS transistor;

[0012] Obtain the gate small-signal capacitance C of a standard MOS transistor at different test temperatures. gg And obtain the gate small-signal capacitance C gg The first relationship curve between the temperature and the test temperature;

[0013] The maximum gate small-signal capacitance C of the standard MOS transistor is obtained from the first relationship curve. ggmax The maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

[0014] In one embodiment, putting a standard MOS transistor into a strongly inverted state includes:

[0015] A first DC bias voltage is applied to the gate of a standard MOS transistor;

[0016] To bring the MOS transistor under test into a strongly inverted state, the following methods are included:

[0017] A second DC bias voltage is applied to the gate of the MOS transistor under test;

[0018] Obtain the second gate small-signal capacitance C of the MOS transistor under test at the first temperature. gg02 Previously, it also included:

[0019] A small-signal alternating current with a preset frequency is applied to the gate of the MOS transistor under test;

[0020] The first DC bias voltage is greater than the threshold voltage of the standard MOS transistor, and the second DC bias voltage is greater than the threshold voltage of the MOS transistor under test.

[0021] In one embodiment, the standard MOS transistor includes a first standard MOS transistor and a second standard MOS transistor, and the gate small-signal capacitance C of the standard MOS transistor is obtained at different test temperatures. gg And obtain the gate small-signal capacitance C gg The first relationship curve between temperature and test temperature includes:

[0022] Obtain the gate small-signal capacitance C of the first standard MOS transistor at different test temperatures. gg1 The small-signal gate capacitance C of the second standard MOS transistor gg2 ;

[0023] Linear fitting was performed to obtain the gate small-signal capacitance C. gg1 The first fitted curve between the test temperature and the gate small-signal capacitance C gg2 The second fitted curve between the test temperature and the actual temperature;

[0024] The first relationship curve is obtained based on the first and second fitted curves.

[0025] In one embodiment, the first gate small-signal capacitance C of a standard MOS transistor is obtained at a first temperature. gg01 ,include:

[0026] Obtain the first gate small-signal capacitance C of the first standard MOS transistor at the first temperature. gg011 ;

[0027] Obtain the first gate small-signal capacitance C of the second standard MOS transistor at the first temperature. gg012 ;

[0028] According to the first gate small-signal capacitance C gg011 and the first gate small-signal capacitor C gg012 The first gate small-signal capacitance C is obtained. gg01 .

[0029] In one embodiment, according to the standard gate oxide capacitance C ox01 First gate small-signal capacitor Cgg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 ,include:

[0030] According to the standard gate oxide capacitance C ox01 and the first gate small-signal capacitor C gg01 The standard gate oxide capacitance C is obtained. ox01 and the first gate small-signal capacitor C gg01 The ratio between them;

[0031] Based on the ratio and the second gate small-signal capacitance C gg02 The capacitance C of the gate oxide layer under test is obtained. ox02 .

[0032] In one embodiment, the method for testing the gate oxide capacitance of a MOS transistor further includes:

[0033] Obtain the third gate small-signal capacitance C of the MOS transistor under test at the second temperature. gg03 ;

[0034] Based on the preset frequency and the third gate small-signal capacitor C gg03 and the gate oxide capacitance C under test ox02 The polysilicon gate capacitance C of the MOS transistor under test was obtained. poly ;

[0035] The second temperature is lower than the critical temperature, which is the maximum gate small-signal capacitance C of the MOS transistor under test. ggmax1 The corresponding test temperature.

[0036] In one embodiment, the first temperature includes the wafer receiving test temperature of the MOS transistor under test.

[0037] The above-described test method for the gate oxide capacitance of a MOS transistor uses the standard gate oxide capacitance C corresponding to a standard MOS transistor. ox01 The first gate small-signal capacitance C of the standard MOS transistor at the first temperature gg01 and the second gate small-signal capacitance C of the MOS transistor under test gg02 The gate oxide capacitance C of the MOS transistor under test can be obtained. ox02 The accurate value is obtained, and thus the true thickness of the gate oxide layer of the MOS transistor under test is obtained, eliminating the problem that the true thickness of the gate oxide layer under test cannot be extracted from the CV curve of the MOS transistor under test due to different conductive carriers.

[0038] This disclosure also provides a test system for the gate oxide capacitance of a MOS transistor, comprising:

[0039] Acquisition device, used to acquire the standard gate oxide capacitance C corresponding to a standard MOS transistor. ox01 And at the first temperature, the first gate small-signal capacitance C of the standard MOS transistor. gg01 ;

[0040] The first power supply device is used to put all the MOS transistors under test into a strongly inverted state.

[0041] The testing apparatus is used to bring the MOS transistor under test to a first temperature and measure the second gate small-signal capacitance C of the MOS transistor under test. gg02 ;

[0042] Arithmetic unit for calculating the standard gate oxide capacitance C. ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 .

[0043] In one embodiment, the first power supply device is further used to bring all standard MOS transistors into a strongly inverted state; the MOS transistor gate oxide capacitance testing system further includes:

[0044] The second power supply device is used to apply a small-signal alternating current with a preset frequency to the gate of a standard MOS transistor;

[0045] The testing apparatus is also used to subject a standard MOS transistor to different test temperatures and to measure the gate small-signal capacitance C of the standard MOS transistor at different test temperatures. gg It is also used to bring a standard MOS transistor to a first temperature and to measure the first gate small-signal capacitance C of the standard MOS transistor. gg01 The computing unit is also used to measure the small-signal gate capacitance C of a standard MOS transistor under different test temperatures. gg The small-signal gate capacitance C is obtained through calculation. gg The first relationship curve between the test temperature and the test temperature is also used to obtain the maximum gate small-signal capacitance C of the standard MOS transistor based on the first relationship curve. ggmax Maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

[0046] In one embodiment, the first power supply device is further configured to apply a first DC bias voltage to the gate of a standard MOS transistor to put the standard MOS transistor in a strongly inverted state, and to apply a second DC bias voltage to the gate of the MOS transistor under test to put the MOS transistor under test in a strongly inverted state; the second power supply device is further configured to apply a small-signal AC current with a preset frequency to the gate of the MOS transistor under test.

[0047] The first DC bias voltage is greater than the threshold voltage of the standard MOS transistor, and the second DC bias voltage is greater than the threshold voltage of the MOS transistor under test.

[0048] In one embodiment, the testing apparatus is further configured to subject the MOS transistor under test to a second temperature and measure the third gate small-signal capacitance C of a standard MOS transistor. gg03 The arithmetic unit is also used to determine the frequency and the third gate small-signal capacitor C according to a preset frequency. gg03 and the gate oxide capacitance C under test ox02 The polysilicon gate capacitance C of the MOS transistor under test was obtained. poly ;

[0049] The second temperature is lower than the critical temperature, which is the maximum gate small-signal capacitance C of the MOS transistor under test. ggmax1 The corresponding test temperature.

[0050] In the aforementioned test system for the gate oxide capacitance of a MOS transistor, the arithmetic unit uses the standard gate oxide capacitance C corresponding to a standard MOS transistor. ox01 The first gate small-signal capacitance C of the standard MOS transistor at the first temperature gg01 and the second gate small-signal capacitance C of the MOS transistor under test gg02The gate oxide capacitance C of the MOS transistor under test can be obtained. ox02 The accurate value is obtained, and thus the true thickness of the gate oxide layer of the MOS transistor under test is obtained, eliminating the problem that the true thickness of the gate oxide layer under test cannot be extracted from the CV curve of the MOS transistor under test due to different conductive carriers. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart illustrating a method for testing the gate oxide capacitance of a MOS transistor in one embodiment;

[0053] Figure 2 This is a cross-sectional schematic diagram of a standard MOS transistor;

[0054] Figure 3 This is a schematic cross-sectional view of the MOS transistor under test.

[0055] Figure 4 In one embodiment, a standard MOS transistor 100 is provided;

[0056] Figure 5 The graph shows the trend of the resistance R of a polysilicon gate as a function of temperature T.

[0057] Figure 6 In one embodiment, the gate small-signal capacitance C of a standard MOS transistor at different test temperatures T is obtained. gg And obtain the gate small-signal capacitance C gg A flowchart illustrating the first relationship curve between temperature and test temperature;

[0058] Figure 7 In one embodiment, the first gate small-signal capacitance C of a standard MOS transistor 100 is obtained at a first temperature T1. gg01 A flowchart;

[0059] Figure 8 In one embodiment, based on the standard gate oxide capacitance C ox01 First gate small-signal capacitor Cgg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 A flowchart;

[0060] Figure 9 This is a flowchart illustrating a method for testing the gate oxide capacitance of a MOS transistor in another embodiment;

[0061] Figure 10 This is a block diagram of a test system for the gate oxide capacitance of a MOS transistor in one embodiment;

[0062] Figure 11 This is a block diagram of a test system for the gate oxide capacitance of a MOS transistor in another embodiment.

[0063] Explanation of reference numerals in the attached figures:

[0064] 100, Standard MOS transistor; 102, First substrate; 104, First source; 106, Second drain; 108, Standard gate structure; 110, Standard gate oxide layer; 112, First polysilicon gate; 200, MOS transistor under test; 202, Second substrate; 204, Second source; 206, Second drain; 208, Gate structure under test; 210, Gate oxide layer under test; 212, Polysilicon gate under test; 302, Acquisition device; 304, First power supply device; 306, Testing device; 308, Computational device; 310, Second power supply device. Detailed Implementation

[0065] To facilitate understanding of the embodiments of this application, a more comprehensive description of the embodiments of this application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the embodiments of this application. However, the embodiments of this application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the embodiments of this application more thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0067] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0068] It is understood that the terms "first," "second," etc., used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first gate small-signal capacitor may be referred to as a second gate small-signal capacitor, and similarly, a second gate small-signal capacitor may be referred to as a first gate small-signal capacitor. Both the first gate small-signal capacitor and the second gate small-signal capacitor are gate small-signal capacitors, but they are not the same gate small-signal capacitor.

[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0070] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0071] Figure 1 This is a schematic flowchart of a method for testing the gate oxide capacitance of a MOS transistor in one embodiment. Figure 2 This is a cross-sectional schematic diagram of a standard MOS transistor. Figure 3 This is a schematic cross-sectional view of the MOS transistor under test, as shown below. Figure 1 As shown, a method for testing the gate oxide capacitance of a MOS transistor is provided, including:

[0072] S102 provides a standard MOS transistor.

[0073] like Figure 2 Specifically, a standard MOS transistor 100 is provided, and the standard gate oxide capacitance C corresponding to the standard MOS transistor 100 is obtained. ox01 And at the first temperature T1, the first gate small-signal capacitance C of the standard MOS transistor 100 gg01 A standard MOS transistor 100 includes a first source 104 and a second drain 106 formed in a first substrate 102, and a standard gate structure 108 located on the upper surface of the first substrate 102 between the first source 104 and the second drain 106. The standard gate structure 108 includes a standard gate oxide layer 110 and a first polysilicon gate 112 located on the standard gate oxide layer 110. The standard gate oxide layer capacitance C... ox01The capacitance value of the standard gate oxide layer 110, and the first gate small-signal capacitance C gg01 This is the gate small-signal capacitance corresponding to the standard gate structure 108 at the first temperature T1.

[0074] Optionally, the first substrate 102 may include, but is not limited to, undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the first substrate 102 is made of single-crystal silicon.

[0075] S104 provides the MOS transistor under test and puts the MOS transistor under test into a strong inversion state.

[0076] like Figure 3 As shown, specifically, a MOS transistor under test 200 is provided and the MOS transistor under test 200 is placed in a strongly inverted state. The MOS transistor under test 200 includes a second source 204 and a second drain 206 formed in a second substrate 202, and a gate structure under test 208 located on the upper surface of the second substrate 202 between the second source 204 and the second drain 206. The gate structure under test 208 includes a gate oxide layer under test 210 and a polysilicon gate under test 212 located on the gate oxide layer under test 210.

[0077] Optionally, the second substrate 202 may include, but is not limited to, undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The constituent material of the second substrate 202 may be the same as or different from the constituent material of the first substrate 102. As an example, in this embodiment, the constituent material of the second substrate 202 is selected as single-crystal silicon.

[0078] S106, Obtain the second gate small-signal capacitance C of the MOS transistor under test at the first temperature. gg02 .

[0079] Obtain the second gate small-signal capacitance C of the MOS transistor 200 under test at the first temperature T1. gg02 Second gate small-signal capacitor C gg02 This is the capacitance value of the gate small-signal capacitor corresponding to the gate structure 208 under test at the first temperature T1.

[0080] S108, according to the standard gate oxide capacitance C ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 .

[0081] According to the standard gate oxide capacitance C ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor 200 under test is calculated. ox02 The gate oxide capacitance C under test ox02 This represents the capacitance value of the gate oxide layer 210 under test.

[0082] The above-described test method for the gate oxide capacitance of a MOS transistor uses the standard gate oxide capacitance C corresponding to a standard MOS transistor 100. ox01 The first gate small-signal capacitance C of the standard MOS transistor 100 at the first temperature gg01 and the second gate small-signal capacitance C of the MOS transistor 200 under test gg02 The gate oxide capacitance C of the MOS transistor 200 under test can be obtained. ox02 The accurate value is obtained, and thus the true thickness of the gate oxide layer 210 of the MOS transistor 200 under test is obtained, eliminating the problem that the true thickness of the gate oxide layer 210 under test cannot be extracted from the CV curve of the MOS transistor 200 under test due to different conductive carriers.

[0083] Figure 4 In one embodiment, a standard MOS transistor 100 is provided, and a standard gate oxide capacitance C corresponding to the standard MOS transistor 100 is obtained. ox01 A flowchart, such as Figure 4 As shown, in one embodiment, a standard MOS transistor 100 is provided, and a standard gate oxide capacitance C corresponding to the standard MOS transistor 100 is obtained. ox01 The steps include:

[0084] 202 provides a standard MOS transistor and puts the standard MOS transistor in a strongly inverted state.

[0085] Provide a standard MOS transistor 100 and put the standard MOS transistor 100 into a strong inversion state.

[0086] In one embodiment, putting the standard MOS transistor 100 into a strongly inverted state includes: applying a first DC bias voltage V to the gate (standard gate structure 108) of the standard MOS transistor 100. GS1 Among them, the first DC bias voltage V GS1The voltage is greater than the threshold voltage V1 of the standard MOS transistor 100. At this time, it is not necessary to scan the entire CV curve of the standard MOS transistor 100, which improves the test speed.

[0087] S204 applies a small-signal alternating current with a preset frequency to the gate of a standard MOS transistor.

[0088] A small-signal alternating current ΔV with a preset frequency ω1 is applied to the gate (standard gate structure 108) of a standard MOS transistor 100. GS1 This is used for small-signal testing to ensure the test process satisfies linear time invariance. Optionally, the preset frequency ω1 includes low or high frequencies, such as 100kHz, and the small-signal AC current ΔV... GS1 The amplitude is between 30mV and 50mV, such as 30mV, 35mV, 40mV, 45mV, 50mV, etc.

[0089] S206, Obtain the gate small-signal capacitance C of a standard MOS transistor at different test temperatures. gg And obtain the gate small-signal capacitance C gg The first relationship curve between temperature and test temperature.

[0090] The standard MOS transistor 100 was subjected to different test temperatures T, and the gate small-signal capacitance C of the standard gate structure 108 at each test temperature T was measured. gg Based on the test temperature T and the gate small-signal capacitance C corresponding to each test temperature T. gg The small-signal gate capacitance C is obtained. gg The first relationship curve between the temperature and the test temperature T.

[0091] S208, the maximum gate small-signal capacitance C of the standard MOS transistor is obtained according to the first relationship curve. ggmax The maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

[0092] The small-signal gate capacitance of a MOS transistor can be considered as the polysilicon gate capacitance C and the gate oxide capacitance. The series capacitance, and the formula for calculating the gate small-signal capacitance of the gate structure in a MOS transistor at temperature T0 are:

[0093] , (1-1)

[0094] in, This refers to the small-signal gate capacitance of the gate structure in a MOS transistor at temperature T0. A small-signal alternating current is applied to the gate structure of the MOS transistor. A small-signal alternating current applied to the gate structure of a MOS transistor at temperature T0 At that time, the measured small-signal alternating current, ω is the small-signal alternating current. The perturbation frequency.

[0095] The formula for calculating the polysilicon gate capacitance C of a MOS transistor at temperature T0 is:

[0096] , (1-2)

[0097] in, This refers to the gate oxide capacitance in a MOS transistor. B is the small-signal gate capacitance of the gate structure in a MOS transistor at temperature T0, and it equals... , A small-signal alternating current is applied to the gate structure of the MOS transistor. A small-signal alternating current applied to the gate structure of a MOS transistor at temperature T0 At that time, the measured small-signal alternating current, ω is the small-signal alternating current. The perturbation frequency.

[0098] Figure 5 The graph shows the trend of the resistance R of a polysilicon gate as a function of temperature T, as shown below. Figure 5 As shown, the conductivity of the polysilicon gate exhibits a linear negative correlation with temperature, resulting in high epitaxial precision. With increasing polysilicon gate conductivity, the density of states increases, leading to an excess net charge distribution on the polysilicon gate surface in a very thin layer. The polysilicon gate eventually depletes and disappears, and the gate capacitance of the MOS transistor approaches the depletion capacitance of the gate oxide layer. Based on the first relationship curve, the maximum small-signal gate capacitance C of the standard MOS transistor 100 is obtained. ggmax That is, obtained from the first relationship curve =0, at this point the test temperature T is the critical temperature T01 of the standard MOS transistor 100, and the gate small-signal capacitance C is... gg The maximum gate small-signal capacitance C of the standard gate structure 108 ggmax This refers to the standard gate oxide capacitance C of a standard MOS transistor 100. ox01 (Capacitance value of standard gate oxide layer 110).

[0099] In one embodiment, putting the MOS transistor 200 under test into a strongly inverted state includes: applying a second DC bias voltage V to the gate (gate structure 208 under test) of the MOS transistor 200 under test. GS2 Among them, the second DC bias voltage V GS2The voltage is greater than the threshold voltage V2 of the MOS transistor 200 under test. Therefore, it is not necessary to scan the entire CV curve of the MOS transistor 200 under test, thus improving the testing speed. The second gate small-signal capacitance C of the MOS transistor 200 under test is obtained at the first temperature T1. gg02 Previously, it also included: applying a small-signal alternating current with a preset frequency ω2 to the gate (gate structure 208) of the MOS transistor under test 200.

[0100] ΔV GS2 Small-signal testing is performed to ensure the test process satisfies linear time invariance. Optionally, the preset frequency ω2 can be low or high, such as 100kHz, and the small-signal AC current ΔV... GS2 The amplitude is between 30mV and 50mV, such as 30mV, 35mV, 40mV, 45mV, 50mV, etc. Optionally, the preset frequency ω2 and preset frequency ω1 can be the same or different, and the small signal AC voltage ΔV... GS2 Amplitude and small-signal AC current ΔV GS1 The amplitudes may be the same or different.

[0101] Figure 6 In one embodiment, the gate small-signal capacitance C of a standard MOS transistor at different test temperatures T is obtained. gg And obtain the gate small-signal capacitance C gg A flowchart illustrating the first relationship curve between temperature and test temperature, as shown below. Figure 6 As shown, in one embodiment, the standard MOS transistor 100 includes a first standard MOS transistor and a second standard MOS transistor, and the gate small-signal capacitance C of the standard MOS transistor 100 is obtained at different test temperatures T. gg And obtain the gate small-signal capacitance C gg The first relationship curve between the temperature and the test temperature T includes:

[0102] S302, Obtain the gate small-signal capacitance C of the first standard MOS transistor at different test temperatures. gg1 The small-signal gate capacitance C of the second standard MOS transistor gg2 .

[0103] Obtain the gate small-signal capacitance C of the first standard MOS transistor at different test temperatures T. gg1 And the gate small-signal capacitance C of the second standard MOS transistor at different test temperatures. gg2 .

[0104] S304, respectively, obtains the gate small-signal capacitance C gg1 The first fitted curve between the test temperature and the gate small-signal capacitance C gg2 The second fitted curve between the test temperature and the actual temperature.

[0105] The small-signal gate capacitance C of the first standard MOS transistor at different test temperatures T and at each test temperature T. gg1 By performing linear fitting, the small-signal gate capacitance C is obtained. gg1 The first fitted curve between the test temperature T and the second standard MOS transistor at different test temperatures T and at each test temperature T, shows the small-signal gate capacitance C. gg2 By performing linear fitting, the small-signal gate capacitance C is obtained. gg2 The second fitted curve between the test temperature T and the temperature T.

[0106] S306. Based on the first fitting curve and the second fitting curve, the first relationship curve is obtained.

[0107] The first and second fitted curves are processed, for example, by linear fitting, to obtain the gate small-signal capacitance C of the standard gate structure 108. gg The first relationship curve between the voltage and the test temperature T, obtained in this way, is closer to the gate small-signal capacitance C. gg The actual curve between the measured temperature T and the actual temperature T allows for more accurate determination of the thickness of the gate oxide layer 210 under test. Optionally, to increase the capacitance C of the gate oxide layer under test... ox02 The accuracy can be obtained by using fitting curves corresponding to three different standard MOS transistors 100, which are greater than or equal to three different standard MOS transistors 100, to obtain the first relationship curve.

[0108] Figure 7 In one embodiment, the first gate small-signal capacitance C of a standard MOS transistor 100 is obtained at a first temperature T1. gg01 A flowchart, such as Figure 7 As shown, in one embodiment, the standard MOS transistor 100 includes a first standard MOS transistor and a second standard MOS transistor, and the first gate small-signal capacitance C of the standard MOS transistor 100 is obtained at a first temperature T1. gg01 ,include:

[0109] S402, Obtain the first gate small-signal capacitance C of the first standard MOS transistor at the first temperature T1. gg011 .

[0110] S404, Obtain the first gate small-signal capacitance C of the second standard MOS transistor at the first temperature T1. gg012 .

[0111] S406, based on the first gate small-signal capacitor C gg011 and the first gate small-signal capacitor C gg012 The first gate small-signal capacitance C is obtained. gg01 .

[0112] For example, this can be achieved by taking the first gate small-signal capacitor C. gg011 and the first gate small-signal capacitor C gg012 The average value is used to obtain the first gate small-signal capacitance C. gg01 .

[0113] Figure 8 In one embodiment, based on the standard gate oxide capacitance C ox01 First gate small-signal capacitor Cgg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 A flowchart, such as Figure 8 As shown, in one embodiment, according to the standard gate oxide capacitance C ox01 First gate small-signal capacitor Cgg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor 200 under test is obtained. ox02 ,include:

[0114] S502, obtain the standard gate oxide capacitance C ox01 and the first gate small-signal capacitor C gg01 The ratio A between them.

[0115] According to the standard gate oxide capacitance C of standard MOS transistor 100 ox01 and the first gate small-signal capacitor C gg01 The standard gate oxide capacitance C is obtained. ox01 and the first gate small-signal capacitor C gg01 The ratio A between them.

[0116] S504, based on the ratio A and the second gate small-signal capacitance C gg02 The capacitance C of the gate oxide layer under test is obtained. ox02 .

[0117] When the test temperature T is the critical temperature T02 of the MOS transistor 200 under test, the gate small-signal capacitance C of the MOS transistor 200 under test... gg 'Equals the gate oxide capacitance C under test ox02 The critical temperature T02 is the temperature boundary where the gate small-signal capacitance of the MOS transistor 200 under test does not change with the test temperature T. Because at the first temperature T1, the ratio of the gate oxide capacitance to the gate small-signal capacitance is approximately constant, the standard gate oxide capacitance C... ox01 and the first gate small-signal capacitor C gg01 The ratio A between them is equal to the capacitance C of the gate oxide layer under test. ox02 Second gate small-signal capacitor C gg02The ratio between them, based on the ratio A and the second gate small-signal capacitance C. gg02 The gate oxide capacitance C of the gate oxide layer 210 in the MOS transistor under test 200 can be obtained. ox02 .

[0118] Figure 9 This is a flowchart illustrating a method for testing the gate oxide capacitance of a MOS transistor in another embodiment, as shown below. Figure 9 As shown, in one embodiment, the method for testing the gate oxide capacitance of a MOS transistor further includes:

[0119] S602, Obtain the third gate small-signal capacitance C of the MOS transistor under test at the second temperature. gg03 .

[0120] Obtain the third gate small-signal capacitance C of the MOS transistor 200 under test at the second temperature T2. gg03 The third gate small-signal capacitor C gg03 Let C be the gate small-signal capacitance corresponding to the gate structure 208 under test at the second temperature T2. Here, the second temperature T2 is the evaluation temperature of the MOS transistor 200 under test; the second temperature T2 is less than the critical temperature T02, and the critical temperature T02 is the maximum gate small-signal capacitance C corresponding to the gate structure 208 under test of the MOS transistor 200 under test. ggmax1 The corresponding test temperature T. Optionally, a small-signal AC current ΔV with a preset frequency ω2 is applied to the gate structure 208 under test. GS2 After placing the MOS transistor under test 200 at the second temperature T2, the small-signal AC current ΔV was measured. GS2 The corresponding small-signal alternating current ΔI G2 According to formula (1-1), .

[0121] S604, based on the preset frequency and the third gate small-signal capacitor C gg03 and the gate oxide capacitance C under test ox02 The polysilicon gate capacitance C of the MOS transistor under test was obtained. poly .

[0122] Specifically, the third gate small-signal capacitance C of the gate structure 208 under test gg03 The capacitance C of the gate oxide layer under test is equal to that of the gate oxide layer 210 under test. ox02 The polysilicon gate capacitance C of the polysilicon gate 212 under the second temperature T2 poly The series capacitor, according to formula (1-2), can be used to obtain the polysilicon gate capacitance C of the polysilicon gate 212. poly .

[0123] In one embodiment, the first temperature T1 includes the wafer receiving test temperature of the MOS transistor 200 under test, and different first temperatures T1 can be set according to the WAT temperature.

[0124] The following is an exemplary description of a method for testing the gate oxide capacitance of a MOS transistor. Step 1: Provide standard MOS transistors 1, 2, 3...n in a strongly inverted state. Step 2: Apply a small-signal alternating current ΔV with a preset frequency ω to the gate of each of the standard MOS transistors 1, 2, 3...n. GS Then, the small-signal AC current ΔI at each test temperature T was measured. G and according to The first gate small-signal capacitance of standard MOS transistor 1 at each test temperature T was obtained. The first gate small-signal capacitance corresponding to standard MOS transistor 2 The first gate small-signal capacitance corresponding to standard MOS transistor 3 …the first gate small-signal capacitance corresponding to the standard MOS transistor n ,in, When the value is 0, the polysilicon gate capacitance in the first gate small-signal capacitance is 0. At this time, the first gate small-signal capacitance of standard MOS transistor 1 is the standard gate oxide layer capacitance C of standard MOS transistor 1. ox011 By analogy, the standard gate oxide capacitance C of standard MOS transistor 2 is obtained. ox012 The standard gate oxide capacitance C of a standard MOS transistor 3 ox013 ...the standard gate oxide capacitance C of a standard MOS transistor n ox01n Step 3: Obtain the first gate small-signal capacitance C of standard MOS transistor 1 at the third temperature T3 according to the method in step 2. gg041 The first gate small-signal capacitance C corresponding to standard MOS transistor 2 gg042 The first gate small-signal capacitance C corresponding to the standard MOS transistor 3 gg043 ...the first gate small-signal capacitance C corresponding to the standard MOS transistor n gg04n Wherein, the third temperature T3 is the preset WAT temperature; Step 4, for The ratio, The ratio, The ratio of... By fitting the ratio, the standard gate oxide capacitance C is obtained. ox01 and the first gate small-signal capacitor C gg01The ratio A between them; Step 5, provide the MOS transistor 1 under test in a strongly inverted state, and obtain the second gate small-signal capacitance C of the MOS transistor 1 under test at the third temperature T3 according to the method in Step 2. gg021 ,according to The gate oxide capacitance C of the gate oxide layer under test in the MOS transistor under test 1 is obtained. ox021 Step 6: Obtain the fourth gate small-signal capacitance C of the MOS transistor 1 under test at the fourth temperature T4, as described in Step 2. gg04 Wherein, the fourth temperature T4 is the evaluation temperature corresponding to the MOS transistor 1 under test; according to formula 1-2, the polysilicon gate capacitance C of the polysilicon gate in the MOS transistor 1 under test at the fourth temperature T4 can be obtained. poly4 .

[0125] It should be understood that, although Figure 1 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Figure 9 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0126] Figure 10 This is a block diagram of a test system for the gate oxide capacitance of a MOS transistor in one embodiment, as shown below. Figure 2 , Figure 3 and Figure 10 As shown, this embodiment provides a testing system for the gate oxide capacitance of a MOS transistor, including: an acquisition device 302, a first power supply device 304, a testing device 306, and a processing device 308. The acquisition device 302 is used to acquire the standard gate oxide capacitance C corresponding to a standard MOS transistor 100. ox01 And at the first temperature T1, the first gate small-signal capacitance C of the standard MOS transistor 100 gg01The standard MOS transistor 100 includes a first source 104 and a second drain 106 formed in a first substrate 102, and a standard gate structure 108 located on the upper surface of the first substrate 102 between the first source 104 and the second drain 106. The standard gate structure 108 includes a standard gate oxide layer 110 and a first polysilicon gate 112 located on the standard gate oxide layer 110. The standard gate oxide layer capacitance C... ox01 The capacitance value of the standard gate oxide layer 110, and the first gate small-signal capacitance C gg01 The gate small-signal capacitance is the value corresponding to the standard gate structure 108 at the first temperature T1. The first power supply device 304 is used to put all the MOS transistors under test 200 in a strongly inverted state. The MOS transistors under test 200 include a second source 204 and a second drain 206 formed in the second substrate 202, and a gate structure 208 located on the upper surface of the second substrate 202 between the second source 204 and the second drain 206. The gate structure 208 includes a gate oxide layer 210 and a polysilicon gate 212 located on the gate oxide layer 210. The test device 306 is used to bring the MOS transistors under test 200 to the first temperature T1 and measure the second gate small-signal capacitance C of the MOS transistors under test 200. gg02 Second gate small-signal capacitor C gg02 The capacitance value is the gate small-signal capacitance corresponding to the gate structure 208 under test at the first temperature T1; the computing device 308 is used to calculate the capacitance value based on the standard gate oxide capacitance C. ox01 First gate small-signal capacitor C gg01 Second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor 200 under test is obtained. ox02 The gate oxide capacitance C under test ox02 This represents the capacitance value of the gate oxide layer 210 under test.

[0127] In the aforementioned test system for the gate oxide capacitance of a MOS transistor, the arithmetic unit 308 measures the standard gate oxide capacitance C corresponding to the standard MOS transistor 100. ox01 The first gate small-signal capacitance C of the standard MOS transistor 100 at the first temperature T1. gg01 and the second gate small-signal capacitance C of the MOS transistor 200 under test gg02 The gate oxide capacitance C of the MOS transistor 200 under test can be obtained. ox02 The accurate value is obtained, and thus the true thickness of the gate oxide layer 210 of the MOS transistor 200 under test is obtained, eliminating the problem that the true thickness of the gate oxide layer 210 under test cannot be extracted from the CV curve of the MOS transistor 200 under test due to different conductive carriers.

[0128] In one embodiment, the first power supply device 304 is further configured to put all standard MOS transistors 100 into a strongly inverted state; specifically, the first power supply device 304 applies a first DC bias voltage V to the gate (standard gate structure 108) of the standard MOS transistors 100. GS1 Among them, the first DC bias voltage V GS1 The voltage is greater than the threshold voltage V1 of the standard MOS transistor 100. At this time, it is not necessary to scan the entire CV curve of the standard MOS transistor 100, which improves the test speed.

[0129] In one embodiment, the first power supply device 304 is used to apply a second DC bias voltage V to the gate (gate structure 208 under test) of the MOS transistor 200 under test. GS2 To put the MOS transistor 200 under test into a strongly inverted state, wherein the second DC bias voltage V GS2 If the voltage is greater than the threshold voltage V2 of the MOS transistor 200 under test, it is not necessary to scan the entire CV curve of the MOS transistor 200 under test, thus improving the test speed.

[0130] Figure 11 Here is a block diagram of a test system for the gate oxide capacitance of a MOS transistor in another embodiment, as shown below. Figure 11 As shown, in this embodiment, the test system for the gate oxide capacitance of a MOS transistor further includes a second power supply device 310, which is used to apply a small-signal alternating current ΔV with a preset frequency ω1 to the gate (standard gate structure 108) of a standard MOS transistor 100. GS1 This is to facilitate small-signal testing, while ensuring the testing process remains linear and time-invariant. Optionally, the preset frequency ω1 can be low or high, such as 100kHz, and the small-signal AC current ΔV... GS1 The amplitude is between 30mV and 50mV, for example, 30mV, 35mV, 40mV, 45mV, 50mV, etc. The test apparatus 306 is also used to subject the standard MOS transistor 100 to different test temperatures T, and to measure the small-signal gate capacitance C corresponding to the standard gate structure 108 of the standard MOS transistor 100 at different test temperatures T. gg The test apparatus 306 is also used to subject the standard MOS transistor 100 to a first temperature T1 and to measure the first gate small-signal capacitance C of the standard MOS transistor 100 at the first temperature T1. gg01 The arithmetic unit 308 is also used to measure the gate small-signal capacitance C of the standard MOS transistor 100 at different test temperatures T. gg The small-signal gate capacitance C is obtained through calculation. gg The arithmetic unit 308 is also used to obtain the maximum gate small-signal capacitance C of the standard MOS transistor 100 based on the first relationship curve between the test temperature T and the test temperature T.ggmax Maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

[0131] In one embodiment, the second power supply device 310 is also used to apply a small-signal alternating current ΔV with a preset frequency ω2 to the gate (gate structure 208) of the MOS transistor 200 under test. GS2 This is to facilitate small-signal testing, while ensuring the testing process remains linear and time-invariant. Optionally, the preset frequency ω2 can be low or high, such as 100kHz, and the small-signal AC current ΔV... GS2 The amplitude is between 30mV and 50mV, such as 30mV, 35mV, 40mV, 45mV, 50mV, etc. Optionally, the preset frequency ω2 and preset frequency ω1 can be the same or different, and the small signal AC voltage ΔV... GS2 Amplitude and small-signal AC current ΔV GS1 The amplitudes may be the same or different.

[0132] In one embodiment, the standard MOS transistor 100 includes a first standard MOS transistor and a second standard MOS transistor. The MOS transistor gate oxide capacitance testing system further includes a computing device connected to the acquisition device 302 and the testing device 306, respectively. The testing device 306 is also used to subject the first standard MOS transistor and the second standard MOS transistor to different test temperatures T, and to measure the small-signal gate capacitance C of the first standard MOS transistor at different test temperatures T. gg1 The small-signal gate capacitance C of the second standard MOS transistor gg2 The computing device is used to measure the small-signal gate capacitance C of the first standard MOS transistor at different test temperatures T and at each test temperature T. gg1 By performing linear fitting, the small-signal gate capacitance C is obtained. gg1 The first fitted curve between the test temperature T and the second standard MOS transistor at different test temperatures T and at each test temperature T, shows the small-signal gate capacitance C. gg2 By performing linear fitting, the small-signal gate capacitance C is obtained. gg2 A second fitted curve is obtained between the first and second fitted curves and the test temperature T. The computing device is also used to process the first and second fitted curves, for example, through linear fitting, to obtain the gate small-signal capacitance C of the standard gate structure 108. gg The first relationship curve between the voltage and the test temperature T. The first relationship curve obtained in this way is closer to the gate small-signal capacitance C. gg The actual curve between the measured temperature T and the actual temperature T allows for more accurate determination of the thickness of the gate oxide layer 210 under test. Optionally, to increase the capacitance C of the gate oxide layer under test... ox02The accuracy can be obtained by using fitting curves corresponding to three different standard MOS transistors 100, which are greater than or equal to three different standard MOS transistors 100, to obtain the first relationship curve.

[0133] In one embodiment, the computing device 308 calculates based on the standard gate oxide capacitance C. ox01 and the first gate small-signal capacitor C gg01 The standard gate oxide capacitance C is calculated. ox01 and the first gate small-signal capacitor C gg01 The ratio A between them, and then based on the ratio A and the second gate small-signal capacitance C gg02 The gate oxide capacitance C of the gate oxide layer 210 in the MOS transistor under test 200 can be obtained. ox02 .

[0134] In one embodiment, the test apparatus 306 is further configured to subject the MOS transistor 200 under test to a second temperature T2 and measure the third gate small-signal capacitance C of the standard MOS transistor 200. gg03 The third gate small-signal capacitor C gg03 Let C be the gate small-signal capacitance corresponding to the gate structure 208 under test at the second temperature T2. Here, the second temperature T2 is the evaluation temperature of the MOS transistor 200 under test; the second temperature T2 is less than the critical temperature T02, and the critical temperature T02 is the maximum gate small-signal capacitance C corresponding to the gate structure 208 under test of the MOS transistor 200 under test. ggmax1 The corresponding test temperature T. Optionally, the test device 306 includes a calculation module and a test module. The test module is used to measure the small-signal AC current ΔV after the MOS transistor 200 under test is placed at a second temperature T2. GS2 The corresponding small-signal alternating current ΔI G2 The arithmetic unit is used to determine the arithmetic logic unit (ALU) based on the following: The third gate small-signal capacitance C of the standard MOS transistor 200 is obtained. gg03 The arithmetic unit 308 is also used to determine the frequency and the third gate small-signal capacitor C according to a preset frequency. gg03 and the gate oxide capacitance C under test ox02 The polysilicon gate capacitance C of the MOS transistor under test was obtained. poly Specifically, the arithmetic unit 308 can obtain the polysilicon gate capacitance C of the polysilicon gate 212 according to the aforementioned formula (1-2). poly .

[0135] In one embodiment, the first temperature T1 includes the wafer receiving test temperature of the MOS transistor 200 under test, and different first temperatures T1 can be set according to the WAT temperature.

[0136] For example, the computing device, arithmetic device 308 and arithmetic module include a memory, an arithmetic unit or a microcontroller, and perform arithmetic by executing a computer program stored in the memory, arithmetic unit or microcontroller. The first power supply device 304 includes a DC power supply and the second power supply device 310 includes an AC power supply.

[0137] This application also provides a testing device, including a controller, a memory, and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the test method for the gate oxide capacitance of the MOS transistor described in any of the above claims.

[0138] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A method for testing the gate oxide capacitance of a MOS transistor, characterized in that, include: Provide a standard MOS transistor and obtain the standard gate oxide capacitance C corresponding to the standard MOS transistor. ox01 And at the first temperature, the first gate small-signal capacitance C of the standard MOS transistor gg01 ; Provide a MOS transistor under test and put the MOS transistor under test into a strongly inverted state; Obtain the second gate small-signal capacitance C of the MOS transistor under test at the first temperature. gg02 ; According to the standard gate oxide capacitance C ox01 The first gate small-signal capacitor C gg01 and the second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 The standard MOS transistor is provided, and the standard gate oxide capacitance C corresponding to the standard MOS transistor is obtained. ox01 ,include: Provide a standard MOS transistor and put the standard MOS transistor in a strongly inverted state; A small-signal alternating current with a preset frequency is applied to the gate of the standard MOS transistor; Obtain the gate small-signal capacitance C of the standard MOS transistor at different test temperatures. gg And obtain the gate small-signal capacitance C gg The first relationship curve between the test temperature and the temperature; The maximum gate small-signal capacitance C of the standard MOS transistor is obtained from the first relationship curve. ggmax The maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

2. The test method according to claim 1, characterized in that, The step of putting the standard MOS transistor into a strongly inverted state includes: A first DC bias voltage is applied to the gate of the standard MOS transistor; The step of putting the MOS transistor under test into a strongly inverted state includes: A second DC bias voltage is applied to the gate of the MOS transistor under test; Obtain the second gate small-signal capacitance C of the MOS transistor under test at the first temperature. gg02 Previously, it also included: A small-signal alternating current with a preset frequency is applied to the gate of the MOS transistor under test; Wherein, the first DC bias voltage is greater than the threshold voltage of the standard MOS transistor, and the second DC bias voltage is greater than the threshold voltage of the MOS transistor under test.

3. The test method according to claim 1, characterized in that, The standard MOS transistor includes a first standard MOS transistor and a second standard MOS transistor. The method for obtaining the gate small-signal capacitance C of the standard MOS transistor at different test temperatures is described. gg And obtain the gate small-signal capacitance C gg The first relationship curve between the test temperature and the temperature includes: Obtain the gate small-signal capacitance C of the first standard MOS transistor at different test temperatures. gg1 and the gate small-signal capacitance C of the second standard MOS transistor gg2 ; Linear fitting was performed to obtain the gate small-signal capacitance C. gg1 The first fitting curve between the test temperature and the gate small-signal capacitance C gg2 A second fitting curve between the test temperature and the test temperature; The first relationship curve is obtained based on the first fitted curve and the second fitted curve.

4. The test method according to claim 3, characterized in that, Obtain the first gate small-signal capacitance C of the standard MOS transistor at the first temperature. gg01 ,include: Obtain the first gate small-signal capacitance C of the first standard MOS transistor at the first temperature. gg011 ; Obtain the first gate small-signal capacitance C of the second standard MOS transistor at the first temperature. gg012 ; According to the first gate small signal capacitance C gg011 and the first gate small signal capacitor C gg012 The first gate small-signal capacitance C is obtained. gg01 .

5. The test method according to claim 2, characterized in that, Also includes: Obtain the third gate small-signal capacitance C of the MOS transistor under test at the second temperature. gg03 ; According to the preset frequency and the third gate small-signal capacitor C gg03 and the gate oxide capacitance C to be tested ox02 The polysilicon gate capacitance C of the MOS transistor under test is obtained. poly ; Wherein, the second temperature is less than the critical temperature, and the critical temperature is the maximum gate small-signal capacitance C corresponding to the MOS transistor under test. ggmax1 The corresponding test temperature.

6. A testing system for the gate oxide capacitance of a MOS transistor, characterized in that, include: Acquisition device, used to acquire the standard gate oxide capacitance C corresponding to a standard MOS transistor. ox01 And at the first temperature, the first gate small-signal capacitance C of the standard MOS transistor gg01 ; The first power supply device is used to put all the MOS transistors under test into a strongly inverted state. The testing apparatus is used to subject the MOS transistor under test to a first temperature and measure the second gate small-signal capacitance C of the MOS transistor under test. gg02 ; A computing device, configured to operate according to the standard gate oxide capacitance C ox01 The first gate small-signal capacitor C gg01 and the second gate small-signal capacitor C gg02 The gate oxide capacitance C of the MOS transistor under test is obtained. ox02 .

7. The testing system according to claim 6, characterized in that, The first power supply device is further configured to put all the standard MOS transistors in a strongly inverted state; it also includes: The second power supply device is used to apply a small-signal alternating current with a preset frequency to the gate of the standard MOS transistor; The testing apparatus is further used to subject the standard MOS transistor to different test temperatures and to measure the gate small-signal capacitance C of the standard MOS transistor at different test temperatures. gg It is also used to subject the standard MOS transistor to a first temperature and to measure the first gate small-signal capacitance C of the standard MOS transistor. gg01 The computing device is also used to determine the gate small-signal capacitance C of the standard MOS transistor under different test temperatures. gg The gate small-signal capacitance C is obtained through calculation. gg The first relationship curve between the test temperature and the test temperature is also used to obtain the maximum gate small-signal capacitance C of the standard MOS transistor based on the first relationship curve. ggmax The maximum gate small-signal capacitance C ggmax That is, the standard gate oxide capacitance C. ox01 .

8. The testing system according to claim 7, characterized in that, The first power supply device is further configured to apply a first DC bias voltage to the gate of the standard MOS transistor to make the standard MOS transistor in a strong inversion state, and to apply a second DC bias voltage to the gate of the MOS transistor under test to make the MOS transistor under test in a strong inversion state; the second power supply device is further configured to apply a small signal AC current with a preset frequency to the gate of the MOS transistor under test. Wherein, the first DC bias voltage is greater than the threshold voltage of the standard MOS transistor, and the second DC bias voltage is greater than the threshold voltage of the MOS transistor under test.

9. The testing system according to claim 8, characterized in that, The testing apparatus is also used to subject the MOS transistor under test to a second temperature and to measure the third gate small-signal capacitance C of the standard MOS transistor. gg03 The computing device is further configured to operate according to the preset frequency and the third gate small-signal capacitor C. gg03 and the gate oxide capacitance C to be tested ox02 The polysilicon gate capacitance C of the MOS transistor under test is obtained. poly ; Wherein, the second temperature is less than the critical temperature, and the critical temperature is the maximum gate small-signal capacitance C corresponding to the MOS transistor under test. ggmax1 The corresponding test temperature.

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