A LDMOS process TVS device and a manufacturing method thereof

Abstract

The present invention provides an LDMOS process TVS device and a manufacturing method thereof, wherein an inner ring area of ​​the TVS device is formed with a cell area, a trigger area and an inner ring terminal area; a first MOS tube is formed in the cell area, and a TVS tube is formed in the trigger area; a first gate resistor and a first gate structure are formed on a substrate body of the inner ring area; a second MOS tube, a second gate resistor and a second gate structure are formed on a substrate body of the outer ring area; metal is interconnected so that the anode of the TVS tube is connected to the gate of the first MOS tube through the first gate structure; one end of the first gate resistor is connected to the anode and the gate structure of the TVS tube, and the other end is connected to the source of the first MOS tube; the drain of the first MOS is connected to the cathode of the TVS tube and the drain of the second MOS tube; one end of the second gate resistor is connected to the second gate structure and the source of the first MOS, and the other end is connected to the source of the second MOS tube.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS process TVS device and a manufacturing method thereof. Background Art

[0002] Transient voltage suppressors (TVS) are widely used in the field of ESD protection. Traditional TVS devices generally adopt a diode structure, which has the disadvantages of high clamping voltage and large clamping coefficient, making it difficult to effectively protect circuits.

[0003] In the prior art, there is provided a TVS device with an SCR structure, which can effectively reduce the clamping coefficient. However, the TVS device using this structure has problems such as high trigger voltage, easy triggering of latch effect, and difficulty in optimizing the ESD window.

[0004] Therefore, how to reduce the clamping coefficient without affecting other performance of the device is a problem that needs to be solved at present. Summary of the invention

[0005] The purpose of the present invention is to provide an LDMOS process TVS device and a manufacturing method thereof, which can reduce the device clamping coefficient and improve the electrostatic protection and current discharge capabilities of the device.

[0006] In order to achieve the above object, the present invention provides an LDMOS process TVS device, comprising:

[0007] A substrate body, wherein the substrate body includes an inner ring area and an outer ring area from the center to the periphery; a cell area, a trigger area and an inner ring terminal area are formed in the inner ring area; a first MOS tube is formed in the cell area, and a TVS tube is formed in the trigger area;

[0008] A first gate resistor and a first gate structure are formed on the substrate body of the inner ring area; the first gate structure is connected to the gate of the first MOS tube;

[0009] A second MOS tube, a second gate resistor, and a second gate structure are formed on the substrate body of the outer ring area, and the second gate structure is connected to the gate of the second MOS tube;

[0010] Interconnecting metal, so that the anode of the TVS tube is connected to the gate of the first MOS tube through the first gate structure; one end of the first gate resistor is connected to the anode of the TVS tube and the first gate structure, and the other end is connected to the source of the first MOS tube; the drain of the first MOS is connected to the cathode of the TVS tube and the drain of the second MOS tube; one end of the second gate resistor is connected to the second gate structure and the source of the first MOS, and the other end is connected to the source of the second MOS tube;

[0011] The first MOS transistor and the second MOS transistor are manufactured by LDMOS process, and the interconnection metals are both arranged on the same side of the substrate body.

[0012] In an optional solution, the inner circle terminal area surrounds the outer periphery of the cell area; the inner circle terminal area includes a pressure-dividing inner ring and a pressure-dividing outer ring, and the trigger area is between the pressure-dividing inner ring and the pressure-dividing outer ring.

[0013] In an optional solution, the cellular area is located at the center of the inner circle area, the trigger area is located at one side edge of the cellular area, and the inner circle terminal area is annular, enclosing the cellular area and the trigger area.

[0014] In an optional solution, the substrate body includes a substrate of a first conductivity type and a homogeneous epitaxial layer formed on the substrate, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer;

[0015] The trigger region includes: a first deep body region and a first well region of the first conductivity type that are heavily doped in the epitaxial layer, and a first injection region of the second conductivity type that is formed in the first well region. The first deep body region and the first injection region constitute the TVS tube in the form of a diode.

[0016] In an optional scheme, the cell region and the cell region to the trigger region include: a second well region of the second conductivity type formed in the epitaxial layer, a second injection region of the second conductivity type heavily doped formed in the second well region; a second deep body region of the first conductivity type heavily doped formed in the epitaxial layer, a third well region of the first conductivity type formed on the upper periphery of the deep body region; a third injection region of the second conductivity type formed in the third well region; and polycrystalline silicon formed above the epitaxial layer; wherein the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polycrystalline silicon constitutes the gate of the first MOS tube, the first gate structure and the first gate resistor, or the second well region constitutes the first gate resistor.

[0017] In an optional solution, an annular isolation oxide ring is provided between the inner ring area and the outer ring area.

[0018] In an optional solution, the TVS device further includes an outer ring terminal region surrounding the outer ring region, the outer ring terminal region includes an inner voltage divider ring and an outer voltage divider ring, and the inner voltage divider ring and the outer voltage divider ring are annular polysilicon columns.

[0019] The present invention also provides a method for manufacturing a TVS device using an LDMOS process, comprising:

[0020] Providing a substrate body, the substrate body comprising a substrate of a first conductivity type and a homogeneous epitaxial layer formed on the substrate, wherein the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer;

[0021] An inner circle area and an outer circle area are planned, and an inner circle cell area, a trigger area and an inner circle terminal area are planned in the inner circle area, and an outer circle cell area is planned in the outer circle area;

[0022] A deep body region heavily doped with the first conductivity type is formed in the epitaxial layer by an implantation and diffusion process, wherein the deep body region located in the trigger region is defined as a first deep body region, and the deep body regions located in the inner ring cell region and the outer ring cell region are defined as a second deep body region;

[0023] forming a first oxide layer covering the epitaxial layer and the deep body region;

[0024] forming a first silicon nitride on the first oxide layer;

[0025] Forming a lightly doped second well region of the second conductivity type in the epitaxial layer of the inner ring cell region and the outer ring cell region by using photolithography, etching, and implantation processes;

[0026] forming a second oxide layer on the second well region;

[0027] removing the first silicon nitride on the first oxide layer by an etching process;

[0028] Using an implantation process and the second oxide layer as a mask to form a lightly doped well region of the first conductivity type in the epitaxial layer, wherein the well region located in the trigger region is defined as a first well region, and the well regions located in the inner ring cell region and the outer ring cell region are defined as a third well region;

[0029] Removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer by an etching process;

[0030] forming a third oxide layer on the epitaxial layer by using thermal oxidation or thin film process;

[0031] Depositing a second silicon nitride on the third oxide layer by using a thin film process;

[0032] Removing part of the second silicon nitride by photolithography and etching process, and forming a fourth oxide layer on the epitaxial layer by thermal oxidation process;

[0033] removing the remaining second silicon nitride by an etching process, and forming a fifth oxide layer on the epitaxial layer by a thermal oxidation process;

[0034] Depositing polysilicon on the fourth oxide layer and the fifth oxide layer by using a thin film process; removing part of the polysilicon by using an etching process;

[0035] Using photolithography and implantation processes, a first implantation region heavily doped with the second conductivity type is formed in the first well region, a second implantation region heavily doped with the second conductivity type is formed in the second well region, and a third implantation region heavily doped with the second conductivity type is formed in the third well region;

[0036] forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;

[0037] Etching the sixth oxide layer and the fifth oxide layer by using photolithography and etching processes to form a contact hole on the epitaxial layer;

[0038] forming interconnecting metal in the metal hole and on the upper surface of the substrate body;

[0039] The first deep body region and the first injection region form a TVS tube in the form of a diode;

[0040] Located in the inner ring area: the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polysilicon constitutes the gate, the first gate structure and the first gate resistor of the first MOS tube, or the second well region constitutes the first gate resistor; the first gate structure is connected to the gate of the first MOS tube;

[0041] Located in the outer ring area: the second injection region constitutes the drain of the second MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the second MOS tube, the polysilicon constitutes the gate, the second gate structure and the second gate resistor of the second MOS tube, or the second well region constitutes the second gate resistor; the second gate structure is connected to the gate of the second MOS tube;

[0042] The interconnecting metal connects the anode of the TVS tube to the gate of the first MOS tube through the first gate structure; connects one end of the first gate resistor to the anode of the TVS tube and the first gate structure, and the other end to the source of the first MOS tube; connects the drain of the first MOS to the cathode of the TVS tube and the drain of the second MOS tube; connects one end of the second gate resistor to the second gate structure and the source of the first MOS, and the other end to the source of the second MOS tube; and connects the first polysilicon in the inner cell region to the source of the first MOS tube.

[0043] In an optional solution, the inner ring terminal region surrounds the outer periphery of the inner ring cell region;

[0044] The inner ring terminal area includes a pressure-dividing inner ring and a pressure-dividing outer ring, and the trigger area is between the pressure-dividing inner ring and the pressure-dividing outer ring.

[0045] In an optional solution, the inner circle cellular area is located at the center of the inner circle area, the trigger area is located at one side edge of the inner circle cellular area, and the inner circle terminal area is annular, enclosing the inner circle cellular area and the trigger area.

[0046] In an optional solution, the method further comprises: forming an annular isolation oxide ring between the inner ring area and the outer ring area.

[0047] In an optional solution, the junction depth of the deep body region is greater than the junction depth of the second well region.

[0048] In an optional embodiment, the deep body region is connected to the substrate.

[0049] The beneficial effects of the present invention are:

[0050] The present invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube. The MOS tube has a negative temperature coefficient. These two points make the present invention have a smaller dynamic resistance per unit area compared with traditional TVS devices, reduce the device clamping coefficient, and improve the device's electrostatic protection and current discharge capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0052] Figure 1 A schematic diagram of the structure of a LDMOS process TVS device according to an embodiment of the present invention is shown.

[0053] Figure 2 A circuit diagram of an LDMOS process TVS device according to an embodiment of the present invention is shown.

[0054] Figure 3 A distribution diagram of the inner ring area of ​​a LDMOS process TVS device according to an embodiment of the present invention is shown.

[0055] Figure 4 A distribution diagram of the inner ring area of ​​a LDMOS process TVS device according to another embodiment of the present invention is shown.

[0056] Figures 5 to 18A schematic structural diagram corresponding to cross sections at different positions during the manufacturing process of a TVS device using an LDMOS process according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0057] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0058] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0059] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0060] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] Example 1

[0062] Reference Figures 1 to 18 This embodiment provides a LDMOS process TVS device, including:

[0063] A substrate body, wherein the substrate body includes an inner ring area and an outer ring area from the center to the periphery; a cell area 200, a trigger area 210 and an inner ring terminal area 201 are formed in the inner ring area; a first MOS tube is formed in the cell area 200, and a TVS tube is formed in the trigger area 210;

[0064] A first gate resistor 202 and a first gate structure 203 are formed on the substrate body of the inner ring area; the first gate structure 203 is connected to the gate of the first MOS tube;

[0065] A second MOS tube, a second gate resistor, and a second gate structure are formed on the substrate body of the outer ring area, and the second gate structure is connected to the gate of the second MOS tube;

[0066] Interconnecting metal, so that the anode of the TVS tube is connected to the gate of the first MOS tube through the first gate structure 203; one end of the first gate resistor 202 is connected to the anode of the TVS tube and the first gate structure 203, and the other end is connected to the source of the first MOS tube; the drain of the first MOS is connected to the cathode of the TVS tube and the drain of the second MOS tube; one end of the second gate resistor is connected to the second gate structure and the source of the first MOS, and the other end is connected to the source of the second MOS tube;

[0067] The first MOS transistor and the second MOS transistor are manufactured by LDMOS process, and the interconnection metals are both arranged on the same side of the substrate body.

[0068] Reference Figure 3In this embodiment, the inner ring terminal area 201 surrounds the outer periphery of the cell area 200; the inner ring terminal area 201 includes an inner pressure division ring and an outer pressure division ring, and the trigger area 210 is between the inner pressure division ring and the outer pressure division ring. The inner pressure division ring and the outer pressure division ring are both an annular polysilicon column surrounding the cell area and a first oxide layer on the outer periphery of the annular polysilicon column.

[0069] Reference Figure 4 In another embodiment, the cellular area is located at the center of the inner circle area, the trigger area 210 is located at one side edge of the cellular area 200 , and the inner circle terminal area 201 is annular, enclosing the cellular area 200 and the trigger area 210 .

[0070] In this embodiment, the substrate body includes a substrate of a first conductive type and a homoepitaxial layer formed on the substrate, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer; the trigger region includes: a first deep body region of heavily doped first conductive type and a first well region of the first conductive type formed in the epitaxial layer, and a first injection region of the second conductive type formed in the first well region, and the first deep body region and the first injection region constitute the TVS tube in the form of a diode.

[0071] The cell region and the cell region to the trigger region include: a second well region of the second conductivity type formed in the epitaxial layer, a second injection region of the second conductivity type heavily doped formed in the second well region; a second deep body region of the first conductivity type heavily doped formed in the epitaxial layer, a third well region of the first conductivity type formed at the upper periphery of the deep body region; a third injection region of the second conductivity type formed in the third well region; and polysilicon formed above the epitaxial layer; wherein the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polysilicon constitutes the gate of the first MOS tube, the first gate structure and the first gate resistor, or the second well region constitutes the first gate resistor.

[0072] An annular isolation oxidation ring is provided between the inner ring area and the outer ring area.

[0073] The TVS device further includes an outer ring terminal region surrounding the outer ring region, wherein the outer ring terminal region includes an inner voltage divider ring and an outer voltage divider ring, wherein the inner voltage divider ring and the outer voltage divider ring are annular polysilicon columns.

[0074] It should be noted that, in the present application, one of the first conductivity type and the second conductivity type is N-type, and the other is P-type.

[0075] Example 2

[0076] This embodiment provides a method for manufacturing a TVS device using an LDMOS process, which can manufacture the TVS device of Embodiment 1. The manufacturing method includes:

[0077] Providing a substrate body, the substrate body comprising a substrate of a first conductivity type and a homogeneous epitaxial layer formed on the substrate, wherein the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer;

[0078] An inner circle area and an outer circle area are planned, and an inner circle cell area (the inner circle cell area is the area where the first MOS tube is formed later), a trigger area (the trigger area is the area where the TVS tube is formed later) and an inner circle terminal area are planned in the inner circle area, and an outer circle cell area (the outer circle cell area is the area where the second MOS tube is formed) is planned in the outer circle area;

[0079] A deep body region heavily doped with the first conductivity type is formed in the epitaxial layer by an implantation and diffusion process, wherein the deep body region located in the trigger region is defined as a first deep body region, and the deep body regions located in the inner ring cell region and the outer ring cell region are defined as a second deep body region;

[0080] forming a first oxide layer covering the epitaxial layer and the deep body region;

[0081] forming a first silicon nitride on the first oxide layer;

[0082] Forming a lightly doped second well region of the second conductivity type in the epitaxial layer of the inner ring cell region and the outer ring cell region by using photolithography, etching, and implantation processes;

[0083] forming a second oxide layer on the second well region;

[0084] removing the first silicon nitride on the first oxide layer by an etching process;

[0085] Using an implantation process and the second oxide layer as a mask to form a lightly doped well region of the first conductivity type in the epitaxial layer, wherein the well region located in the trigger region is defined as a first well region, and the well regions located in the inner ring cell region and the outer ring cell region are defined as a third well region;

[0086] Removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer by an etching process;

[0087] forming a third oxide layer on the epitaxial layer by using thermal oxidation or thin film process;

[0088] Depositing a second silicon nitride on the third oxide layer by using a thin film process;

[0089] Removing part of the second silicon nitride by photolithography and etching process, and forming a fourth oxide layer on the epitaxial layer by thermal oxidation process;

[0090] removing the remaining second silicon nitride by an etching process, and forming a fifth oxide layer on the epitaxial layer by a thermal oxidation process;

[0091] Depositing polysilicon on the fourth oxide layer and the fifth oxide layer by using a thin film process; removing part of the polysilicon by using an etching process;

[0092] Using photolithography and implantation processes, a first implantation region heavily doped with the second conductivity type is formed in the first well region, a second implantation region heavily doped with the second conductivity type is formed in the second well region, and a third implantation region heavily doped with the second conductivity type is formed in the third well region;

[0093] forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;

[0094] Etching the sixth oxide layer and the fifth oxide layer by using photolithography and etching processes to form a contact hole on the epitaxial layer;

[0095] forming interconnecting metal in the metal hole and on the upper surface of the substrate body;

[0096] The first deep body region and the first injection region form a TVS tube in the form of a diode;

[0097] Located in the inner ring area: the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polysilicon constitutes the gate, the first gate structure and the first gate resistor of the first MOS tube, or the second well region constitutes the first gate resistor; the first gate structure is connected to the gate of the first MOS tube;

[0098] Located in the outer ring area: the second injection region constitutes the drain of the second MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the second MOS tube, the polysilicon constitutes the gate, the second gate structure and the second gate resistor of the second MOS tube, or the second well region constitutes the second gate resistor; the second gate structure is connected to the gate of the second MOS tube;

[0099] The interconnecting metal connects the anode of the TVS tube to the gate of the first MOS tube through the first gate structure; connects one end of the first gate resistor to the anode of the TVS tube and the first gate structure, and the other end to the source of the first MOS tube; connects the drain of the first MOS to the cathode of the TVS tube and the drain of the second MOS tube; connects one end of the second gate resistor to the second gate structure and the source of the first MOS, and the other end to the source of the second MOS tube; and connects the first polysilicon in the inner cell region to the source of the first MOS tube.

[0100] The distribution forms of the inner cell area, trigger area and inner terminal area in the inner area include the following two types:

[0101] 1. The inner ring terminal area surrounds the outer periphery of the inner ring cell area; the inner ring terminal area includes a pressure-dividing inner ring and a pressure-dividing outer ring, and the trigger area is between the pressure-dividing inner ring and the pressure-dividing outer ring.

[0102] 2. The inner circle cellular area is located at the center of the inner circle area, the trigger area is located at one side edge of the inner circle cellular area, and the inner circle terminal area is annular, enclosing the inner circle cellular area and the trigger area.

[0103] The MOS tube of this embodiment is manufactured by LDMOS process. The manufacturing method of the TVS device of this embodiment is briefly described below:

[0104] Reference Figures 5 to 18 , the following briefly describes the manufacturing method of the TVS device of this embodiment:

[0105] Step S1, growing an epitaxial layer P-EPI of a first conductivity type on a heavily doped silicon substrate P+SUB of a first conductivity type (P type);

[0106] Step S2, forming a hard mask on the epitaxial layer P-EPI by using thermal oxidation or thin film process;

[0107] Step S3, etching the hard mask by using a photolithography + etching process, and forming a Deep P+ region (deep body region, including a first deep body region located in the trigger region and a second deep body region located in the inner cell region and the outer cell region) on the epitaxial layer by an implantation and diffusion process;

[0108] Preferably, the junction depth is 2um-3um greater than the NW junction depth;

[0109] Preferably, it is connected to the substrate P+SUB;

[0110] Step S4, removing the hard mask on the surface of the epitaxial layer P-EPI;

[0111] Step S5, forming a first oxide layer by using thermal oxidation or thin film process;

[0112] Step S6, forming a first silicon nitride on the first oxide layer by using a thin film process;

[0113] Step S7, forming a lightly doped second conductivity type N-well (second well region) by photolithography, etching, and implantation processes;

[0114] Step S8, forming a second oxide layer on the epitaxial layer P-EPI by using a diffusion process;

[0115] Step S9, removing the silicon nitride on the first oxide layer by an etching process;

[0116] Step S10, using an implantation process and the second oxide layer as a mask to form a lightly doped first conductivity type P-well (a first well region and a third well region);

[0117] Step S11, removing the first and second oxide layers on the surface of the epitaxial layer P-EPI by an etching process;

[0118] Step S12, forming a third oxide layer on the epitaxial layer P-EPI by using thermal oxidation or thin film process;

[0119] Step S13, depositing a second silicon nitride on the third oxide layer using a thin film process;

[0120] Step S14, removing part of the second silicon nitride by photolithography and etching process, and forming a fourth oxide layer on the epitaxial layer by thermal oxidation process;

[0121] Step S15, removing the remaining second silicon nitride by an etching process, and forming a fifth oxide layer on the epitaxial layer by a thermal oxidation process;

[0122] Step 16, depositing polysilicon on the fourth and fifth oxide layers using a thin film process;

[0123] Step 17, using an etching process to remove part of the polysilicon, and using photolithography and implantation processes to form an N+ implantation region on the epitaxial layer (including a first implantation region (located in the first well region of the trigger region), a second implantation region (located in the second well region of the inner cell region and the outer cell region), and a third implantation region (located in the third well region of the inner cell region and the outer cell region);

[0124] Step 18, forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process;

[0125] Step 19, etching the sixth and fifth oxide layers by photolithography and etching processes to form contact holes on the epitaxial layer;

[0126] Step 20, depositing interconnect metal in the contact holes and on the upper surface of the substrate body;

[0127] Preferably, a multi-layer metal process can be used to save area and form better interconnections.

[0128] Preferably, the method also includes: forming an annular isolation trench surrounding the inner ring area between the inner ring area and the outer ring area, the depth of the isolation trench being 2-3um greater than the thickness of the epitaxial layer 110; and then using thermal oxidation or thin film technology to form an oxide layer in the isolation trench to form an isolation oxide ring.

[0129] It should be noted that the second MOS tube, second gate resistor and second gate structure formed in the outer ring area are respectively formed in the same step with the first MOS tube, first gate resistor and first gate structure in the inner ring area using the same materials, but at different positions.

[0130] The above two embodiments have the following advantages:

[0131] First, this embodiment utilizes the LDMOS process and is compatible with existing processes;

[0132] Second, the clamping coefficient of traditional TVS devices is generally 1.2-1.4. Under the existing equipment conditions, this embodiment improves the LDMOS process, adds TVS, and reduces the clamping coefficient to a level below 1.1, thereby improving the device's electrostatic protection, current discharge capacity and unit area utilization.

[0133] Third, the MOS process TVS is nested twice, reducing the gate resistance requirements.

[0134] Example 3

[0135] The difference between this embodiment and the above two embodiments is that, in the first two embodiments, the first gate resistor in the inner ring area is formed by polysilicon in the inner ring area, and the second gate resistor in the outer ring area is formed by polysilicon in the outer ring area, while in this embodiment, the first gate resistor in the inner ring area is formed by the second well area in the inner ring area, and the second gate resistor in the outer ring area is formed by the second well area in the outer ring area.

[0136] It should be noted that Example 3 of this specification only describes the parts that are different from Example 1, and the parts that are the same as Example 1 can refer to Example 1.

[0137] The present invention converts the dynamic resistance of the TVS tube into the transconductance of the MOS tube. The MOS tube has a negative temperature coefficient. These two points make the present invention have a smaller dynamic resistance per unit area compared with traditional TVS devices, reduce the device clamping coefficient, and improve the device's electrostatic protection and current discharge capabilities.

[0138] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A LDMOS process TVS device, characterized in that: include: A substrate body, wherein the substrate body includes an inner ring area and an outer ring area from the center to the periphery; a cell area, a trigger area and an inner ring terminal area are formed in the inner ring area; a first MOS tube is formed in the cell area, and a TVS tube is formed in the trigger area; A first gate resistor and a first gate structure are formed on the substrate body of the inner ring area; the first gate structure is connected to the gate of the first MOS tube; A second MOS tube, a second gate resistor, and a second gate structure are formed on the substrate body of the outer ring area, and the second gate structure is connected to the gate of the second MOS tube; Interconnecting metal so that the anode of the TVS tube is connected to the gate of the first MOS tube through the first gate structure; one end of the first gate resistor is connected to the anode of the TVS tube and the first gate structure, and the other end is connected to the source of the first MOS tube; Connecting the drain of the first MOS tube to the cathode of the TVS tube and the drain of the second MOS tube; One end of the second gate resistor is connected to the second gate structure and the source of the first MOS, and the other end is connected to the source of the second MOS tube; The first MOS transistor and the second MOS transistor are manufactured by LDMOS process, and the interconnection metals are both arranged on the same side of the substrate body.

2. The LDMOS process TVS device according to claim 1, characterized in that: The inner ring terminal area surrounds the outer periphery of the cell area; The inner ring terminal area includes a pressure-dividing inner ring and a pressure-dividing outer ring, and the trigger area is between the pressure-dividing inner ring and the pressure-dividing outer ring.

3. The LDMOS process TVS device according to claim 1, characterized in that: The cellular area is located at the center of the inner circle area, the trigger area is located at one side edge of the cellular area, and the inner circle terminal area is annular and surrounds the cellular area and the trigger area.

4. The LDMOS process TVS device according to claim 1, characterized in that: The substrate body comprises a substrate of a first conductivity type and a homogeneous epitaxial layer formed on the substrate, wherein the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer; The trigger region includes: a first deep body region and a first well region of the first conductivity type that are heavily doped in the epitaxial layer, and a first injection region of the second conductivity type that is formed in the first well region. The first deep body region and the first injection region constitute the TVS tube in the form of a diode.

5. The LDMOS process TVS device according to claim 4, characterized in that: The cell region and the cell region to the trigger region include: a second well region of the second conductivity type formed in the epitaxial layer, a second injection region of the second conductivity type heavily doped formed in the second well region; a second deep body region of the first conductivity type heavily doped formed in the epitaxial layer, a third well region of the first conductivity type formed at the upper periphery of the deep body region; a third injection region of the second conductivity type formed in the third well region; and polysilicon formed above the epitaxial layer; wherein the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polysilicon constitutes the gate of the first MOS tube, the first gate structure and the first gate resistor, or the second well region constitutes the first gate resistor.

6. The LDMOS process TVS device according to claim 1, characterized in that: An annular isolation oxidation ring is provided between the inner ring area and the outer ring area.

7. The LDMOS process TVS device according to claim 1, characterized in that: The TVS device further includes an outer ring terminal region surrounding the outer ring region, wherein the outer ring terminal region includes an inner voltage divider ring and an outer voltage divider ring, wherein the inner voltage divider ring and the outer voltage divider ring are annular polysilicon columns.

8. A method for manufacturing a TVS device using LDMOS technology, characterized in that: include: Providing a substrate body, the substrate body comprising a substrate of a first conductivity type and a homogeneous epitaxial layer formed on the substrate, wherein the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer; An inner circle area and an outer circle area are planned, and an inner circle cell area, a trigger area and an inner circle terminal area are planned in the inner circle area, and an outer circle cell area is planned in the outer circle area; A deep body region heavily doped with the first conductivity type is formed in the epitaxial layer by an implantation and diffusion process, wherein the deep body region located in the trigger region is defined as a first deep body region, and the deep body regions located in the inner ring cell region and the outer ring cell region are defined as a second deep body region; forming a first oxide layer covering the epitaxial layer and the deep body region; forming a first silicon nitride on the first oxide layer; Forming a lightly doped second well region of the second conductivity type in the epitaxial layer of the inner ring cell region and the outer ring cell region by using photolithography, etching, and implantation processes; forming a second oxide layer on the second well region; removing the first silicon nitride on the first oxide layer by an etching process; Using an implantation process and the second oxide layer as a mask to form a lightly doped well region of the first conductivity type in the epitaxial layer, wherein the well region located in the trigger region is defined as a first well region, and the well regions located in the inner ring cell region and the outer ring cell region are defined as a third well region; Removing the first oxide layer and the second oxide layer on the surface of the epitaxial layer by an etching process; forming a third oxide layer on the epitaxial layer by using thermal oxidation or thin film process; Depositing a second silicon nitride on the third oxide layer by using a thin film process; Removing part of the second silicon nitride by photolithography and etching process, and forming a fourth oxide layer on the epitaxial layer by thermal oxidation process; removing the remaining second silicon nitride by an etching process, and forming a fifth oxide layer on the epitaxial layer by a thermal oxidation process; Depositing polysilicon on the fourth oxide layer and the fifth oxide layer by using a thin film process; Removing part of the polysilicon by etching process; Using photolithography and implantation processes, a first implantation region heavily doped with the second conductivity type is formed in the first well region, a second implantation region heavily doped with the second conductivity type is formed in the second well region, and a third implantation region heavily doped with the second conductivity type is formed in the third well region; forming a sixth oxide layer on the fourth oxide layer, the fifth oxide layer and the polysilicon by using a thin film process; Etching the sixth oxide layer and the fifth oxide layer by using photolithography and etching processes to form a contact hole on the epitaxial layer; forming interconnect metal in the contact hole and on the upper surface of the substrate body; The first deep body region and the first injection region form a TVS tube in the form of a diode; Located in the inner ring area: the second injection region constitutes the drain of the first MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the first MOS tube, the polysilicon constitutes the gate, the first gate structure and the first gate resistor of the first MOS tube, or the second well region constitutes the first gate resistor; the first gate structure is connected to the gate of the first MOS tube; Located in the outer ring area: the second injection region constitutes the drain of the second MOS tube, the second deep body region, the third well region and the third injection region together constitute the source of the second MOS tube, the polysilicon constitutes the gate, the second gate structure and the second gate resistor of the second MOS tube, or the second well region constitutes the second gate resistor; the second gate structure is connected to the gate of the second MOS tube; The interconnecting metal connects the anode of the TVS tube to the gate of the first MOS tube through the first gate structure; one end of the first gate resistor is connected to the anode of the TVS tube and the first gate structure, and the other end is connected to the source of the first MOS tube; The drain of the first MOS is connected to the cathode of the TVS tube and the drain of the second MOS tube; one end of the second gate resistor is connected to the second gate structure and the source of the first MOS, and the other end is connected to the source of the second MOS tube; The polysilicon in the inner cell region is connected to the source of the first MOS tube.

9. The method for manufacturing a TVS device using LDMOS technology according to claim 8, wherein: The inner circle terminal area surrounds the outer periphery of the inner circle cell area; The inner ring terminal area includes a pressure-dividing inner ring and a pressure-dividing outer ring, and the trigger area is between the pressure-dividing inner ring and the pressure-dividing outer ring.

10. The method for manufacturing a TVS device using LDMOS technology according to claim 8, wherein: The inner circle cellular area is located at the center of the inner circle area, the trigger area is located at one side edge of the inner circle cellular area, and the inner circle terminal area is annular, enclosing the inner circle cellular area and the trigger area.

11. The method for manufacturing a TVS device using LDMOS technology according to claim 8, wherein: The method further includes: forming an annular isolation oxide ring between the inner ring area and the outer ring area.

12. The method for manufacturing a TVS device using LDMOS technology according to claim 8, wherein: A junction depth of the deep body region is greater than a junction depth of the second well region.

13. The method for manufacturing a TVS device using LDMOS technology according to claim 8, wherein: The deep body region is in contact with the substrate.

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