Trimming circuit and chip comprising same, trimming method

Abstract

This invention discloses a calibration circuit, a chip including the same, and a calibration method. The calibration circuit according to an embodiment of the invention includes an input terminal for receiving a voltage control signal, wherein the voltage control signal is directly or inversely proportional to an ideal output voltage; a sampling unit connected to the output terminal to sample and obtain a test voltage; a first test voltage being a test output voltage corresponding to a first ideal output voltage, and a second test voltage being a test output voltage corresponding to a second ideal output voltage; an arithmetic unit obtaining a proportional deviation parameter based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, and the directly or inversely proportional relationship; and a proportional adjustment unit adjusting the output voltage signal according to the proportional deviation parameter. The calibration circuit and the chip including the same according to an embodiment of the invention can achieve accurate calibration across the entire adjustment range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a trimming circuit, a chip including the circuit, and a trimming method. Background Technology

[0002] In circuits, adjustments are often made to meet different operational requirements or operating modes. Taking display driver chips as an example, display driver chips provide various driving voltages for the screen panel. To meet the needs of adapting to different screens or providing better performance in different operating modes, the voltage generated by the display driver chip needs to have the ability to be precisely adjusted within a wide voltage range.

[0003] In existing display driver voltage generation circuits, circuit adjustment is achieved by adjusting the adjustable resistor corresponding to the operational amplifier based on the error value between the ideal voltage and the test voltage. However, while existing adjustment methods can ensure a significant reduction in error at the test voltage, in practical applications, to accommodate different panels or different operating modes of the same panel, the output voltage is often adjusted significantly, leading to an increase in error voltage. Traditional voltage adjustment circuits cannot guarantee adjustment accuracy and are unlikely to meet current requirements.

[0004] Therefore, it is desirable to have a new tuning circuit, including the chip and tuning method, that can overcome the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a voltage adjustment circuit and a chip including the same, an adjustment method, and in particular a voltage adjustment circuit for display driving, thereby achieving accurate calibration across the entire adjustment range.

[0006] According to one aspect of the present invention, a trimming circuit is provided, comprising: an input terminal for receiving a voltage control signal; different values ​​of the voltage control signal correspond to different values ​​of ideal output voltage, and the voltage control signal is directly proportional or inversely proportional to the ideal output voltage; an output terminal for outputting a voltage signal; a sampling unit connected to the output terminal to sample and obtain a test voltage, the test voltage including a first test voltage and a second test voltage; the first test voltage being a test output voltage corresponding to a first ideal output voltage, and the second test voltage being a test output voltage corresponding to a second ideal output voltage; a calculation unit for obtaining a test proportionality coefficient between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage; the calculation unit obtaining a proportional deviation parameter based on the test proportionality coefficient and the directly proportional or inversely proportional relationship; and a proportional adjustment unit connected to the output terminal for adjusting the output voltage signal output by the output terminal according to the proportional deviation parameter.

[0007] Optionally, the proportional adjustment unit includes a first resistor and a second resistor connected in series, and a first MOSFET and a second MOSFET connected in parallel with the first resistor and the second resistor, respectively;

[0008] The adjustment circuit also includes:

[0009] A control unit is connected to the first MOSFET and the second MOSFET respectively to control the on and off states of the first MOSFET and the second MOSFET respectively.

[0010] When the first MOSFET is turned off, the first resistor is electrically connected to the output terminal; when the second MOSFET is turned off, the second resistor is electrically connected to the output terminal.

[0011] Optionally, the arithmetic unit obtains the test scaling factor and offset parameter between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage.

[0012] An offset adjustment unit is connected to the output terminal and adjusts the output voltage signal output by the output terminal according to the offset parameter.

[0013] Optionally, the offset adjustment unit includes a first branch, the output terminal, and a second branch connected in sequence;

[0014] The first branch includes a first regulating resistor and a first PMOS transistor connected in parallel with the first regulating resistor; the second branch includes a second regulating resistor and a first NMOS transistor connected in parallel with the second regulating resistor;

[0015] The adjustment circuit also includes:

[0016] The control unit is connected to the first PMOS transistor and the first NMOS transistor respectively, and uses the same signal to control the first PMOS transistor and the first NMOS transistor to make the first PMOS transistor turn on and the first NMOS transistor turn off, or the first PMOS transistor turn off and the first NMOS transistor turn on.

[0017] Optionally, the adjustment circuit further includes:

[0018] A preamplifier, which is connected to the input terminal to receive the voltage control signal;

[0019] A proportional adjustment unit, the first end of which is connected to the output terminal of the preamplifier;

[0020] An offset adjustment unit, wherein the first end of the offset adjustment unit is connected to the second end of the proportional adjustment unit;

[0021] The post-stage operational amplifier has its first terminal connected to the second terminal of the offset adjustment unit, and its second terminal connected to the output terminal.

[0022] Optionally, the offset adjustment unit includes a first branch and a second branch; the trimming circuit further includes a voltage divider resistor unit, which includes multiple series resistors.

[0023] The first end of the first branch is connected to the second end of the proportional adjustment unit, and the second end of the first branch is connected to the first end of the voltage divider resistor unit.

[0024] The first end of the second branch is connected to the second end of the voltage divider resistor unit, and the second end of the second branch is grounded;

[0025] The third terminal of the voltage divider resistor unit is connected to the first terminal of the subsequent operational amplifier.

[0026] Optionally, the adjustment circuit further includes:

[0027] A voltage follower, wherein the first terminal of the voltage follower is connected to the output terminal of the preamplifier, and the second terminal of the voltage follower is connected to the first terminal of the proportional adjustment unit.

[0028] According to another aspect of the present invention, a chip is provided, comprising the tuning circuit described above.

[0029] According to another aspect of the present invention, a tuning method is provided, comprising: acquiring a voltage control signal; different values ​​of the voltage control signal correspond to different values ​​of ideal output voltage, and the voltage control signal is directly proportional or inversely proportional to the ideal output voltage; sampling to obtain a test voltage, the test voltage including a first test voltage and a second test voltage; the first test voltage being a test output voltage corresponding to a first ideal output voltage, and the second test voltage being a test output voltage corresponding to a second ideal output voltage; obtaining a test proportionality coefficient between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage; obtaining a proportional deviation parameter based on the test proportionality coefficient and the directly proportional or inversely proportional relationship; and adjusting the output voltage signal according to the proportional deviation parameter.

[0030] Optionally, the adjustment method further includes:

[0031] Based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage, the test scaling factor and offset parameter between the test voltage and the voltage control signal are obtained;

[0032] The output voltage signal is adjusted according to the offset parameter.

[0033] According to the present invention, the adjustment circuit, the chip therein, and the adjustment method thereof, during sampling testing, at least two test voltages are acquired to obtain a proportional deviation coefficient, and adjustment is performed based on the proportional deviation coefficient, thereby achieving accurate calibration across the entire adjustment range.

[0034] Furthermore, during sampling testing, at least two test voltages are acquired to obtain the proportional deviation coefficient and offset parameter, and adjustments are made based on the proportional deviation coefficient and offset parameter, enabling accurate calibration across the entire adjustment range.

[0035] Furthermore, the proportional adjustment unit used for adjusting the proportional deviation parameter achieves the change of the input resistance by controlling the turn-off and turn-on of the MOSFET. The structure is simple and does not require a significant increase in circuit area.

[0036] Furthermore, the offset adjustment unit used for offset parameter adjustment controls at least one set of NMOS transistors and PMOS transistors through the same signal to change the access resistance. The structure is simple and does not require a significant increase in circuit area. Attached Figure Description

[0037] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0038] Figure 1 A schematic diagram of the adjustment circuit according to an embodiment of the present invention is shown.

[0039] Figure 2 A circuit diagram of the adjustment circuit according to Embodiment 1 of the present invention is shown.

[0040] Figure 3 A circuit diagram of an operational amplifier according to Embodiment 1 of the present invention is shown.

[0041] Figure 4 A circuit diagram of the adjustment circuit according to Embodiment 2 of the present invention is shown.

[0042] Figure 5 A flowchart of a tuning method according to an embodiment of the present invention is shown.

[0043] Figure 6 The voltage output curve according to an embodiment of the present invention is shown.

[0044] Figure 7 A schematic diagram showing a comparison of simulation results of the calibration error of the trimming circuit according to an embodiment of the present invention and that of a conventional trimming circuit is presented. Detailed Implementation

[0045] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings.

[0046] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0047] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0048] Figure 1 A schematic diagram of the adjustment circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the adjustment circuit according to an embodiment of the present invention includes an input terminal 100, an output terminal 200, a sampling unit 300, an arithmetic unit 400, and a proportional adjustment unit 500.

[0049] Specifically, input terminal 100 is used to receive voltage control signals. Different values ​​of voltage control signals correspond to different values ​​of ideal output voltage, and the voltage control signal and the ideal output voltage are directly or inversely proportional. For distinction, the ideal output voltages corresponding to different values ​​of voltage control signals can be referred to as the first ideal output voltage, the second ideal output voltage, etc.

[0050] Output terminal 200 is used to output voltage signals. Taking the adjustment circuit applied to the display driver chip as an example, the output voltage signal output by output terminal 200 can be the voltage required for various driving functions of the screen panel, in order to meet the needs of adapting to different screens or providing better performance in different working modes.

[0051] The sampling unit 300 is connected to the output terminal 200 to sample and obtain the test voltage. The test voltage includes a first test voltage and a second test voltage. The first test voltage is the test output voltage corresponding to the first ideal output voltage, and the second test voltage is the test output voltage corresponding to the second ideal output voltage.

[0052] The arithmetic unit 400 obtains a test proportionality coefficient between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage. The arithmetic unit 400 then obtains a proportional deviation coefficient based on the test proportionality coefficient and a direct or inverse proportional relationship. The arithmetic unit 400 is, for example, connected to the sampling unit 300 to acquire the signal sampled by the sampling unit 300.

[0053] The proportional adjustment unit 500 is connected to the output terminal 200 and adjusts the output voltage signal output from the output terminal 200 according to the proportional deviation parameter. The proportional adjustment unit 500 is connected to the arithmetic unit 400, for example, to obtain the proportional deviation parameter.

[0054] In an optional embodiment of the present invention, the arithmetic unit 400 obtains the test ratio coefficient and offset parameter between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage. The adjustment circuit further includes an offset adjustment unit ( Figure 1 (Not shown in the diagram). The offset adjustment unit is connected to the output terminal 200 and adjusts the output voltage signal output by the output terminal 200 according to the offset parameter.

[0055] Figure 2 A circuit diagram of the adjustment circuit according to Embodiment 1 of the present invention is shown. Figure 2 As shown, the adjustment circuit according to Embodiment 1 of the present invention includes a pre-amplifier 700, a proportional adjustment unit 500, an offset adjustment unit 600, and a post-amplifier 900. Optionally, the adjustment circuit further includes a voltage follower 800 and a voltage divider resistor unit 950.

[0056] Specifically, the preamplifier 700 is connected to the input terminal to receive voltage control signals.

[0057] The first terminal of the proportional adjustment unit 500 is connected to the output terminal of the preamplifier 700. The proportional adjustment unit 500 includes, for example, a slope adjustment resistor R3.

[0058] The first terminal of the offset adjustment unit 600 is connected to the second terminal of the proportional adjustment unit 500. The offset adjustment unit 600 includes, for example, offset adjustment resistors R4 and R6. Optionally, the total resistance of the offset adjustment unit 600 (i.e., offset adjustment resistors R4 and R6) connected in the circuit is a fixed value.

[0059] The first terminal of the power amplifier 900 is connected to the second terminal of the offset adjustment unit 600, and the second terminal of the power amplifier 900 is connected to the output terminal.

[0060] Optionally, the adjustment circuit further includes a voltage follower 800 and a voltage divider resistor unit 950. The first terminal of the voltage follower 800 is connected to the output of the pre-amplifier 700, and the second terminal of the voltage follower 800 is connected to the first terminal of the proportional adjustment unit 500. The voltage follower 800 includes, for example, a second-stage operational amplifier AMP1. The first terminal of the voltage divider resistor unit 950 is connected to the offset adjustment resistor R4; the second terminal of the voltage divider resistor unit 950 is connected to the offset adjustment resistor R6; and the third terminal of the voltage divider resistor unit 950 is connected to the first terminal of the subsequent operational amplifier 900. The voltage divider resistor unit 950 includes, for example, multiple series resistors, and the subsequent operational amplifier 900 is connected between these multiple series resistors.

[0061] Furthermore, Figure 3 A circuit diagram of an operational amplifier according to Embodiment 1 of the present invention is shown. Figure 3 The operational amplifier shown can be Figure 2 The preamplifier 700 and / or the power amplifier 900 are shown.

[0062] Specifically, the preamplifier 700 may include one or more Figure 3The operational amplifier (op-amp combination) shown provides a reference voltage for multiple modules within the driver circuit (chip). Other modules use this reference voltage to generate the voltage required by the panel. The voltage follower 800 ensures that its output voltage is the same as the output voltage of the preceding op-amp 700 and provides the necessary drive capability for the load. The load of the voltage follower (second-stage op-amp) 800 can include two sets of adjustable resistors and one set of voltage divider resistors. The internal nodes of the voltage divider resistors are connected to one end of a set of switches, and the other end of the switches is connected to the input terminal of the subsequent op-amp 900. The switching on and off is controlled by an external signal, working in conjunction with a MUX to switch the input voltage of the subsequent op-amp. The subsequent op-amp 900 may include one or more... Figure 3 The operational amplifier (op-amp combination) shown is used to achieve functions such as voltage expansion and positive / negative voltage conversion. In addition, it can also provide strong driving capability to drive the circuits inside the panel.

[0063] Figure 4 A circuit diagram of the adjustment circuit according to Embodiment 2 of the present invention is shown. Figure 4 As shown, the adjustment circuit according to Embodiment 2 of the present invention includes a voltage follower 800, a proportional adjustment unit 500, an offset adjustment unit 600, a voltage divider resistor unit 950, and a control unit ( Figure 4 (Not shown in the image). The offset adjustment unit 600 includes a first branch 610 and a second branch 620.

[0064] The proportional control unit 500 includes a first resistor and a second resistor connected in series, and a first MOSFET and a second MOSFET connected in parallel with the first resistor and the second resistor, respectively. The control unit is connected to the first MOSFET and the second MOSFET respectively to control the conduction and turn-off of the first MOSFET and the second MOSFET. When the first MOSFET is off, the first resistor is electrically connected to the output terminal; when the second MOSFET is off, the second resistor is electrically connected to the output terminal.

[0065] The first branch 610, the output terminal (not shown in the figure), and the second branch 620 are connected sequentially. The first branch includes a first regulating resistor and a first PMOS transistor connected in parallel with the first regulating resistor; the second branch includes a second regulating resistor and a first NMOS transistor connected in parallel with the second regulating resistor. The control unit is connected to the first PMOS transistor and the first NMOS transistor respectively, and uses the same signal to control the first PMOS transistor and the first NMOS transistor to make the first PMOS transistor turn on and the first NMOS transistor turn off, or the first PMOS transistor turn off and the first NMOS transistor turn on. Optionally, the resistance values ​​of the first regulating resistor and the second regulating resistor are the same.

[0066] Specifically, GND represents power ground; R represents a resistor; AMP represents an amplifier; MUX represents an N-to-1 selector controlled by a digital signal; PM represents a P-type transistor, and NM represents an N-type transistor. R31 / R32 / … / R3m represents m resistors, which, together with m P-type transistors MP11 / MP12 / … / MP1m, implement the function of R3; R41 / R42 / … / R4j represents j resistors, which, together with j P-type transistors MP21 / MP22 / … / MP2j, implement the function of R4; R61 / R62 / … / R6j represents j resistors, which, together with j N-type transistors MN21 / MN22 / … / MN2j, implement the function of R6. Figure 2 As shown, the preamplifier 700 provides a reference voltage for the voltage follower (second stage op-amp) 800; the positive input terminal of AMP1 is connected to the output of the preamplifier 700, and the negative input terminal is connected to the output terminal to form a follower.

[0067] The proportional adjustment unit 500 is, for example, a slope adjustment resistor (R3). The offset adjustment unit 600 is, for example, an offset adjustment resistor (R4 / R6). The voltage divider resistor unit 950 is, for example, a voltage divider resistor (R5) composed of N resistors connected in series. R3, R4, R5, and R6 are connected in sequence, with the other end of R3 connected to the output terminal of AMP1 and the other end of R6 connected to GND. Specifically, the slope adjustment resistor R3 is composed of a basic unit consisting of m resistors and MOSFETs. The conduction and cutoff of MP11~MP1m can be controlled by digital signals, thereby adjusting the number of resistors connected to the circuit and thus adjusting the slope of the output characteristic curve. The offset adjustment resistors (R4 / R6) are composed of a basic unit consisting of j resistors and MOSFETs. MP21 and MN21 are controlled by the same signal, MP22 and MN22 are controlled by the same signal, and so on. MP2j and MN2j are controlled by the same signal. Since MP2x and MN2x are pmos and nmos respectively, one of the MOSFETs controlled by the same signal will be in the on state while the other is off. By changing the control signal, a resistor can be moved from above to below the voltage divider resistor unit 950 (MUX), or vice versa, thus adjusting the offset in the output characteristic curve. Optionally, the resistors R4j and R6j corresponding to MP2j and MN2j controlled by the same signal have the same resistance value to ensure that the sum of the resistances of the offset adjustment resistors R4 and R6 (offset adjustment unit 600) connected in the circuit is a fixed value, thereby avoiding new deviations introduced during the offset adjustment process.

[0068] The adjustment circuit provided in this embodiment of the invention measures two or more voltages during testing, calculates the slope and offset errors respectively, and adjusts R3 by digital signal control to adjust the slope of the output characteristic curve to eliminate the slope error Δk. Adjusting R4 / R6 can adjust the offset of the output characteristic curve to eliminate the offset error Δb, thereby achieving the purpose of eliminating errors across the entire output range. Furthermore, the adjustment circuit provided in this embodiment of the invention can maintain the same accuracy of the output voltage across the entire adjustment range without significantly increasing the circuit area, thus meeting the new demands brought about by the development of panel technology and satisfying the performance requirements.

[0069] According to another aspect of the present invention, a chip is provided. The chip includes the tuning circuit described above. Chips according to embodiments of the present invention include, but are not limited to, display driver chips.

[0070] According to another aspect of the present invention, a tuning method is provided. This tuning method is applied, for example, to a tuning circuit as described above. Figure 5 As shown, the adjustment method according to an embodiment of the present invention includes the following steps:

[0071] In step S101, a voltage control signal is acquired;

[0072] Obtain the voltage control signal. Different voltage control signal values ​​correspond to different ideal output voltage values, and the voltage control signal and the ideal output voltage are directly or inversely proportional.

[0073] In step S102, the test voltage is sampled;

[0074] The test voltage is obtained by sampling. The test voltage includes a first test voltage and a second test voltage. The first test voltage is the test output voltage corresponding to the first ideal output voltage, and the second test voltage is the test output voltage corresponding to the second ideal output voltage.

[0075] In step S103, the test ratio coefficient between the test voltage and the voltage control signal is obtained based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage.

[0076] In step S104, the proportional deviation parameter is obtained based on the test proportionality coefficient and the direct or inverse proportional relationship;

[0077] In step S105, the output voltage signal is adjusted according to the proportional deviation parameter.

[0078] Optionally, the adjustment method according to embodiments of the present invention further includes:

[0079] Based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage, the test ratio coefficient and offset parameter between the test voltage and the voltage control signal are obtained.

[0080] Adjust the output voltage signal according to the offset parameter.

[0081] Figure 6 The voltage output curve according to an embodiment of the present invention is shown. Figure 7 A schematic diagram comparing simulation results of the calibration error of the trimming circuit according to an embodiment of the present invention with that of a conventional trimming circuit is shown. (Combined with...) Figures 4 to 7 As shown, in one specific embodiment, the adjustment circuit is a circuit with an adjustable output voltage function, and the voltage output characteristic curve of this circuit, which characterizes the output voltage, is shown in the figure. Figure 6 As shown in the diagram, the horizontal axis represents the Digital Code input digital control signal, with each Digital Code corresponding to an output voltage. The vertical axis, Vout, represents the output voltage value. For an ideal power supply without any errors, its output characteristic curve is a straight line with a slope equal to the design value and a zero offset. This can be represented by Vout = kx + b, where x represents the decimal value of the Digital Code, and b represents the output voltage value when the Digital Code is 0. The applicant discovered that actual power supplies are affected by design, manufacturing processes, and other factors, causing changes in the slope of the output characteristic curve or introducing offsets, thus generating errors. Figure 6 Figures (a) and (b) illustrate the effects on the output voltage when only the offset Δb and the slope error Δk exist, respectively. For a system where both Δk and Δb exist, its output characteristic curve can be expressed as follows: Figure 6 In the middle (c), it is indicated that the output voltage can be represented by Vout=(k+Δk)x+b+Δb.

[0082] During sampling testing, two voltages are measured, corresponding to Digital Codes x1 and x2 of the digital control signal. The measured output voltages are Vout1 and Vout2. Based on the output characteristic curve, we can obtain:

[0083] Vout1 = (k + Δk)x1 + b + Δb

[0084] Vout2 = (k + Δk)x2 + b + Δb

[0085] Where k is the output difference between two adjacent Digital Codes under ideal conditions, b is the output voltage value when the Digital Code is 0 under ideal conditions, Δk is the change in k when considering non-ideal factors, and Δb is the change in b when considering non-ideal factors. It should be noted that k and b can be determined according to actual needs.

[0086] During testing and calibration, the slope and offset errors can be calculated using the method described above. The slope k and offset b can then be adjusted by changing the number of resistors connected to R3 and / or R4 and / or R6, ensuring the voltage remains relatively accurate across the entire output voltage range. Optionally, when calibrating using the above calculation method, measurements can be taken at multiple voltages, or multiple measurements can be performed at each voltage level and the average value taken, further reducing the impact of measurement errors.

[0087] In the above embodiments of the present invention, the circuit used in the error calibration method of the present invention is designed using CMOS (Complementary Metal Oxide Semiconductor) technology. Combined with... Figures 1 to 7 As shown, an offset voltage is introduced at the input terminals of AMP2 and AMP3 to simulate the mismatch generated during actual manufacturing. The output voltage is then measured and calibrated according to the method (algorithm) described above. (Refer to...) Figure 7 As shown, calibration was performed at Digital Code=36 using the same amplifier and with the same bias current, operating voltage, process environment, and operating temperature. Simulation results show that the output error is smaller after calibration at the calibration point. However, calibration using a traditional (existing) voltage trimming circuit results in a larger error across the entire output range, approximately ±40mV. Calibration using the novel voltage trimming circuit of this invention results in an error of less than 2.4mV across the entire output range. This comparison demonstrates that the novel voltage trimming circuit of this invention exhibits a superior output voltage error across the entire output range compared to the traditional voltage trimming circuit.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0089] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A tuning circuit, characterized in that, include: The input terminal is used to receive voltage control signals; Different values ​​of the voltage control signal correspond to different values ​​of the ideal output voltage, and the voltage control signal is directly proportional or inversely proportional to the ideal output voltage; The output terminal is used to output voltage signals. A sampling unit is connected to the output terminal to sample and obtain a test voltage, the test voltage including a first test voltage and a second test voltage; the first test voltage is the test output voltage corresponding to a first ideal output voltage, and the second test voltage is the test output voltage corresponding to a second ideal output voltage; The arithmetic unit obtains a test ratio coefficient between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage. The calculation unit obtains the proportional deviation parameter based on the test proportionality coefficient and the direct or inverse proportional relationship; A proportional adjustment unit is connected to the output terminal and adjusts the output voltage signal output from the output terminal according to the proportional deviation parameter.

2. The adjustment circuit according to claim 1, wherein, The proportional adjustment unit includes a first resistor and a second resistor connected in series, and a first MOSFET and a second MOSFET connected in parallel with the first resistor and the second resistor, respectively. The adjustment circuit also includes: A control unit is connected to the first MOSFET and the second MOSFET respectively to control the on and off states of the first MOSFET and the second MOSFET respectively. When the first MOSFET is turned off, the first resistor is electrically connected to the output terminal; when the second MOSFET is turned off, the second resistor is electrically connected to the output terminal.

3. The adjustment circuit according to claim 1, wherein, The arithmetic unit obtains the test scaling factor and offset parameter between the test voltage and the voltage control signal based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage. An offset adjustment unit is connected to the output terminal and adjusts the output voltage signal output by the output terminal according to the offset parameter.

4. The adjustment circuit according to claim 3, wherein, The offset adjustment unit includes a first branch, the output terminal, and a second branch connected in sequence. The first branch includes a first regulating resistor and a first PMOS transistor connected in parallel with the first regulating resistor; the second branch includes a second regulating resistor and a first NMOS transistor connected in parallel with the second regulating resistor; The adjustment circuit also includes: The control unit is connected to the first PMOS transistor and the first NMOS transistor respectively, and uses the same signal to control the first PMOS transistor and the first NMOS transistor to make the first PMOS transistor turn on and the first NMOS transistor turn off, or the first PMOS transistor turn off and the first NMOS transistor turn on.

5. The adjustment circuit according to claim 3, wherein, The adjustment circuit also includes: A preamplifier, which is connected to the input terminal to receive the voltage control signal; A proportional adjustment unit, the first end of which is connected to the output terminal of the preamplifier; An offset adjustment unit, wherein the first end of the offset adjustment unit is connected to the second end of the proportional adjustment unit; The post-stage operational amplifier has its first terminal connected to the second terminal of the offset adjustment unit, and its second terminal connected to the output terminal.

6. The adjustment circuit according to claim 5, wherein, The offset adjustment unit includes a first branch and a second branch; the adjustment circuit further includes a voltage divider resistor unit, which includes multiple series resistors. The first end of the first branch is connected to the second end of the proportional adjustment unit, and the second end of the first branch is connected to the first end of the voltage divider resistor unit. The first end of the second branch is connected to the second end of the voltage divider resistor unit, and the second end of the second branch is grounded; The third terminal of the voltage divider resistor unit is connected to the first terminal of the subsequent operational amplifier.

7. The adjustment circuit according to claim 5, wherein, The adjustment circuit also includes: A voltage follower, wherein the first terminal of the voltage follower is connected to the output terminal of the preamplifier, and the second terminal of the voltage follower is connected to the first terminal of the proportional adjustment unit.

8. A chip, characterized in that, include: The adjustment circuit as described in any one of claims 1-7.

9. A method for adjusting settings, characterized in that, include: Obtain the voltage control signal; Different values ​​of the voltage control signal correspond to different values ​​of the ideal output voltage, and the voltage control signal is directly proportional or inversely proportional to the ideal output voltage; The test voltage is obtained by sampling, and the test voltage includes a first test voltage and a second test voltage; the first test voltage is the test output voltage corresponding to a first ideal output voltage, and the second test voltage is the test output voltage corresponding to a second ideal output voltage; Based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, and the voltage control signal corresponding to the second test voltage, a test ratio coefficient between the test voltage and the voltage control signal is obtained. Based on the test proportionality coefficient and the direct or inverse proportional relationship, the proportionality deviation parameter is obtained; The output voltage signal is adjusted according to the proportional deviation parameter.

10. The adjustment method according to claim 9, wherein, The adjustment method also includes: Based on the first test voltage, the voltage control signal corresponding to the first test voltage, the second test voltage, the voltage control signal corresponding to the second test voltage, the first ideal output voltage, and the second ideal output voltage, the test scaling factor and offset parameter between the test voltage and the voltage control signal are obtained; The output voltage signal is adjusted according to the offset parameter.

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