Computer-aided weak pattern detection and authentication system

Abstract

This application relates to a computer-aided weak pattern detection and qualification system. A weak pattern detection and qualification system can include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system can also include at least one processor in communication with the wafer inspection tool. The at least one processor can be configured to perform pattern grouping on the detected defects based on a design of the wafer, identify regions of interest based on the pattern grouping, identify weak patterns contained in the identified regions of interest, the weak patterns being patterns that deviate from the design by more than a threshold amount, validate the identified weak patterns, and report the validated weak patterns or facilitate a correction to the design of the wafer based on the validated weak patterns.

Description

[0001] Related Application Data

[0002] This application is a divisional application of application number 201780024782.4, filed on April 21, 2017, entitled "Computer Aided Weak Pattern Detection and Qualification System", which claims priority to U.S. Provisional Application No. 62 / 326,653, filed on April 22, 2016. The entire disclosure of U.S. Provisional Application No. 62 / 326,653 is incorporated by reference herein.

[0003] Cross Reference To Related Applications

[0004] This application claims the benefit under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 62 / 326,653, filed April 22, 2016. The entire disclosure of U.S. Provisional Application No. 62 / 326,653 is incorporated by reference herein. TECHNICAL FIELD

[0005] The present disclosure relates generally to the field of inspection, and in particular, to wafer inspection. BACKGROUND

[0006] Thin polished plates, such as silicon wafers and the like, are a very important part of modern technology. For example, a wafer can mean a thin slice of semiconductor material used in the manufacture of integrated circuits and other devices. Other examples of thin polished plates can include disk substrates, gauge blocks, and the like. Although the technology described herein primarily refers to wafers, it should be appreciated that the technology is also applicable to other types of polished plates. The term wafer and the term thin polished plate are used interchangeably in the present disclosure.

[0007] Wafers are subjected to defect inspection. Defects can be random or systematic. Systematic defects can occur on specific design patterns and can be referred to as hotspots (i.e., weak patterns, or patterns on the wafer that deviate from the design). One of the purposes of defect inspection is to detect and qualify these hotspots. For example, an inspection process can utilize an inspection tool to scan a wafer and use design based grouping (DBG) to classify detected defects. The defects can be sampled and re-inspected using a scanning electron microscope (SEM) and manually classified to determine the presence of hotspots. Simulations can be utilized to help predict patterns or sites that are prone to failure, which in turn can be used to help users place inspection focus in areas that can contain such patterns and sites.

[0008] It should be noted that while the above inspection process can be helpful, it is also associated with several drawbacks. For example, the inspection process relies on the human eye to determine the presence of defects, which means that the inspection process can only handle small sample sizes and lacks verification. In fact, system defects with critical dimension (CD) variations of about 20% to 30% that are detected can be discarded. Furthermore, because there is no automation and all classification must be done by humans, the sample size is typically limited to no more than about 5,000 defects and is prone to errors due to sampling and fatigue. As the volume of data increases due to increased detection sensitivity, the effectiveness of sampling can be limited unless automated methods are developed. Moreover, simulation helps to predict risk sites but it does not help the user to identify whether the sites are actually failing post-processing.

[0009] It is desirable to provide a method and system for weak pattern detection and qualification without the foregoing drawbacks. SUMMARY

[0010] The present disclosure relates to a system. The system can include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system can also include at least one processor in communication with the wafer inspection tool. The at least one processor can be configured to perform pattern grouping on detected defects based on a design of the wafer, identify regions of interest based on the pattern grouping, identify weak patterns contained in the identified regions of interest, a weak pattern being a pattern that deviates from a design by more than a threshold amount, validate the identified weak patterns, and report the validated weak patterns or facilitate a modification of a design of a wafer based on the validated weak patterns.

[0011] A further embodiment of the present disclosure relates to a system. The system can include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system can also include at least one processor in communication with the wafer inspection tool. The at least one processor can be configured to perform pattern grouping on detected defects based on a design of the wafer, simulate an effect of a wafer processing tool on a wafer, identify regions of interest in which patterns deviate from a design of the wafer, identify weak patterns contained in the identified regions of interest, a weak pattern being a pattern that deviates from a design by more than a threshold amount, validate the identified weak patterns, and report the validated weak patterns or facilitate a modification of a design of a wafer based on the validated weak patterns.

[0012] An additional embodiment of the present disclosure relates to a system. The system can include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system can also include at least one processor in communication with the wafer inspection tool. The at least one processor can be configured to perform pattern grouping on detected defects based on a design of the wafer, obtain a scanning electron microscope (SEM) image of the wafer, align the SEM image of the wafer with a design of the wafer, identify regions of interest based on the alignment of the SEM image of the wafer with the design of the wafer, obtain metrics of the wafer in the identified regions of interest, measure pattern variations in the identified regions of interest based on the obtained metrics, identify weak patterns based on the pattern variations, a weak pattern being a pattern that deviates from the design by more than a threshold amount, validate the identified weak patterns, and report the validated weak patterns or facilitate a revision of the design of the wafer based on the validated weak patterns.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate subject matter of the application. The description and drawings together serve to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0014] Those skilled in the art will readily understand many of the advantages of the present application over the prior art by reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a diagram depicting an inspection system configured in accordance with an embodiment of the present disclosure;

[0016] Figure 2 is a diagram depicting a simulation-based hot spot detection and qualification process configured in accordance with an embodiment of the present disclosure;

[0017] Figure 3 is a diagram depicting a layout-based hot spot detection and qualification process configured in accordance with an embodiment of the present disclosure; and

[0018] Figure 4 is a diagram depicting a plurality of identified regions of interest on a wafer. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0020] Embodiments in accordance with the present application relate to methods and systems for providing weak pattern (or hot spot) detection and qualification. More specifically, a computer-driven hot spot-design detection and verification system is disclosed that implements computer-aided for automatically discovering and qualifying hot spots on a wafer. In some embodiments, a system configured in accordance with the present application can be configured to implement automatic identification of weak points within a hot spot. In some embodiments, a system configured in accordance with the present application can be further configured to employ an algorithmic approach to separate and rank hot spots based on the severity (or marginality) of pattern variations. It is contemplated that methods and systems configured in accordance with the present application can provide significant improvements in both efficiency and accuracy compared to existing hot spot inspection methods and systems.

[0021] Referring now to Figure 1 , a diagram depicting an exemplary inspection system 100 configured in accordance with embodiments of the present application is shown. Inspection system 100 can include an inspection tool 102 (e.g., a broadband plasma inspection tool, a metrology inspection tool, an electron beam inspection tool, with or without output from simulation provided by design rule checking (DRC), optical rule checking (ORC), or the like). Inspection tool 102 can be configured to inspect a wafer (e.g., a patterned wafer) and detect defects present on the wafer. Detected defects can be provided to one or more processors 104 (e.g., special purpose processing units, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or various other types of processors or processing units) that can be configured to perform single-step or multi-step pattern grouping based on a design. In some embodiments, pattern grouping can be performed utilizing a technique commonly referred to as design-based ranking (also referred to as design-based grouping or classification). Design-based ranking can integrate design information and defect inspection results to group detected defects into different groups / ranks based on their pattern types.

[0022] Potential hot spots can be identified after pattern grouping is complete. In some embodiments, a simulation-based identification process 106 can be utilized to simulate a design or wafer process (e.g., photolithography) to search for regions of interest that can contain potential hot spots. Regions of interest can be automatically placed with high accuracy for each pattern type (e.g., according to pattern grouping / ranking) to automatically evaluate local CD and other pattern variations (e.g., line end shortening and corner rounding). Alternatively and / or in addition, a layout-based identification process 108 can be utilized to automatically identify regions of interest for defect sites identified by inspection tool 102. Regardless of which identification process (simulation-based 106 or layout-based 108) is utilized, it should be noted that a filtering process 110 can be engaged to help determine the severity of failures that occur in identified regions of interest and filter out some identified regions based on the severity of failures. Remaining regions can be reported as regions containing potential hot spots, which can then be verified using processes that will be described in detail below.

[0023] Referring now to Figure 2 , more detailed illustrations depicting exemplary embodiments of a simulation-based hot spot detection and qualification process are shown. It should be noted that since the simulation-based hot spot detection and qualification process is an automated process (i.e., the identification process does not rely on human eyes to determine the presence of defects), the defect sample size is no longer limited by human capabilities. In other words, it is contemplated that the defect sample size can be increased (step 106A) as desired to help increase the accuracy of the hot spot detection and qualification process.

[0024] In the case of a selected sample, in a simulation step 106B, one or more simulators (e.g., implemented using one or more processors) can be engaged to execute one or more simulation programs running thereon to simulate the effects of a wafer processing tool, such as photolithography, chemical mechanical planarization, etching, or the like. It is contemplated that the simulation can be able to show how a particular region changes across different focus and offset conditions without having to scan a wafer. The results of the simulation can be processed in an identification step 106C to search for local variations and identify regions where a local pattern can be failing (e.g., deviating from the design). A filtering step 110 can then be utilized to filter out some of the identified regions based on one or more thresholds established for one or more measured metrics (e.g., regions with CD variations below a certain threshold can be filtered out). The filtering step 110 can automatically identify pattern failures based on the thresholds and / or based on exhibiting abnormal values greater than a typical variation amount. It should be noted that the thresholds used in this manner can help determine the severity of the failure and qualify the weak spots based on desired specifications. The remaining regions (i.e., regions where a local pattern can have deviated from the design by an amount greater than the threshold) can then be reported as regions containing potential hot spots that can need to be verified by a verification process.

[0025] The verification process can be performed in a variety of ways. For example, in some embodiments, a pattern search step 112 can be invoked to help define a hot spot attention region (also referred to as an inspection attention region) around the reported potential hot spot. In a verification step 114, an inspection tool capable of sampling and providing a scanning electron microscope (SEM) re-inspection of the defined inspection attention region can then be utilized to help confirm the validity of the hot spot. In some embodiments, if the inspection tool 102 is capable of sampling and providing a SEM re-inspection, then the same inspection tool 102 can be utilized to perform the verification step 114. Otherwise, a second inspection tool can be utilized to perform the verification step 114. The verified hot spot (i.e., a pattern confirmed to be a weak pattern) can then be reported to a user (e.g., a wafer engineer or designer) or provided to facilitate a revision of the design of the wafer (e.g., to reduce or eliminate the weak pattern).

[0026] In some embodiments, in the verification step 114, a pattern fidelity measurement (e.g., measuring CD variation) can be employed to help confirm the validity of the hotspots. The pattern fidelity measurement can indicate variation and / or deviation of the pattern from an expected pattern morphology. In some embodiments, the pattern fidelity measurement can be performed with technology similar to that disclosed in U.S. Patent Application No. 14 / 918,394, entitled "Automated Pattern Fidelity Measurement Plan Generation," which is incorporated by reference herein in its entirety. It should be appreciated that other pattern fidelity measurement technology can also be utilized without departing from the spirit and scope of the present disclosure.

[0027] It should also be appreciated that the verification process described above is merely exemplary and not meant to be limiting. For example, in some embodiments, a pattern fidelity measurement can be performed prior to the pattern search to automatically confirm the hotspots. Then, the pattern search (to help define the inspection focus areas) can be performed, but the search can be limited to only the confirmed hotspots. Then, the wafer with the defined inspection focus areas can be inspected, sampled, and SEM rechecked. If desired, the pattern fidelity measurement can be performed again to measure CD variation in these hotspots.

[0028] As will be apparent from the above, the hotspot detection and qualification process can be automated in a variety of ways to help increase the efficiency and accuracy of the process. It should also be noted that, since the hotspot detection and qualification process can be performed in a variety of ways, different layers can be allowed to use different hotspot detection and qualification processes. For example, one particular hotspot detection and qualification process can be well suited for identifying hotspots in an after-develop inspection (ADI) layer, while a slightly different hotspot detection and qualification process (e.g., where the process steps are performed in a slightly different order) can be better suited for identifying hotspots in a different (e.g., after-etch) layer. It is therefore contemplated that the hotspot detection and qualification process configured in accordance with the present disclosure can be implemented differently for different purposes without departing from the spirit and scope of the present disclosure.

[0029] Reference is now made to Figure 3 , which shows a more detailed illustration depicting an exemplary implementation of a layout-based hotspot detection and qualification process. The layout-based hotspot detection and qualification process configured in this way can use a design layout to automatically identify areas of interest for defect sites identified by the inspection tool 102. More specifically, as shown in Figure 3 , in a SEM imaging step 108A, a wafer can be sampled and a SEM image of the wafer can be collected. In an alignment step 108B, the SEM image can then be aligned with a design and areas of interest can be automatically identified in step 108C (e.g., at line ends, corners, minimum CD areas, or the like, as shown in Figure 4Subsequently, metrics can be performed in step 108D to find potential bias only in the identified regions of interest and pattern variations (e.g., in terms of pinching, protrusions, or the like) can be measured in step 108E in the identified regions of interest.

[0030] Next, filtering step 110 can be utilized to filter out some of the identified regions based on one or more thresholds established for one or more measurement metrics. In some embodiments, pattern fidelity measurements (e.g., to measure CD variations) can be performed on these regions and potential hotspots can be determined based on the severity of the CD variations (e.g., absolute or relative variations). The potential hotspots can then be verified by a verification process similar to that described above. For example, the potential hotspots can be verified by running a pattern search on the entire wafer, inspecting wafer inspection regions of interest on an inspection tool, sampling and re-inspecting SEM defects, and running pattern fidelity measurements again to measure CD variations.

[0031] It should be noted that the hot spot detection and qualification process configured in accordance with the present disclosure uses a process simulation and / or layout based approach to effectively automatically determine hot spots, not as a pre-inspection prediction but as a tool to algorithmically identify and assess failures. It should be noted that the hot spot detection and qualification process configured in accordance with the present disclosure (both simulation based and layout based) is able to find more hot spots than existing approaches by increasing sampling through automated assessment of SEM pre-data. It should also be noted that the hot spot detection and qualification process configured in accordance with the present disclosure can achieve automatic placement of regions of interest for each pattern type (e.g., each tier as determined based on design based tiering) with high accuracy to automatically assess local CD and other pattern variations (e.g., line end shortening and corner rounding).

[0032] It is further noted that the hot spot detection and qualification process configured in accordance with the present disclosure can also eliminate human subjectivity in determining the severity of pattern variations and failures. Moreover, the hot spot detection and qualification process configured in accordance with the present disclosure can achieve a fully automated flow of hot spot discovery, including identification and qualification of failure sites, which in turn can provide time savings as the automated metric and simulation processing volume is increased. Furthermore, it should be noted that the hot spot detection and qualification process configured in accordance with the present disclosure does not require upfront simulation for all pattern types. In other words, the hot spot detection and qualification process configured in accordance with the present disclosure does not rely on predicting hot spots on a pre-design, wafer, or master mask.

[0033] It should be appreciated that the threshold values referenced in the above examples can be user-defined or system-defined. A user can define, for example, an amount of deviation from an expected or nominal value as a threshold value. A system configured in accordance with the present disclosure can also define the threshold value. The system can, for example, define an amount of deviation where a weak pattern is identified if a particular location is outside of a particular value from a typical variation. It should be appreciated that the methods and systems described in the present disclosure can be implemented to support both user-defined threshold values and / or system-defined threshold values without departing from the spirit and scope of the present disclosure.

[0034] It should also be appreciated that although the above examples relate to wafers, systems and methods in accordance with the present disclosure can also be applicable to other types of polishing plates without departing from the spirit and scope of the present disclosure. The term wafer used in the present disclosure can include thin slices of semiconductor material used in the manufacture of integrated circuits and other devices as well as other thin polishing plates such as disk substrates, gauge blocks, and the like.

[0035] It is contemplated that the methods and systems described in the present disclosure can be implemented as standalone products or as components of various wafer measurement, inspection, and / or hot spot finding tools. It should be appreciated that the particular order or hierarchy of steps in the disclosed methods are examples of exemplary methods. Based upon design preferences, it is appreciated that the particular order or hierarchy of steps in the methods can be rearranged while still being within the scope and spirit of the present disclosure. It should also be appreciated that the various blocks depicted in the diagrams are presented separately for illustrative purposes. It is contemplated that although the various blocks depicted in the diagrams can be implemented as separate (and communicatively coupled) devices and / or processing units, they can also be integrated together without departing from the spirit and scope of the present disclosure.

[0036] It is believed that the system and apparatus of the present disclosure and many of its attendant advantages will be understood by the foregoing description, and it will be apparent that various changes can be made in the form, construction, and arrangement of the components without departing from the scope and spirit of the disclosed subject matter or without sacrificing all of its material advantages. The form described is merely exemplary.

Claims

1. A system comprising: at least one processor in communication with a wafer inspection tool, the at least one processor configured to receive detected defects from the wafer inspection tool: perform pattern grouping on the detected defects based on a design of the wafer; automatically identify regions of interest based on the pattern grouping; identify weak patterns contained in identified regions of interest, the weak patterns being patterns that deviate from the design by more than a threshold amount; validate identified weak patterns by: performing a pattern search process to define one or more hotspot inspection areas around one or more of the identified weak patterns; re-inspecting defects within the one or more hotspot inspection areas using at least one of the wafer inspection tool or a second wafer inspection tool; and performing a pattern fidelity measurement on the defects to determine local CD variation of the one or more identified weak patterns; and reporting the validated weak patterns or facilitating a correction to the design of the wafer based on the validated weak patterns.

2. The system of claim 1, wherein the at least one processor is configured to identify the weak patterns by: simulating effects of a wafer processing tool on the wafer; identifying regions of interest in which patterns deviate from the design of the wafer; and identifying the weak patterns contained in the identified regions of interest.

3. The system of claim 2, wherein the at least one processor is configured to: perform a pattern search only on the validated weak patterns to define at least one inspection area of interest around the validated weak patterns; and facilitate sampling and SEM re-inspection of the at least one inspection area of interest.

4. The system of claim 1, wherein the at least one processor is configured to identify the weak patterns by: obtaining SEM images of the wafer; aligning the SEM images of the wafer with the design of the wafer; identifying regions of interest based on the alignment of the SEM images of the wafer with the design of the wafer; obtaining metrology of the wafer in the identified regions of interest; measuring pattern variation in the identified regions of interest based on the obtained metrology; and identifying the weak patterns based on the pattern variation.

5. The system of claim 1, wherein an identified weak pattern having a local critical dimension variation greater than the threshold is confirmed as a valid weak pattern.

6. A system comprising: at least one processor in communication with a wafer inspection tool and configured to receive detected defects from the wafer inspection tool, the at least one processor configured to: perform pattern grouping on the detected defects based on a design of the wafer; perform a simulation to simulate effects of a wafer processing tool on the wafer; analyze output of the simulation to automatically identify regions of interest in which patterns deviate from the design of the wafer; identify weak patterns contained in identified regions of interest, the weak patterns being patterns that deviate from the design by more than a threshold amount; validate identified weak patterns by: ​ performing a pattern search process to define one or more hot spot inspection focus areas surrounding one or more of the identified weak patterns; re-inspecting defects within the one or more hot spot inspection focus areas using at least one of the wafer inspection tools or a second wafer inspection tool; and performing a pattern fidelity measurement on the defects to determine local CD variation of the one or more identified weak patterns; and reporting verified weak patterns or facilitating a modification of the design of the wafer based on the verified weak patterns.

7. The system of claim 6, wherein an identified weak pattern having a local critical dimension variation greater than the threshold value is confirmed as a valid weak pattern.

8. A system comprising: at least one processor in communication with a wafer inspection tool and configured to receive detected defects from the wafer inspection tool, the at least one processor configured to: perform pattern grouping on the detected defects based on a design of the wafer; obtain a scanning electron microscope (SEM) image of the wafer; align the SEM image of the wafer with the design of the wafer; identify regions of interest based on the alignment of the SEM image of the wafer with the design of the wafer; obtain metrics of the wafer in identified regions of interest; measure pattern variation in the identified regions of interest based on the obtained metrics; identify weak patterns based on the pattern variation, the weak patterns being patterns that deviate from the design by an amount greater than a threshold value; verify identified weak patterns by: performing a pattern search process to define one or more hot spot inspection focus areas surrounding one or more of the identified weak patterns; re-inspecting defects within the one or more hot spot inspection focus areas using at least one of the wafer inspection tools or a second wafer inspection tool; and performing a pattern fidelity measurement on the defects to determine local CD variation of the one or more identified weak patterns; and reporting verified weak patterns or facilitating a modification of the design of the wafer based on the verified weak patterns.

9. The system of claim 8, wherein an identified weak pattern having a local critical dimension variation greater than the threshold value is confirmed as a valid weak pattern.

Images