Circuits and methods for biasing transistors and corresponding apparatuses

Abstract

The present disclosure relates to a circuit and a method for biasing a transistor and a corresponding device. A circuit for biasing a transistor (13) is provided. The circuit comprises an output terminal (12) configured to be coupled to a gate terminal (14) of the transistor and a circuit arrangement (11). In a first state, the circuit arrangement (11) is configured to output a control signal at a first voltage level to set the transistor (13) into a first transistor state. In a second state, the circuit arrangement (11) is configured to first output the control signal at a second voltage level different from the first voltage level and subsequently change the control signal over time from the second voltage level to a third voltage level different from the first and second voltage levels.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit and method for biasing a transistor, and to a device comprising such a circuit and a corresponding transistor. BACKGROUND

[0002] In various applications, a transistor is biased at a certain voltage to set an operating point for the transistor. One example of such an application is the use of a transistor as an amplifier for an AC (alternating current) signal. In such an application, the transistor is set to an operating point, for example in the linear region of the transistor, by a DC (direct current) bias voltage. Then, an AC signal is additionally applied to the transistor, and the current through the transistor is modulated according to the AC signal. One example of such an AC signal is an RF (radio frequency) signal used in a communication application.

[0003] In some of these applications, it can be required to switch the transistor between a first transistor state in which the transistor is substantially inactive (either cut-off or biased to have a reduced current), and a second transistor state in which the transistor is biased at its operating point, as mentioned above. One example is time division duplexing (TDD) used in communication standards like 5G, in which during time slots in which the communication device receives signals, the transistor of the amplifier is set to the first transistor state, i.e. the inactive state, so as not to interfere with the received signals. In order to transmit signals in other time slots, the transistor is set to the second transistor state, for example, to amplify the signals to be transmitted.

[0004] In order to amplify the AC signal in a reproducible manner, the current through the transistor, which is set in the second transistor state at the operating point, should be the same each time the transistor is switched to the second state without an applied signal to be amplified. However, due to effects such as charge trapping, or immediately after the transition to the second transistor state, a different (e.g. lower) current can occur, and only after a certain time the actually expected nominal current flows. Other effects such as self-heating can also influence the current. For example, in communication, this can lead to a distortion of the transmitted symbols, resulting in communication errors.

[0005] Such effects can be particularly pronounced for transistors of wide bandgap materials such as gallium nitride based high electron mobility transistors (GaN HE MTs), but can also occur in other transistor types. One conventional solution is to make the transistor as little cut-off as possible in the first state (or in other words, not to make the transistor fully cut-off), which can reduce the trapping effects. However, this can increase the noise. Another solution is to pre-distort the signal to be amplified, which requires additional signal processing. SUMMARY

[0006] There is provided a circuit as defined in claim 1 and a method as defined in claim 13. Dependent claims define further embodiments and devices comprising such a circuit.

[0007] According to one embodiment, there is provided a circuit for biasing a transistor, comprising:

[0008] an output terminal configured to be coupled to a control terminal of the transistor, and

[0009] circuitry configured to selectively:

[0010] - in a first state, output a control signal at the output terminal having a first voltage level to set the transistor to a first transistor state, or

[0011] - in a second state, output the control signal at the output terminal to set the transistor to a second transistor state by first outputting the control signal at a second voltage level different from the first voltage level, and subsequently changing the control signal over time from the second voltage level towards a third voltage level different from the first and second voltage levels,

[0012] wherein the circuit is configured to select a difference between the second voltage level and the third voltage level based on at least one of a duration of the first state prior to the second state or the first voltage level.

[0013] According to another embodiment, there is provided a method for biasing a transistor, comprising, selectively:

[0014] - in a first state, outputting a control signal to a control terminal of the transistor at a first voltage level to set the transistor to a first transistor state, or

[0015] - in a second state, to set the transistor to a second transistor state, first outputting the control signal at a second voltage level different from the first voltage level, and subsequently changing the control signal over time from the second voltage level towards a third voltage level different from the first and second voltage levels,

[0016] The method further comprises selecting a difference between the second voltage level and the third voltage level based on at least one of a duration of the first state prior to the second state or the first voltage level.

[0017] The above summary of the disclosure only provides a brief summary of some embodiments and should not be interpreted as limiting in any way as other embodiments can include features other than those explicitly mentioned above. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a block diagram of a device according to an embodiment.

[0019] Figure 2 is a flow chart illustrating a method according to some embodiments.

[0020] Figure 3 is a circuit diagram of a device according to an embodiment.

[0021] Figure 4 is a diagram illustrating an example signal of an embodiment. Figure 3

[0022] Figure 5 is a diagram illustrating an embodiment of a control scheme.

[0023] Figure 6 is a circuit diagram of a device according to yet another embodiment. DETAILED DESCRIPTION

[0024] Various embodiments will be described in detail below with reference to the attached drawings. These embodiments are given by way of example only and are not to be construed as limiting. For example, although the illustrated embodiments include certain features (components, elements, devices, acts, events, method steps), other embodiments can include fewer or additional features. Where certain elements, components, devices, acts, events, method steps or the like are described, they are to be understood as being among other possible embodiments. Any feature described with respect to one embodiment can be incorporated into another embodiment. Changes and modifications can be made to the described embodiments without departing from the scope thereof.

[0025] Unless otherwise stated, connections and couplings described herein refer to electrical connections or couplings. Such connections or couplings can be modified, e.g. by removing elements or by providing additional intermediate elements, as long as the general purpose of the connection or coupling is not significantly altered, e.g. to provide a certain signal, a certain voltage, a certain control, etc.

[0026] ​In this document, a transistor will generally be described as including a control terminal and two load terminals (a first and a second load terminal). By applying a control signal to the control terminal of the transistor, such as a resistance between the load terminals, an operating point through the transistor and / or a current through the load terminals can be set. As used herein, the term transistor includes various types of transistors, such as a field effect transistor (FET), a bipolar junction transistor (BJT), or an insulated gate bipolar transistor (IGBT). In the case of a field effect transistor, the control terminal corresponds to a gate terminal, and the load terminals correspond to source and drain terminals. In the case of a bipolar junction transistor, the control terminal corresponds to a base terminal, and the load terminals correspond to collector and emitter terminals. In the case of an IGBT, the control terminal corresponds to a gate terminal, and the load terminals correspond to collector and emitter terminals.

[0027] A field effect transistor can include various subtypes, such as a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT), etc. The transistor can be based on various semiconductor materials, such as a group IV material, including silicon, germanium, carbon, and compounds thereof, such as SiGe or SiC, or a group III-V semiconductor, such as gallium arsenide (GaAs) or gallium nitride (GaN). While specific transistor types are used in some embodiments described below, it should be understood that the concepts discussed herein for biasing a transistor are also applicable to other transistor types.

[0028] Turning now to the drawings, Figure 1 is a block diagram illustrating an apparatus according to one embodiment.

[0029] Figure 1 The apparatus of

[0030] The circuit 10 includes an output terminal 12 coupled to a control terminal 14 of the transistor 13. Further, the transistor 13 includes a first load terminal 15 and a second load terminal 16. In operation, one of the load terminals 15, 16 can be coupled to a load, for example. In some applications, the transistor 13 can operate as an amplifier or as part of an amplifier. In this case, the circuit 10 can be used to set an operating point of the transistor 13, and, in addition, a signal to be amplified (not shown in Figure 1 but will be referred to in the following Figure 6 further explained for specific examples) can be applied to the control terminal 14, for example, to modify a current between the load terminals 15, 16.

[0031] The circuit 10 comprises a bias voltage generation circuit arrangement 11 which provides a control signal to an output terminal 12 and thus to a control terminal 14 of the transistor 13. The operation of the bias voltage generation circuit arrangement 11 will be explained with reference to Figure 2 .

[0032] Figure 2 is a flow chart illustrating a method according to some embodiments, which can be implemented using the circuit 10 and the bias voltage generation circuit arrangement 11 of Figure 1 , but also using other devices. However, for ease of illustration, the method of Figure 1 will be explained using the devices of Figure 2 .

[0033] At 20, the method comprises providing, in a first state, a control signal to the transistor at a first voltage level. In the case of Figure 1 , this means that the bias voltage generation circuit arrangement 11 in the first state provides a control signal at the first voltage level to the control terminal 14 of the transistor 13 via the output terminal 12. The control signal at the first voltage level sets the transistor 13 to a first transistor state. The first transistor state can be an inactive state in which the transistor 13 is not used. In this inactive state, the transistor 13 can be turned off (i.e. substantially non-conducting between the load terminals 15, 16), or at least set to a state with high impedance between the control terminals 15, 16, even if not completely turned off. For example, when using a time division duplexing scheme, the transistor 13 is used as an amplifier for a signal to be transmitted in a communication system, the first state can be assumed in the time in which the communication device receives data and thus does not use the transistor 13. By setting the transistor 13 to the first transistor state, interference caused by the transistor 13 in a receive path for receiving a signal can be reduced.

[0034] At 21, the method comprises, in a second state, providing a control signal which is first at a second voltage level and subsequently changes towards a third voltage level, wherein the second and third voltage levels are different from each other and from the first voltage level. With the control signal in the second state, the transistor 13 can be set to a second transistor state, e.g. an active state in which the transistor 13 is used and set to a specific operating point. In the above-mentioned example of a communication application, the second state can correspond to a state in which the transistor 13 is used for amplifying a signal to be transmitted.

[0035] The second voltage level and the transition to the third voltage level are chosen to at least partially compensate for the effects described in the introductory section, such as trapping or self-heating effects. The third voltage level can be a steady state, for example, after the trapping effect becomes negligible following the switch to the second state. The third voltage level can then, for example, ensure a specific operating current between load terminals 15 and 16. When the device switches back to the first state after the second state and then back to the second state, the second voltage level ensures that the same current flows immediately after switching transistor 13 to the second transistor state as it does in the steady state at the third voltage level. In this way, effects such as trapping or self-heating effects can be at least reduced.

[0036] For example, when transistor 13 is an N-type field-effect transistor, the second voltage level can be higher than the third voltage level to compensate for the trapping effect, and both the second and third voltage levels can be higher than the first voltage level. Conversely, in the case of a P-type transistor, the second voltage level can be lower than the third voltage level, and both the second and third voltage levels can be lower than the first voltage level. In both cases, the third voltage level is between the first and second voltage levels. However, in other cases, the second voltage level can be between the first and third voltage levels, for example, in some cases of an n-type transistor, where, without the techniques discussed herein, the drain current will be higher than expected immediately after switching to the second transistor state (rather than the lower state in the example above).

[0037] The transition "towards" the third voltage level means reaching the third voltage level after a specific time. However, depending on the operation, it is possible that transistor 13 must be switched back to the first transistor state before actually reaching the third voltage level.

[0038] To further illustrate, specific implementations and example signals from those specific implementations will now be used to describe general concepts. Figure 1 and Figure 2 The technology described herein. However, this should be understood as an example, and other implementations are possible.

[0039] Figure 3 This is a circuit diagram of a device according to another embodiment. Figure 3 The device includes circuitry for biasing transistor 310, comprising elements 30 to 39. Figure 3 In the example, transistor 310 is an N-type field-effect transistor. In a particular embodiment (e.g., for use in high-speed communication applications), transistor 310 may be a gallium nitride (GaN)-based high electron mobility transistor (HEMT). The drain terminal of transistor 310 is coupled to voltage V via a load 311, which is represented as an impedance. DrainThe current flowing through the load 311 is in the Figure 3 first state marked as I Drain .

[0040] The circuit 30 to 39 is shown as comprising 4 terminals, an enable terminal 33 for receiving an enable signal EN, a clamp voltage terminal 39 for receiving a clamp voltage VCLMP, an output terminal 38 for outputting a control signal (Gate) to the gate terminal of the transistor 310, and a terminal 37 at which the output of the digital-to-analog converter 30 can be tapped via a buffer comprising a differential amplifier 32 and a feedback resistor 31, as shown.

[0041] The circuit furthermore comprises two switches 35, 36 provided in a similar half-bridge configuration. A node between the switches 35, 36 is coupled to the output terminal 38. The switches 35, 36 can be implemented as transistor switches in any conventional way.

[0042] Figure 3 The switch 35 in the example is directly controlled by the enable signal EN, while the switch 36 is controlled by the enable signal EN via an inverter 34, such that always one of the switches 35, 36 is closed and the other one of the switches 35, 36 is open.

[0043] In a first state, corresponding to the first state described above, the enable signal EN controls the switches 35, 36 such that the switch 36 is closed and the switch 35 is open. As a result, the transistor 310 is biased by the voltage VCLMP. The voltage VCLMP sets the transistor P110 in an inactive state, for example, an off state or a state with a high impedance between the source terminal and the drain terminal and thus with a reduced drain current I drain .

[0044] The signal EN can be received from another entity, for example, a controller controlling the operation of a communication system operating in a similar time division duplex operation, or another controller controlling the operation of a system in which the device shown in Figure 3 is used.

[0045] In the second state, the enable signal EN controls the switch 35 to be closed and the switch 36 to be open, such that the output signal of the digital-to-analog converter 30 is provided via the buffer 31, 32 to the output terminal 38 and thus to the gate terminal of the transistor 310. The digital-to-analog converter 30 can be any type of digital-to-analog converter (DAC), for example, a resistive DAC. The digital-to-analog converter 30 is provided with a series of digital values which provide a desired second voltage level, followed by a transition towards a third voltage level towards the transistor 310, as explained with respect to 21 of Figure 2 .

[0046] By using the switches 35, 36, a fast transition between the first and second state is possible. However, in other embodiments using a sufficiently fast digital-to-analog converter 30, the voltage level (VCLMP) in the first state can also be generated by the digital-to-analog converter. In this case, no switching circuitry, such as the switches 35, 36, is needed. Figure 3

[0047] To further illustrate this, Figure 4 an example signal of an embodiment of Figure 3 is shown. These signals are only used as simple implementation examples, and the actual signal waveforms can vary depending on the implementation.

[0048] Although Figure 4 the signals of Figure 3 are example signals of an embodiment of Figure 1 , similar signals can be used in other embodiments, such as an embodiment of Figure 4 . The signals of

[0049] The curve 40 shows an example of the enable signal EN switching between the first state and the second state. In the example of Figure 4 , when the enable signal 40 is high, the switch 35 is closed and the switch 36 is open, and the device is thus in the second state. When the enable signal 40 is low, the switch 36 is closed and the switch 35 is open, and the device is in the first state. For ease of reference, on one line below the time axis in Figure 4 , the states are labeled, i.e., first (leftmost in Figure 4 ), the second state is labeled 2.1, followed by the first state being labeled 1.1, the next second state being labeled 2.2, etc., i.e., the first number gives the state (first or second state), and the second number consecutively labels the respective state (first or second).

[0050] The curve 41 illustrates the signal DAC output by the DAC 30 and the buffers 31, 32, which, for example, can be tapped at the terminal 37 and supplied to the output terminal 38 and thus to the transistor 310 in the second state. In other words, the DAC signal 41 determines the voltage applied to the gate terminal in the second state. In the example of Figure 4 , the DAC signal 41 is between a second voltage level V2 and a third voltage level V3 (corresponding to the second and third voltage levels in the above explanation). The second voltage level V2 is higher than the third voltage level V3 by a difference voltage indicated by the arrow 44. Furthermore, in the example of Figure 4 ​In the example, the second voltage V2 changes toward the third voltage V3 until the third voltage V3 eventually reaches a linear slope indicated by reference numeral 45. Both the difference 44 and the slope indicated by reference numeral 45 can be programmable. Furthermore, although a linear transition from the second voltage V2 to the third voltage V3 is shown, nonlinear waveforms can be used in other embodiments.

[0051] Curve 42 represents the signal Gate, output at output terminal 38 and applied to the gate terminal of transistor 310. Curve 43 represents the drain current I. Drain .

[0052] In curve 42, the voltage VCLMP supplied to terminal 39 represents the reference above. Figure 1 The first voltage V1 in the meaning explained.

[0053] exist Figure 4 In the example, the system is first in the second state (state 2.1), which can be an active state, where the transistor is biased by voltage V3 and drain current flows. Then, by switching the enable signal low according to curve 40, the system is brought to the first state ( Figure 4 In state 1.1), in the first state, a first voltage V1, namely VCLMP, is applied to the transistor. This sets the transistor to an inactive state, the transistor is turned off or set to a state with higher impedance between the source and drain terminals, resulting in a decrease in drain current, as shown in curve 43.

[0054] During the first state (e.g., 1.1), the digital-to-analog converter ramps up to provide an output signal at the second voltage level V2. Since this ramp to the second voltage V2 is performed during the first state, that is, when the voltage generated by the digital-to-analog converter is not applied to the output terminal 38, the ramp can be performed relatively slowly, or in other words, a fast digital-to-analog converter is not required.

[0055] Then, when the enable signal 40 goes high again at the end of the first state 1.1, the voltage applied to the gate of the transistor according to curve 42 rises to the second voltage V2, which is provided by the digital-to-analog converter 30 via buffers 31, 32 and a closed switch 35. By using a switching circuit device including switches 35, 36, the rise time from the first voltage V1 corresponding to VCLMP to the second voltage V2 can be made faster, for example, less than 10 μs, particularly less than 5 μs or less than 1 μs, or less than 100 ns. The value of the second voltage level V2 can be adjusted by adjusting the difference between the second voltage level V2 and the third voltage level V3 (as indicated by arrow 44), as indicated by arrow 47. It should be noted that in some cases V2 can also be lower than V3.

[0056] Then, according to the slope 45, the voltage provided to the gate at the output terminal, i.e. the control signal, changes from the second voltage level V2 to a third voltage level V3 according to the curve 42, as indicated by the arrow 46. The duration of this transition can be above 10 μβ, e.g. above 100 μβ, and can reach the order of milliseconds. The duration can be chosen to compensate for the above-mentioned adverse effects that decay over time, such as the trapping effect or the self-heating effect, in which case the duration can correspond to the time before the transistor reaches a stable temperature.

[0057] Then, after the period indicated by the arrow 46, the voltage provided to the gate terminal of the transistor remains at the third voltage level V3.

[0058] With the difference between the voltage levels V2, V3 and the slope 45, the voltage applied to the gate terminal of the transistor 310 during the second state can be adjusted (as indicated by the arrow 48) so that the drain current in the second state is substantially always at the same level, including the time indicated by the arrow 49 and corresponding to the time indicated by the arrow 46. If only the third voltage V3 were applied, the drain current can behave as indicated for example by the dashed curve of the curve 43.

[0059] As already mentioned previously, it can occur that the third voltage level V3 is not reached in case the device remains in the second state for a relatively short time. Figure 4 An example of this is the second state 2.3 in which the device changes to the first state 1.3 before the third voltage level V3 is reached. Thus, although the second voltage V2 in the state 2.3 here also changes towards the third voltage level V3, it does not reach the third voltage level V3 before the device changes to the first state again.

[0060] In some embodiments, the difference between the second and third voltage levels as determined by the slope 45, indicated by the arrow 44, or the time indicated by the arrow 46, can depend on the duration of the preceding first state. For example, when the transistor 310 is in the first state for a relatively long time, the trapping effect can become more pronounced, and therefore, the difference 44 can increase, and / or the duration indicated by the arrow 46 can increase, corresponding to a smaller slope 45. The corresponding values of the difference 44 (or the values of the second and third voltage levels), the slope 45 or other waveform information can be stored in a look-up table and read out depending on the time of the preceding first state or other parameters, such as the temperature, which can be measured by a timer. Figure 5 An example control is illustrated in Fig. 2. Again, the trapping effect can depend on the first voltage level V1. For example, for Figure 3 and Figure 4As shown in the diagram, a lower V1 may result in more pronounced trapping, and the value of V2, and therefore the difference between V2 and V3, may increase with a lower value of V1 (e.g., a more negative value) and decrease with a higher value of V1. A lower value of V1 also corresponds to a higher difference between V1 and V3, such that the difference between V2 and V3 can also be set to a higher value and a lower value as a result of a higher difference between V2 and V1. In a similar manner, other properties, such as the slope or waveform mentioned above, can also be selected based on V1. The value of the difference between V2 and V3, or the values ​​of other properties mentioned above that depend on duration or V1, can be determined by calibration measurements and, for example, stored in a lookup table.

[0061] Figure 5 Control can be achieved, for example, using a correspondingly programmed digital microcontroller or application-specific integrated circuit (ASIC) or other special-purpose circuitry. Therefore, Figure 5 The different blocks in the circuit do not need to be implemented as separate devices, but can be implemented as control flow in any digital circuit device.

[0062] Figure 5 The control device has a DAC value 50 stored therein. This DAC value 50 can be a base value for the third voltage V3. This base value can be modified, for example, by calculation 51 based on temperature or other considerations, such as current limits for a specific application, the desired slope at the transistor's operating point, etc. In other embodiments, calculation 51 may be omitted.

[0063] The resulting value is added in adder 52 to another value output by bias compensation 55. Figure 4 In the example, this value modifies the third voltage V3 to, for example, reach the second voltage V2 and provide a slope of 45. For this purpose, at 54, the difference between the third voltage level and the second voltage level can be stored. Figure 4 Arrow 44 in the diagram, and at 56, the slope can be stored. Offset compensation 55, based on these values, calculates the values ​​to be added to the output of calculation 51.

[0064] In other embodiments, as also referred to Figure 4 Briefly, for example, based on sensor information obtained from sensing 58, the values ​​stored at 54 and 56 can be modified by controller 57. Sensing 58 may, for example, include a timer to measure the duration of the first state as explained above, and, for example, use a lookup table to modify the values ​​stored at 54 and 56 based on that time. In other embodiments, sensing 58 may capture temperature and also modify the stored values ​​accordingly. Therefore, the change from the second voltage level V2 to the third voltage level V3 is caused by… Figure 5 The equipment is actively controlled.

[0065] At the output of the adder 52, a limiter 53 can limit the value if it exceeds a predetermined threshold, for example to prevent the application of too high a voltage to the gate terminal of the transistor 310. The output of the limiter 53 is then provided as an input to the DAC 30.

[0066] The device as discussed herein can be used as an amplifier, for example a radio frequency amplifier. Figure 6 An example amplifier device is shown in Figure 6 The device of Figure 3 is a modification of the device of and corresponding elements have the same reference numerals and will not be described again.

[0067] In the case of such an amplifier, the first state explained above is the inactive state of the amplifier and the second state discussed above is the active state, in which Figure 2 In the device of the radio frequency input signal RFIN provided at the terminal 62 is amplified. In some embodiments, for example, this can be used in a time division duplex (TDD) communication system. In such an application, the signal RFIN can be a signal to be amplified and then transmitted during a transmission time slot of a TDD scheme. The first state (inactive state) can then be a state in which the communication device receives signals and the transistor 310 is set to the second transistor state for reducing interference from Figure 6 the device of into the receive path of the communication device.

[0068] In the device of Figure 6 In the device of the signal RFIN is provided to the gate terminal of the transistor 310 via the capacitor 61. The capacitor 61 is a simple example of a high pass filter which allows the transmission of the radio frequency input signal RFIN but blocks DC voltages. In addition, in some embodiments, an impedance 60 (for example, an inductor) can be provided between the output terminal 38 and the gate terminal of the transistor 310 which acts as a simple example of a low pass filter, preventing any radio frequency interference signals from being coupled to the gate of the transistor 310. In the second state in which the switch 35 is closed, the transistor 310 is set to a particular operating point and then the radio frequency signal RFIN is amplified, i.e. the radio frequency signal RFIN modifies the drain current I Drain If the load 311 is a resistor, for example, the amplified voltage signal can be tapped at the terminals of the load 311. In other embodiments, the load 311 can represent other radio frequency circuitry which then transmits the amplified radio frequency signal.

[0069] Some further embodiments are defined by the following examples:

[0070] Example 1. A circuit for biasing a transistor, comprising:

[0071] an output terminal configured to be coupled to a control terminal of the transistor,

[0072] a circuitry configured to selectively:

[0073] - in a first state, output a control signal having a first voltage level at the output terminal for setting the transistor to a first transistor state, or

[0074] - in a second state, output the control signal at the output terminal for setting the transistor to a second transistor state by first outputting the control signal at a second voltage level different from the first voltage level and subsequently changing the control signal from the second voltage level over time towards a third voltage level different from the first and second voltage levels, wherein the circuitry is configured to select a difference between the second voltage level and the third voltage level based on at least one of a duration of the first state prior to the second state or the first voltage level.

[0075] Example 2. The circuit of example 1, wherein a duration between outputting the control signal having the second voltage level and outputting the control signal having the third voltage level is at least 10 ps.

[0076] Example 3. The circuit of example 1 or 2, wherein a duration between outputting the control signal having the first voltage level at the end of the first state and outputting the control signal having the second voltage level at the beginning of the second state is less than 10 ps.

[0077] Example 4. The circuit of any one of examples 1 to 3, further comprising: a control circuitry configured to control the change of the control signal from the second voltage towards the third voltage.

[0078] Example 5. The circuit of any one of examples 1 to 4, wherein at least one of: a duration between outputting the control signal having the second voltage level and outputting the control signal having the third voltage level, a slope of the control signal between the second voltage level and the third voltage level, and a waveform of the control signal between the second voltage level and the third voltage level, is configurable.

[0079] Example 6. The circuit of example 5, wherein the circuitry is configured to select at least one of: a duration between outputting the control signal having the second voltage level and outputting the control signal having the third voltage level, a slope of the control signal between the second voltage level and the third voltage level, and a waveform of the control signal between the second voltage level and the third voltage level, based on at least one of a duration of the first state prior to the second state and the first voltage level.

[0080] Example 7. The circuit of any one of Examples 1 to 6, wherein the circuit comprises a stored lookup table and is configured to perform the selection based on the stored lookup table.

[0081] Example 8. The circuit of any one of Examples 1 to 7, wherein the third voltage level is between the first voltage level and the second voltage level.

[0082] Example 9. The circuit of any one of Examples 1 to 8, wherein the second voltage level is higher than the third voltage level.

[0083] Example 10. The circuit of any one of Examples 1 to 9, wherein the circuit comprises:

[0084] a bias voltage generator for generating the control signal in the second state, and

[0085] a switching circuit arrangement configured to couple the output terminal to the first voltage level in the first state and to the bias voltage generator in the second state.

[0086] Example 11. The circuit of Example 10, wherein the bias voltage generator comprises a digital-to-analog converter.

[0087] Example 12. An apparatus comprising:

[0088] the circuit of any one of Examples 1 to 11, and

[0089] a transistor, wherein a control terminal of the transistor is coupled to an output terminal of the circuit.

[0090] Example 13. The apparatus of Example 12, further comprising a radio frequency input terminal coupled to the control terminal of the transistor via a high pass filter.

[0091] Example 14. The apparatus of Example 12 or 13, wherein the apparatus is configured as an amplifier apparatus, wherein in the second state the control signal determines an operating point of the transistor.

[0092] Example 15. The apparatus of Example 14, wherein the second voltage level is selected to at least partially compensate for one of a trapping effect or a self-heating effect in the transistor.

[0093] Example 16. The apparatus of Example 14 or 15, wherein the second transistor state is an inactive state of the amplifier apparatus.

[0094] Example 17. The apparatus of any one of Examples 12 to 16, wherein the transistor is a GaN transistor.

[0095] Example 18. A method for biasing a transistor, comprising, selectively:

[0096] - in the first state, outputting a control signal at a first voltage level to a control terminal of the transistor to set the transistor to a first transistor state, or

[0097] - in the second state, to set the transistor to a second transistor state, first outputting a control signal at a second voltage level different from the first voltage level, and subsequently changing the control signal from the second voltage level to a third voltage level different from the first and second voltage levels over time,

[0098] The method further comprises selecting a difference between the second voltage level and the third voltage level based on at least one of a duration of the first state prior to the second state or the first voltage level.

[0099] Example 19. The method of example 20, wherein a duration between outputting the control signal with the second voltage level and outputting the control signal with the third voltage level is at least 10 ps.

[0100] Example 20. The method of example 18 or 19, wherein a duration between outputting the control signal with the first voltage level at the end of the first state and outputting the control signal with the second voltage level at the beginning of the second state is less than 10 ps.

[0101] Example 21. The method of any of examples 18-20, further comprising actively controlling the change of the control signal from the second voltage towards the third voltage.

[0102] Example 22. The method of any of examples 18-21, wherein at least one of a duration between outputting the control signal with the second voltage level and outputting the control signal with the third voltage level, a slope of the control signal between the second voltage level and the third voltage level, and a waveform of the control signal between the second voltage level and the third voltage level is configurable.

[0103] Example 23. The method of example 22, further comprising selecting at least one of a duration between outputting the control signal with the second voltage level and outputting the control signal with the third voltage level, a slope of the control signal between the second voltage level and the third voltage level, and a waveform of the control signal between the second voltage level and the third voltage level based on at least one of a duration of the first state prior to the second state or the first voltage level.

[0104] Example 24. The method of any of examples 18-23, wherein the third voltage level is between the first voltage level and the second voltage level.

[0105] Example 25. The method of any one of examples 18-24, wherein the second voltage level is higher than the third voltage level.

[0106] While specific embodiments have been illustrated and described herein, it will be appreciated that various alternative and / or equivalent implementations can be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be limited only by the claims and the equivalents thereof.

Claims

1. Circuit (10) for biasing a transistor (13, 310), comprising: an output terminal (12, 38) configured to be coupled to a control terminal (14) of the transistor (13, 310), circuit means (11) configured to selectively: in a first state, output a control signal (42) having a first voltage level (VI) at the output terminal (12, 38) for setting the transistor (13, 310) into a first transistor state, or in a second state, output the control signal (42) at the output terminal (12, 38) by first outputting the control signal (42) at a second voltage level (V2) different from the first voltage level (VI), and subsequently changing the control signal (42) over time from the second voltage level (V2) towards a third voltage level (V3) different from the first voltage level (VI) and the second voltage level (V2) for setting the transistor (13, 310) into a second transistor state, wherein the circuit is configured to select a difference (44) between the second voltage level (V2) and the third voltage level (V3) based on at least one of a duration of the first state before the second state or the first voltage level (VI).

2. Circuit (10) according to claim 1, wherein a duration between outputting the control signal (42) having the second voltage level (V2) and outputting the control signal (42) having the third voltage level (V2) is at least 10 ps.

3. Circuit (10) according to claim 1 or 2, wherein a duration between outputting the control signal (42) having the first voltage level (VI) at the end of the first state and outputting the control signal (42) having the second voltage level (V2) at the beginning of the second state is less than 10 ps. control circuit means (50-58) configured to control the change of the control signal (42) from the second voltage level (V2) towards the third voltage level (V3).

4. The circuit (10) of claim 1 or 2, further comprising:

5. Circuit according to claim 1 or 2, wherein at least one of a duration (46) between outputting the control signal (42) having the second voltage level (V2) and outputting the control signal (42) having the third voltage level (V3), a slope (45) of the control signal (42) between the second voltage level (V2) and the third voltage level (V3), and a waveform of the control signal (42) between the second voltage level (V2) and the third voltage level (V3) is configurable. ​ 6. The circuit (10) of claim 5, wherein the circuit is configured to select at least one of the duration (46) between outputting the control signal (42) with the second voltage level (V2) and outputting the control signal (42) with a third voltage level (V3), the slope (45) of the control signal (42) between the second voltage level (V2) and the third voltage level (V3), and the waveform of the control signal (42) between the second voltage level (V2) and third voltage level based on at least one of the duration of the first state preceding the second state or the first voltage level (V1).

7. The circuit (10) of any one of claims 1, 2 and 5, wherein the third voltage level (V3) is between the first voltage level (V1) and the second voltage level (V2).

8. The circuit (10) of claim 7, wherein the circuit is configured to set the difference (44) between the second voltage level (V2) and the third voltage level based on at least one of the duration of the first state preceding the second state or the first voltage level (V1).

9. The circuit (10) of any one of claims 1, 2, 5 and 8, wherein the circuit arrangement comprises a bias voltage generator for generating the control signal in the second state, and a switching circuit arrangement (35, 36) configured to couple the output terminal (12, 38) to the first voltage level (V1) in the first state and to the bias voltage generator in the second state.

10. The circuit (10) of claim 9, wherein the bias voltage generator comprises a digital-to-analog converter (30).

11. An electronic device comprising: the circuit (10) of any one of claims 1 to 10, and a transistor (13, 310), wherein a control terminal (14) of the transistor (13, 310) is coupled to the output terminal (12, 38) of the circuit (10).

12. The electronic device of claim 11, wherein the device is configured as an amplifier device, wherein the control signal (42) in the second state determines an operating point of the transistor (13, 310).

13. The electronic device of claim 12, wherein the second voltage level (V2) is selected to at least partially compensate for one of a trapping effect or a self-heating effect in the transistor (13, 310).

14. A method for biasing a transistor (13, 310), comprising, selectively: in a first state, outputting a control signal (42) to a control terminal (14) of the transistor (13, 310) at a first voltage level (V1) to set the transistor (13, 310) to a first transistor state, or in a second state, outputting the control signal (42) to the control terminal (14) of the transistor (13, 310) at a second voltage level (V2) to set the transistor (13, 310) to a second transistor state. ​ ​ ​ ​ ​ In the second state, in order to set the transistor (13, 310) into a second transistor state, first the control signal (42) is output at a second voltage level (V2) different from the first voltage level (V1), and subsequently the control signal (42) is changed over time from the second voltage level (V2) to a third voltage level (V3) different from the first voltage level (V1) and the second voltage level (V2), The method further comprises: the difference (44) between the second voltage level (V2) and the third voltage level (V3) is selected based on at least one of the duration of the first state preceding the second state or the first voltage level (V1).

15. The method according to claim 14, wherein: at least one of the following is configurable: the duration (46) between outputting the control signal (42) with the second voltage level (V2) and outputting the control signal (42) with the third voltage level (V3), the slope (45) of the control signal (42) between the second voltage level (V2) and the third voltage level (V3), and the waveform of the control signal (42) between the second voltage level (V2) and the third voltage level (V3).

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