Data transmission circuit and data transmission method

Abstract

The present disclosure provides a data transmission circuit and a data transmission method applied to the data transmission circuit, wherein the data transmission circuit comprises: a data selection module connected to a plurality of storage blocks, and connected to a low-order data port through a first group of data buses, and connected to a high-order data port through a second group of data buses, each group of data buses comprising an odd data line and an even data line; an error correction module, each group of the data buses being provided with the error correction module, the error correction module being provided on the odd data line or the even data line, and the error correction module being used to correct the data written from the low-order data port or the high-order data port. The embodiments of the present disclosure can reduce the number of error correction modules in the data transmission circuit and save the layout area of ​​the data transmission circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a data transmission circuit and a data transmission method applied to the data transmission circuit. Background Art

[0002] In a memory, an error correction circuit (ECC) is usually set on the data line to check and correct the data in transmission. During circuit layout, the error correction circuit occupies a large area, so the conventional data transmission circuit has a large layout area.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide a data transmission circuit capable of saving layout area and a data transmission method applied to the data transmission circuit, so as to at least overcome the problem of large layout area of ​​the data transmission circuit to a certain extent.

[0005] According to a first aspect of the present disclosure, there is provided a data transmission circuit, comprising: a data selection module, connected to a plurality of storage blocks, and connected to a low-order data port via a first group of data buses, and connected to a high-order data port via a second group of data buses, each group of data buses comprising an odd data line and an even data line; an error correction module, each group of the data buses being provided with the error correction module, the error correction module being provided on the odd data line or the even data line, and the error correction module being used for correcting errors of data written from the low-order data port or the high-order data port.

[0006] In an exemplary embodiment of the present disclosure, the error correction module includes a first error correction module arranged on the first group of data buses and a second error correction module arranged on the second group of data buses.

[0007] In an exemplary embodiment of the present disclosure, the error correction modules of different groups of the data buses are arranged on data lines of the same type.

[0008] In an exemplary embodiment of the present disclosure, the data selection module includes a first data selector and a second data selector, the first data selector is connected to a first group of storage blocks, and the low-order data port is connected through the first group of data buses, the second data selector is connected to a second group of storage blocks, and the high-order data port is connected through the second group of data buses, and a transmission bus is arranged between the first data selector and the second data selector.

[0009] In an exemplary embodiment of the present disclosure, the transmission bus includes a first transmission bus and a second transmission bus.

[0010] In an exemplary embodiment of the present disclosure, the first group of storage blocks includes a first storage block and a second storage block, and the second group of storage blocks includes a third storage block and a fourth storage block.

[0011] According to a second aspect of the present disclosure, there is provided a data transmission method, which is applied to a data transmission circuit as described in any one of the above items, comprising: in response to a data write request, writing target data into a target storage block via a first type of data line or a second type of data line in a first group of data buses provided with an error correction module, and a first type of data line or a second type of data line in a second group of data buses provided with an error correction module, wherein the first group of data buses is connected to a low-order data port, and the second group of data buses is connected to a high-order data port, and in the first group of data buses and the second group of data buses, one of the first type of data line and the second type of data line is provided with the error correction module, and the other is not provided with the error correction module.

[0012] In an exemplary embodiment of the present disclosure, the first group of data buses is connected to a first data strobe, the first data strobe is connected to a first group of storage blocks, the second group of data buses is connected to a second data strobe, the second data strobe is connected to a second group of storage blocks, a transmission bus is arranged between the first data strobe and the second data strobe, and the method further includes: when alternatingly writing the first data and the second data, writing the low-order data of the first data and the low-order data of the second data through the first-type data lines in the first group of data buses and the first data strobe, and writing the high-order data of the first data and the high-order data of the second data through the first-type data lines in the second group of data buses and the second data strobe.

[0013] In an exemplary embodiment of the present disclosure, when the first data and the second data are alternately written into the first group of storage blocks, the high-order data of the first data and the high-order data of the second data are written into the first group of storage blocks through the first-type data lines in the second group of data buses, the second data selector, two transmission buses in the transmission bus, and the first data selector; when the first data and the second data are alternately written into the second group of storage blocks, the low-order data of the first data and the low-order data of the second data are written into the second group of storage blocks through the first-type data lines in the first group of data buses, the first data selector, two transmission buses in the transmission bus, and the second data selector.

[0014] In an exemplary embodiment of the present disclosure, the transmission bus includes a first transmission bus and a second transmission bus. When the first data and the second data are written into the first group of storage blocks and the second group of storage blocks respectively, the low-order data of the first data is written into the first group of storage blocks through the first-type data lines and the first data selector in the first group of data buses; the high-order data of the first data is written into the first group of storage blocks through the first-type data lines, the second data selector, the first transmission bus, and the first data selector in the second group of data buses; the low-order data of the second data is written into the second group of storage blocks through the first-type data lines, the first data selector, the second transmission bus, and the second data selector in the first group of data buses; and the high-order data of the second data is written into the second group of storage blocks through the first-type data lines and the second data selector in the second group of data buses.

[0015] In an exemplary embodiment of the present disclosure, the method further includes: in response to a data read request, reading target data from a target storage block through the first group of data buses and the second group of data buses.

[0016] In an exemplary embodiment of the present disclosure, the first group of data buses is connected to a first data strobe, the first data strobe is connected to a first group of storage blocks, the second group of data buses is connected to a second data strobe, the second data strobe is connected to a second group of storage blocks, a transmission bus is provided between the first data strobe and the second data strobe, and the reading of target data from a target storage block through the first group of data buses and the second group of data buses comprises: when the target data is stored in the first group of storage blocks, the low-order data of the target data is read into the first group of storage blocks through the first data strobe and the first type of data lines in the first group of data buses. The low-order data port reads the high-order data of the target data to the high-order data port through the first data selector, the transmission bus, the second data selector, and the first type of data lines in the second group of data buses; when the target data is stored in the second group of storage blocks, the high-order data of the target data is read to the high-order data port through the second data selector and the first type of data lines in the second group of data buses, and the low-order data of the target data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the first type of data lines in the first group of data buses.

[0017] In an exemplary embodiment of the present disclosure, the target data includes first data and second data, the first data and the second data are stored in the same group of storage blocks, and the reading of the target data from the target storage block through the first group of data buses and the second group of data buses includes: when the first data and the second data are both stored in the first group of storage blocks, the low-order data of the first data is read to the low-order data port through the first data strobe and the first-type data line in the first group of data buses, and the high-order data of the first data is read to the high-order data port through the first data strobe, the transmission bus, the second data strobe, and the first-type data line in the second group of data buses; the low-order data of the second data is read to the low-order data port through the first data strobe and the second-type data line in the first group of data buses, and the low-order data of the second data is read to the low-order data port through the first data strobe, the transmission bus, the second data strobe, and the second-type data line in the first group of data buses. The data selector and the second type of data lines in the second group of data buses read the high-order data of the second data to the high-order data port; when the first data and the second data are both stored in the second group of storage blocks, the high-order data of the first data is read to the high-order data port through the second data selector and the first type of data lines in the second group of data buses, and the low-order data of the first data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the first type of data lines in the first group of data buses; the high-order data of the second data is read to the high-order data port through the second data selector and the second type of data lines in the second group of data buses, and the low-order data of the second data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the second type of data lines in the first group of data buses.

[0018] In an exemplary embodiment of the present disclosure, the target data includes first data and second data, the first data and the second data are stored in the first group of storage blocks and the second group of storage blocks respectively, the transmission bus includes a first transmission bus and a second transmission bus, and the reading of the target data from the target storage block through the first group of data buses and the second group of data buses includes: reading low-order data of the first data to the low-order data port through the first data selector and the first type of data lines in the first group of data buses, and reading high-order data of the first data to the high-order data port through the first data selector, the first transmission bus, the second data selector, and the first type of data lines in the second group of data buses; reading high-order data of the second data to the high-order data port through the second data selector and the second type of data lines in the second group of data buses, and reading low-order data of the second data to the low-order data port through the second data selector, the second transmission bus, the first data selector, and the second type of data lines in the first group of data buses.

[0019] In an exemplary embodiment of the present disclosure, the first-category data lines are odd data lines, and the second-category data lines are even data lines; or, the first-category data lines are even data lines, and the second-category data lines are odd data lines.

[0020] The disclosed embodiment can greatly save the layout area of ​​the data transmission circuit by providing only one error correction module on the odd data line or the even data line in the data bus.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0023] Figure 1 is a structural schematic diagram of a data transmission circuit in an exemplary embodiment of the present disclosure;

[0024] Figure 2 In one embodiment of the present disclosure Figure 1 The connection relationship diagram of the data strobe module 1 shown;

[0025] Figure 3is a flow chart of a data transmission method provided by an exemplary embodiment of the present disclosure;

[0026] Figure 4A to Figure 4C In the embodiment of the present disclosure Figure 2 The circuit shown is based on Figure 3 Schematic diagram of data writing by the method shown;

[0027] Figure 5 is a flowchart of a data transmission method in another embodiment of the present disclosure;

[0028] Figure 6A to Figure 6C In the embodiment of the present disclosure Figure 2 The circuit shown is based on Figure 5 Schematic diagram of data reading using the method shown. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0030] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0031] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 Schematic diagram of a data transmission circuit in an exemplary embodiment of the present disclosure.

[0033] refer to Figure 1 , the data transmission circuit 100 may include:

[0034] A data strobe module 1 is connected to a plurality of storage blocks BG, and is connected to a low-order data port 31 via a first set of data buses 21, and is connected to a high-order data port 32 via a second set of data buses 22, each set of data buses including an odd data line and an even data line;

[0035] The error correction module 4 is provided for each data bus. The error correction module 4 is provided on the odd data line or the even data line. The error correction module 4 is used to correct the error of the data written from the low-order data port 31 or the high-order data port 32 .

[0036] In the disclosed embodiment, each storage block needs to communicate data with two groups of data ports, the low-order data port 31 and the high-order data port 32. The low-order data port and the high-order data port transmit high-order data (high N bits) and low-order data (low N bits) of a 2N-bit data respectively. In one embodiment, N is, for example, 4 or 8. When the target data to be transmitted is 8 bits, the low-order data port 31 is used to transmit (write or read) the low 4 bits (bit0 to bit3) of the target data, and the high-order data port 32 is used to transmit the high 4 bits (bit4 to bit7) of the target data. When the target data to be transmitted is 16 bits, the low-order data port 31 is used to transmit (write or read) the low 8 bits (bit0 to bit7) of the target data, and the high-order data port 32 is used to transmit the high 8 bits (bit8 to bit15) of the target data.

[0037] Taking the disclosure as an example that each piece of data is 16 bits, the 16-bit target data can be split into low 8 bits and high 8 bits for transmission, but with the subsequent development of technology, the data may not be split once. That is, although the embodiment of the present disclosure only shows two groups of data buses to respectively connect the high-order data port 32 and the low-order data port 31, in other embodiments of the present disclosure, the data transmission circuit 100 may also include multiple groups of data buses, each group of data buses connecting different data ports. Each group of data buses is provided with an error correction module 4. Each group of data buses includes two or more types of data lines, and only one type of data line on each group of data buses is provided with an error correction module 4, and the other types of data lines are not provided with an error correction module 4.

[0038] exist Figure 1 In the illustrated embodiment, the error correction module 4 includes a first error correction module 41 disposed on the first group of data buses 21 and a second error correction module 42 disposed on the second group of data buses 22. The error correction module (Link ECC) is used to check and correct data.

[0039] In the disclosed embodiment, the error correction modules of different groups of data buses can be set on the same type of data lines. For example, the first error correction module 41 and the second error correction module 42 are both set on the odd data line, or the first error correction module 41 and the second error correction module 42 are both set on the even data line. In other embodiments, the first error correction module 41 can also be set on the odd data line and the second error correction module 42 can be set on the even data line and the second error correction module 42 can be set on the odd data line, or the first error correction module 41 can be set on the even data line and the second error correction module 42 can be set on the odd data line. Those skilled in the art can set it according to the actual situation.

[0040] In the storage circuit, data is sampled by odd clocks and even clocks to obtain the data to be transmitted. The data sampled by the odd clock is called odd data, and the data sampled by the even clock is called even data. Odd data and even data are transmitted alternately to improve the transmission capacity of the data line. At the same time, the parallel odd data lines and even data lines alternate in timing when transmitting odd data and even data, which can avoid the occurrence of crosstalk between data lines. In the related art, since the error correction circuit takes a long time to calculate the check and error correction, it is impossible to process odd data and even data at the same time. Usually, error correction circuits are set on both odd data lines and even data lines to realize the check and error correction of the alternating odd data and even data.

[0041] In the embodiment of the present disclosure, by providing an error correction module only on the odd data line or the even data line that can check and correct both the odd data and the even data when the odd data and the even data are transmitted alternately, that is, only one error correction module is provided, the circuit layout area of ​​the data transmission circuit can be greatly saved, so that the chip using the data transmission circuit has a smaller volume, or more functional circuits can be accommodated in the same volume.

[0042] Figure 2 In one embodiment of the present disclosure Figure 1 The connection relationship diagram of the data strobe module 1 is shown.

[0043] refer to Figure 2 In an exemplary embodiment of the present disclosure, the data strobe module 1 may include a first data strobe 11 and a second data strobe 12, the first data strobe 11 is connected to a first group of storage blocks 61, and is connected to a low-order data port 31 through a first group of data buses 21, the second data strobe 12 is connected to a second group of storage blocks 62, and is connected to a high-order data port 32 through a second group of data buses 22, and a transmission bus 5 is arranged between the first data strobe 11 and the second data strobe 12.

[0044] In an exemplary embodiment of the present disclosure, the transmission bus 5 includes at least a first transmission bus 51 and a second transmission bus 52 to achieve at least two paths of data transmission at the same time. In other embodiments of the present disclosure, more transmission buses can be provided to transmit more data in parallel.

[0045] In an exemplary embodiment of the present disclosure, the first group of storage blocks 61 includes a first storage block BGA (Bank Group A) and a second storage block BGB (Bank Group B), and the second group of storage blocks 62 includes a third storage block BGC (Bank Group C) and a fourth storage block BGD (Bank Group D). Each storage block interacts with the data selector through two data lines, one data line is used to transmit high-bit data, and the other data line is used to transmit low-bit data.

[0046] In other embodiments, the first group of storage blocks 61 and the second group of storage blocks 62 may further include more storage blocks, but the present disclosure is not limited thereto.

[0047] exist Figure 2 In the embodiment shown, a smaller circuit layout can be realized by setting only one error correction module on the odd data line or even data line of a group data bus, thereby realizing reading and writing of four or more storage blocks. The detailed reading and writing process is detailed in the following method embodiment of the present disclosure.

[0048] Figure 3 is a flowchart of a data transmission method provided by an exemplary embodiment of the present disclosure. Figure 3 The data transmission method shown can be applied to Figure 1 or Figure 2 The data transmission circuit shown.

[0049] refer to Figure 3 , the data transmission method 300 may include:

[0050] Step S1, in response to a data write request, write target data into a target storage block through a first-type data line or a second-type data line provided with an error correction module in a first group of data buses, and a first-type data line or a second-type data line provided with an error correction module in a second group of data buses, the first group of data buses being connected to a low-order data port, the second group of data buses being connected to a high-order data port, and in the first group of data buses and the second group of data buses, one of the first-type data line and the second-type data line is provided with an error correction module, and the other is not provided with an error correction module.

[0051] In an exemplary embodiment of the present disclosure, the first type of data lines are odd data lines, and the second type of data lines are even data lines; or, the first type of data lines are even data lines, and the second type of data lines are odd data lines.

[0052] Next, combine Figure 2 Description of the circuit shown Figure 3 Detailed flow of the method shown.

[0053] Figure 4A to Figure 4C In the embodiment of the present disclosure Figure 2 The circuit shown is based on Figure 3 Schematic diagram of data writing using the method shown.

[0054] refer to Figure 4A to Figure 4C In the embodiment of the present disclosure, the first data bus 21 is connected to the first data strobe 11, the first data strobe 11 is connected to the first storage block 61, the second data bus 22 is connected to the second data strobe 12, the second data strobe 12 is connected to the second storage block 62, and a transmission bus 5 is provided between the first data strobe 11 and the second data strobe 12. When the first data and the second data are alternately written in one cycle, the low-order data of the first data and the low-order data of the second data are written through the first-type data line 211 provided with the error correction module 41 in the first data bus 21 and the first data strobe 11, and the high-order data of the first data and the high-order data of the second data are written through the first-type data line in the second data bus 22 and the second data strobe 12.

[0055] For data write operations, data is obtained from the data bus based on the sampling clock. Since the distance from the data bus to the data port remains unchanged, data in different storage blocks can be stably written alternately based on the same sampling clock. In this way, the area of ​​the error correction module can be saved, and only the first type of data line (such as the odd data line, Even DQ Bus) is used for data error correction.

[0056] exist Figure 4A to Figure 4C In the figure, the transmission direction and transmission path of the first data are represented by the first data stream 71, and the transmission direction and transmission path of the second data are represented by the second data stream 72. Figure 4A to Figure 4C The illustrated embodiment is suitable for alternately writing data to two storage blocks (BG) within a transmission period T (the time interval between adjacent data on a data line), and the time interval for writing to the two storage blocks is, for example, T / 2.

[0057] refer to Figure 4A When the first data and the second data are alternately written into the first group of storage blocks 61 within one cycle, the high-order data of the first data and the high-order data of the second data are written into the first group of storage blocks 61 through the first type of data lines in the second group of data buses 22, the second data selector 12, the two transmission buses in the transmission bus 5 (the first transmission bus 51 and the second transmission bus 52), and the first data selector 11.

[0058] refer to Figure 4B When the first data and the second data are alternately written into the second group of storage blocks 62, the low-order data of the first data and the low-order data of the second data are written into the second group of storage blocks 62 through the first type of data lines in the first group of data buses 21, the first data selector 11, the two transmission buses in the transmission bus 5, and the second data selector 12.

[0059] refer to Figure 4C In an exemplary embodiment of the present disclosure, the transmission bus 5 (Cross Bus) includes at least a first transmission bus 51 (Even Cross Bus) and a second transmission bus 52 (Odd Cross Bus), so that when the transmission bus 5 needs to simultaneously bear the transmission of two paths of data, two paths of data in the same direction or in different directions are transmitted simultaneously through different transmission buses to reduce mutual interference between data. In other embodiments of the present disclosure, more transmission buses can be set to transmit more data in parallel.

[0060] When the first data and the second data are written into the first group of storage blocks 61 and the second group of storage blocks 62 respectively, the low-order data of the first data are written into the first group of storage blocks 61 through the first type of data lines in the first group of data buses 21 and the first data selector 11; the high-order data of the first data are written into the first group of storage blocks 61 through the first type of data lines in the second group of data buses 22, the second data selector 12, the first transmission bus 51, and the first data selector 11; the low-order data of the second data are written into the second group of storage blocks 62 through the first type of data lines in the first group of data buses 21, the first data selector 11, the second transmission bus 52, and the second data selector 12; the high-order data of the second data are written into the second group of storage blocks 62 through the first type of data lines in the second group of data buses 22 and the second data selector 12.

[0061] Figure 5 is a flowchart of a data transmission method in yet another embodiment of the present disclosure.

[0062] refer to Figure 5 In another exemplary embodiment of the present disclosure, the data transmission method 300 further includes:

[0063] Step S2 , in response to the data read request, read the target data from the target storage block via the first group of data buses 21 and the second group of data buses 22 .

[0064] For data read (Read) operations, data is obtained from different storage locations, and the data timing of each block is different. Even for the same storage block, the data timing is different as the voltage and temperature change. Therefore, in order to ensure the integrity of the data, in the disclosed embodiment, the data read from different storage blocks are randomly placed on different first-class data lines or second-class data lines, and different transmission buses (Cross Bus) to be transmitted to the data port. In this way, the data validity time of each storage block will be relatively wide. When the same operation is performed on two storage blocks in succession, one storage block can use the first-class data bus (e.g., odd data line, Even Bus), and the other storage block can use the second-class data bus (e.g., even data line, Odd Bus), thereby reducing interference between data and achieving stable and efficient data transmission.

[0065] Figure 6A to Figure 6C In the embodiment of the present disclosure Figure 2 The circuit shown is based on Figure 5 Schematic diagram of data reading using the method shown.

[0066] refer to Figure 6A to Figure 6C In an exemplary embodiment of the present disclosure, a first group of data buses 21 are connected to a first data strobe 11, the first data strobe 11 is connected to a first group of storage blocks 61, a second group of data buses 22 are connected to a second data strobe 12, the second data strobe 12 is connected to a second group of storage blocks 62, and a transmission bus 5 is arranged between the first data strobe 11 and the second data strobe 12.

[0067] refer to Figure 6A to Figure 6C When the target data is stored in the first group of storage blocks 61, the low-order data of the target data is read to the low-order data port 31 through the first data selector 11 and the first type of data line in the first group of data buses 21, and the high-order data of the target data is read to the high-order data port 32 through the first data selector 11, the transmission bus 5, the second data selector 12, and the first type of data line in the second group of data buses 22.

[0068] When the target data is stored in the second group of storage blocks 62, the high-order data of the target data is read to the high-order data port 32 through the second data selector 12 and the first type of data line in the second group of data buses 22, and the low-order data of the target data is read to the low-order data port 31 through the second data selector 12, the transmission bus 5, the first data selector 11, and the first type of data line in the first group of data buses 21.

[0069] exist Figure 6A to Figure 6C In the illustrated embodiment, the target data includes first data and second data, and the first data and the second data are stored in the same group of storage blocks. Figure 6A to Figure 6CThe illustrated embodiment is suitable for alternately reading data from two storage blocks (BG) within a transmission period T (the time interval between adjacent data on a data line), and the interval time between reading the two storage blocks is, for example, T / 2.

[0070] exist Figure 6A to Figure 6C In the figure, the transmission direction and transmission path of the first data are represented by the first data stream 71, and the transmission direction and transmission path of the second data are represented by the second data stream 72.

[0071] refer to Fig. 6A When both the first data and the second data are stored in the first group of storage blocks 61, the low-order data of the first data is read to the low-order data port 31 through the first data selector 11 and the first type of data lines in the first group of data buses 21, and the high-order data of the first data is read to the high-order data port 32 through the first data selector 11, the transmission bus 5, the second data selector 12, and the first type of data lines in the second group of data buses 22; the low-order data of the second data is read to the low-order data port 31 through the first data selector 11 and the second type of data lines in the first group of data buses 21, and the high-order data of the second data is read to the high-order data port 32 through the first data selector 11, the transmission bus 5, the second data selector 12, and the second type of data lines in the second group of data buses 22.

[0072] refer to Figure 6B When both the first data and the second data are stored in the second group of storage blocks 62, the high-order data of the first data are read to the high-order data port 32 through the second data selector 12 and the first type of data lines in the second group of data buses 22, and the low-order data of the first data are read to the low-order data port 31 through the second data selector 12, the transmission bus 5, the first data selector 11, and the first type of data lines in the first group of data buses 21; the high-order data of the second data are read to the high-order data port 32 through the second data selector 12 and the second type of data lines in the second group of data buses 22, and the low-order data of the second data are read to the low-order data port 31 through the second data selector 12, the transmission bus 5, the first data selector 11, and the second type of data lines in the first group of data buses 21.

[0073] refer to Figure 6C In an exemplary embodiment of the present disclosure, the target data includes first data and second data, the first data and the second data are respectively stored in a first group of storage blocks 61 and a second group of storage blocks 62, and the transmission bus 5 includes a first transmission bus 51 and a second transmission bus 52.

[0074] At this time, the low-order data of the first data is read to the low-order data port 31 through the first data selector 11 and the first type of data lines in the first group of data buses 21, and the high-order data of the first data is read to the high-order data port 32 through the first data selector 11, the first transmission bus 51, the second data selector 12, and the first type of data lines in the second group of data buses 22; the high-order data of the second data is read to the high-order data port 32 through the second data selector 12 and the second type of data lines in the second group of data buses 22, and the low-order data of the second data is read to the low-order data port 31 through the second data selector 12, the second transmission bus 52, the first data selector 11, and the second type of data lines in the first group of data buses 21.

[0075] The data transmission method provided by the embodiment of the present disclosure can realize high-speed data transmission while saving the layout area of ​​the data transmission circuit.

[0076] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0077] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A data transmission circuit, characterized in that: include: A data strobe module is connected to the plurality of storage blocks and is connected to the low-order data port via a first set of data buses and is connected to the high-order data port via a second set of data buses, each set of data buses including an odd data line and an even data line; An error correction module, each group of the data buses is provided with the error correction module, the error correction module is only provided on the odd data lines but not on the even data lines, or the error correction module is only provided on the even data lines but not on the odd data lines, and the error correction module is used to correct errors of data written from the low-order data port or the high-order data port; When data is written to two storage blocks continuously, the data corresponding to the two storage blocks are written through the odd data line or the even data line provided with the error correction module; when data is read from two storage blocks continuously, one storage block reads data through the odd data line, and the other storage block reads data through the even data line.

2. The data transmission circuit according to claim 1, characterized in that: The error correction module includes a first error correction module arranged on the first group of data buses and a second error correction module arranged on the second group of data buses.

3. The data transmission circuit according to claim 1 or 2, characterized in that: The error correction modules of different groups of the data buses are arranged on data lines of the same type.

4. The data transmission circuit according to claim 1, characterized in that: The data selection module includes a first data selector and a second data selector, the first data selector is connected to a first group of storage blocks, and is connected to the low-order data port through the first group of data buses, the second data selector is connected to a second group of storage blocks, and is connected to the high-order data port through the second group of data buses, and a transmission bus is set between the first data selector and the second data selector.

5. The data transmission circuit according to claim 4, characterized in that: The transmission bus includes a first transmission bus and a second transmission bus.

6. The data transmission circuit according to claim 4, characterized in that: The first group of storage blocks includes a first storage block and a second storage block, and the second group of storage blocks includes a third storage block and a fourth storage block.

7. A data transmission method, characterized in that: The data transmission circuit according to any one of claims 1 to 6, characterized in that it comprises: In response to a data write request, the target data is written into a target storage block through a first data line or a second data line in a first group of data buses provided with an error correction module, and a first data line or a second data line in a second group of data buses provided with an error correction module, the first group of data buses being connected to a low-order data port, the second group of data buses being connected to a high-order data port, and in the first group of data buses and the second group of data buses, one of the first data line and the second data line is provided with the error correction module, and the other is not provided with the error correction module.

8. The data transmission method according to claim 7, characterized in that: The first group of data buses is connected to a first data strobe, the first data strobe is connected to a first group of storage blocks, the second group of data buses is connected to a second data strobe, the second data strobe is connected to a second group of storage blocks, a transmission bus is provided between the first data strobe and the second data strobe, and the method further comprises: When the first data and the second data are written alternately, the low-order data of the first data and the low-order data of the second data are written through the first type of data lines in the first group of data buses and the first data selector, and the high-order data of the first data and the high-order data of the second data are written through the first type of data lines in the second group of data buses and the second data selector.

9. The data transmission method according to claim 8, characterized in that: When the first data and the second data are alternately written into the first group of storage blocks, high-order data of the first data and high-order data of the second data are written into the first group of storage blocks through the first type of data lines in the second group of data buses, the second data selector, two transmission buses in the transmission buses, and the first data selector; When the first data and the second data are alternately written into the second group of storage blocks, the low-order data of the first data and the low-order data of the second data are written into the second group of storage blocks through the first type of data lines in the first group of data buses, the first data selector, two transmission buses in the transmission bus, and the second data selector.

10. The data transmission method according to claim 8, characterized in that: The transmission bus includes a first transmission bus and a second transmission bus. When the first data and the second data are written into the first group of storage blocks and the second group of storage blocks respectively, Writing the low-order data of the first data into the first group of storage blocks through the first type of data lines in the first group of data buses and the first data selector; Writing high-order data of the first data into the first group of storage blocks through the first type of data lines in the second group of data buses, the second data strobe, the first transmission bus, and the first data strobe; Writing the lower bits of the second data into the second group of storage blocks through the first type of data lines in the first group of data buses, the first data strobe, the second transmission bus, and the second data strobe; The high-order data of the second data are written into the second group of storage blocks through the first type of data lines in the second group of data buses and the second data selector.

11. The data transmission method according to claim 7, characterized in that: Also includes: In response to a data read request, target data is read from a target storage block via the first group of data buses and the second group of data buses.

12. The data transmission method according to claim 11, characterized in that: The first group of data buses is connected to a first data strobe, the first data strobe is connected to a first group of storage blocks, the second group of data buses is connected to a second data strobe, the second data strobe is connected to a second group of storage blocks, a transmission bus is provided between the first data strobe and the second data strobe, and the reading of target data from a target storage block through the first group of data buses and the second group of data buses includes: When the target data is stored in the first group of storage blocks, the low-order data of the target data is read to the low-order data port through the first data strobe and the first-type data line in the first group of data buses, and the high-order data of the target data is read to the high-order data port through the first data strobe, the transmission bus, the second data strobe, and the first-type data line in the second group of data buses; When the target data is stored in the second group of storage blocks, the high-order data of the target data is read to the high-order data port through the second data selector and the first type of data line in the second group of data buses, and the low-order data of the target data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the first type of data line in the first group of data buses.

13. The data transmission method according to claim 12, characterized in that: The target data includes first data and second data, the first data and the second data are stored in the same group of storage blocks, and the reading of the target data from the target storage block through the first group of data buses and the second group of data buses includes: When both the first data and the second data are stored in the first group of storage blocks, the low-order data of the first data is read to the low-order data port through the first data strobe and the first-type data line in the first group of data buses, and the high-order data of the first data is read to the high-order data port through the first data strobe, the transmission bus, the second data strobe, and the first-type data line in the second group of data buses; the low-order data of the second data is read to the low-order data port through the first data strobe and the second-type data line in the first group of data buses, and the high-order data of the second data is read to the high-order data port through the first data strobe, the transmission bus, the second data strobe, and the second-type data line in the second group of data buses; When both the first data and the second data are stored in the second group of storage blocks, the high-order data of the first data is read to the high-order data port through the second data selector and the first type of data lines in the second group of data buses, and the low-order data of the first data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the first type of data lines in the first group of data buses; the high-order data of the second data is read to the high-order data port through the second data selector and the second type of data lines in the second group of data buses, and the low-order data of the second data is read to the low-order data port through the second data selector, the transmission bus, the first data selector, and the second type of data lines in the first group of data buses.

14. The data transmission method according to claim 12, characterized in that: The target data includes first data and second data, the first data and the second data are stored in the first group of storage blocks and the second group of storage blocks respectively, the transmission bus includes a first transmission bus and a second transmission bus, and the reading of the target data from the target storage block through the first group of data buses and the second group of data buses includes: Reading low-order data of the first data to the low-order data port through the first data strobe and the first-type data line in the first group of data buses, and reading high-order data of the first data to the high-order data port through the first data strobe, the first transmission bus, the second data strobe, and the first-type data line in the second group of data buses; The high-order data of the second data is read to the high-order data port through the second data selector and the second type of data lines in the second group of data buses, and the low-order data of the second data is read to the low-order data port through the second data selector, the second transmission bus, the first data selector, and the second type of data lines in the first group of data buses.

15. The data transmission method according to claim 7, characterized in that: The first type of data lines are odd data lines, and the second type of data lines are even data lines; or, the first type of data lines are even data lines, and the second type of data lines are odd data lines.

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