Chip junction temperature estimation method and device of power module, equipment and medium

Abstract

The application provides a chip junction temperature estimation method, device and equipment of a power module and a medium, the method comprises the following steps: acquiring physical parameters, reference point temperature and loss power of each chip in the power module; establishing a simulation model based on the physical parameters; applying the loss power to the simulation power module in the simulation model to obtain simulation junction temperature data; obtaining a thermal impedance matrix based on the simulation junction temperature data, the loss power and the reference point temperature; establishing a thermal network model for estimating the chip junction temperature; comparing the output result of the thermal network model with the actual junction temperature result of the test to correct the thermal impedance matrix; predicting the life of the power module to obtain the aging relationship between the life and the thermal impedance matrix; and estimating the junction temperature of the chip of the power module with different life cycles according to the aging relationship; the reliability and stability of the chip junction temperature estimation are improved, the accuracy of the chip junction temperature estimation is ensured, and the automobile can be safely and reliably driven.

Description

Technical Field

[0001] This application relates to the field of vehicle power module technology, specifically to a method, apparatus, device, and medium for estimating the chip junction temperature of a power module. Background Technology

[0002] In recent years, with the development of new energy vehicles, the size of new energy generator sets has increased, the requirements have become more stringent, and the capacity of power converters has also been improved. Therefore, the safety and reliability requirements of new energy vehicles have become increasingly important. Thus, for new energy vehicles to operate safely and reliably, the reliability of the motor controller is essential. IGBTs (Insulated Gate Bipolar Transistors), also known as power modules, are one of the most important power modules in the entire motor controller and are its core component. Since IGBTs are encapsulated inside the power module, it is difficult to directly measure their junction temperature; therefore, junction temperature estimation is necessary. In electric vehicles, due to the high current requirements, three IGBTs are typically connected in parallel within the power module to increase current density, and each IGBT includes multiple chips. However, factors such as uneven current distribution among multiple chips and thermal coupling between parallel chips make accurate estimation of the IGBT chip junction temperature difficult.

[0003] Chinese patent CN107219016B discloses a method and system for calculating the transient junction temperature of an IGBT module. The method establishes a thermal resistance network model of the IGBT module based on the thermal coupling between chips inside the power module to calculate the junction temperature. However, this method does not consider the impact of IGBT module lifetime decay on the thermal resistance matrix, resulting in insufficient reliability of the junction temperature calculation. Its accuracy will decrease with lifetime decay. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, this application provides a method, apparatus, device and medium for estimating the junction temperature of a power module chip, in order to solve the technical problems of insufficient reliability and reduced accuracy of junction temperature calculation due to the failure to consider the impact of IGBT module life decay on the thermal impedance matrix.

[0005] This application provides a method for estimating the junction temperature of a power module chip. The method includes: acquiring the physical parameters of the power module, a reference point temperature, and the power loss of each chip in the power module; performing virtual simulation of the power module based on the physical parameters to establish a simulation model; applying the power loss to the simulated power module in the simulation model to obtain the simulated junction temperature data of the simulated power module; calculating the thermal impedance of the chip based on the simulated junction temperature data, the power loss, and the reference point temperature to obtain a thermal impedance matrix; establishing a thermal network model for estimating the junction temperature of the chip based on the thermal impedance matrix, wherein the thermal impedance includes self-heating impedance and mutual heat resistance; comparing the output of the thermal network model with the actual junction temperature results of the test; correcting the thermal impedance matrix according to the comparison results; and predicting the lifetime of the power module to obtain the aging relationship between the lifetime and the thermal impedance matrix, so as to estimate the junction temperature of the chips of the power module at different life cycles according to the aging relationship.

[0006] In one embodiment of this application, before obtaining the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module, the chip junction temperature estimation method of the power module includes: establishing a power loss model for calculating the power loss based on switching frequency, voltage data, and current data; collecting the operating condition data of the power module, the operating condition data including switching frequency, voltage data, current data, and the reference point temperature; and inputting the switching frequency, voltage data, and current data in the operating condition data into the power loss model, so as to use the output result of the power loss model as the power loss of each chip.

[0007] In one embodiment of this application, applying the loss power to the simulation power module in the simulation model to obtain the simulation junction temperature data of the simulation power module includes: applying the loss power of a corresponding chip to a simulation chip in the simulation power module to make the simulation chip heat up and radiate heat to other simulation chips, wherein the simulation chips in the simulation power module correspond one-to-one with the chips in the power module; measuring the simulation junction temperature of each simulation chip and configuring a corresponding identifier for the simulation junction temperature, wherein the identifier represents the correspondence between the heating simulation chip and the thermally radiated simulation chip; until all simulation chips have completed heating up, the multiple measured simulation junction temperatures are collected into the simulation junction temperature data.

[0008] In one embodiment of this application, the thermal impedance of the chip is calculated based on the simulated junction temperature data, the power loss, and the reference point temperature to obtain a thermal impedance matrix. A thermal network model for estimating the chip junction temperature is then established based on the thermal impedance matrix. This includes: calculating the temperature difference between the simulated junction temperature and the reference point temperature; matching a first chip and a second chip corresponding to the simulated junction temperature according to the identifier of the simulated junction temperature and the correspondence between simulated chips and individual chips; determining the ratio between the temperature difference and the power loss of the first chip as the thermal impedance of the first chip to the second chip; if the first chip and the second chip are the same, the thermal impedance is the self-thermal impedance; if the first chip and the second chip are different, the thermal impedance is the mutual thermal impedance; after obtaining the self-thermal impedance and mutual thermal impedance of each chip, the self-thermal impedance and mutual thermal impedance of each chip are combined into the thermal impedance matrix, and the thermal network model is established based on the thermal impedance matrix, the reference point temperature, and the power loss.

[0009] In one embodiment of this application, the output of the thermal network model is compared with the actual junction temperature result of the test, and the thermal impedance matrix is ​​corrected according to the comparison result. This includes: testing the power module to obtain the actual junction temperature result, which includes the actual junction temperature of each chip; calculating the difference between the estimated junction temperature and the actual junction temperature of the chip as the junction temperature difference of the chip, obtaining the junction temperature difference of each chip, where the output of the thermal network model includes the estimated junction temperature of each chip; dividing the junction temperature difference of the chip into a first junction temperature difference and a second junction temperature difference according to a preset ratio; calibrating the self-thermal impedance of the chip using the first junction temperature difference, and calibrating the mutual thermal impedance of adjacent chips using the second junction temperature difference, obtaining the calibrated self-thermal impedance of the chip and the calibrated mutual thermal impedance of the adjacent chips, where the adjacent chips are those adjacent to the chip; and correcting the thermal impedance matrix based on the calibrated self-thermal impedance and the calibrated mutual thermal impedance of each chip, obtaining the corrected thermal impedance matrix.

[0010] In one embodiment of this application, the lifetime prediction of the power module to obtain the aging relationship between lifetime and thermal impedance matrix includes: performing an aging experiment on the power module based on a preset number of cycles until the power module fails; upon completion of each life cycle aging experiment, comparing the output result of the thermal network model corresponding to the current life cycle with the actual junction temperature result of the test corresponding to the current life cycle, iteratively correcting the thermal impedance matrix of the previous life cycle based on the comparison result to obtain the thermal impedance matrix of the current life cycle, and predicting the lifetime of the power module to obtain the lifetime of the current life cycle, with each preset number of cycles corresponding to one life cycle, and the thermal impedance matrix of the previous life cycle being the corrected thermal impedance matrix; after the power module fails, performing curve fitting based on the lifetime of each life cycle and the thermal impedance matrix of each life cycle to obtain an aging curve, the aging curve representing the aging relationship between lifetime and thermal impedance matrix.

[0011] In one embodiment of this application, after obtaining the aging relationship between lifetime and thermal impedance matrix, the chip junction temperature estimation method of the power module includes: acquiring the current operating condition data and current lifetime of the target power module, the target power module including multiple target chips; calculating the current power loss of each target chip based on the power loss model and the switching frequency, voltage data and current data in the current operating condition data; matching the current thermal impedance matrix corresponding to the current lifetime according to the aging relationship, and inputting the reference point temperature in the current operating condition data, the thermal impedance matrix and the current power loss into the thermal network model, so that the thermal network model outputs the current estimated junction temperature of each target chip.

[0012] In one embodiment of this application, a chip junction temperature estimation device for a power module is also provided. The chip junction temperature estimation device for a power module includes: an acquisition module, used to acquire physical parameters of the power module, a reference point temperature, and the power loss of each chip in the power module; a simulation module, used to perform virtual simulation of the power module based on the physical parameters, establish a simulation model, apply the power loss to the simulated power module in the simulation model, and obtain simulated junction temperature data of the simulated power module; a thermal network module, used to calculate the thermal impedance of the chip based on the simulated junction temperature data, the power loss, and the reference point temperature to obtain a thermal impedance matrix, and establish a thermal network model for estimating the chip junction temperature based on the thermal impedance matrix, wherein the thermal impedance includes self-heating impedance and mutual heating impedance; and a correction module, used to compare the output result of the thermal network model with the actual junction temperature result of the test, correct the thermal impedance matrix according to the comparison result, and perform lifetime prediction of the power module to obtain the aging relationship between lifetime and thermal impedance matrix, so as to estimate the junction temperature of the chips of the power module at different life cycles according to the aging relationship.

[0013] In one embodiment of this application, an electronic device is also provided, the electronic device comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the chip junction temperature estimation method for the power module as described above.

[0014] In one embodiment of this application, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a computer processor, causes the computer to execute the chip junction temperature estimation method for the power module as described above.

[0015] The beneficial effects of this invention are as follows: This invention provides a method, apparatus, device, and medium for estimating the junction temperature of a power module chip. The method obtains simulated junction temperature data through a simulation model, then calculates the self-thermal impedance and mutual thermal impedance of each chip in the power module to obtain a thermal impedance matrix. This matrix is ​​used to establish a thermal network model for estimating the junction temperature of the chip, and the thermal impedance matrix is ​​calibrated, improving the accuracy of the junction temperature estimation. Furthermore, considering the impact of lifetime decay on the thermal impedance matrix and junction temperature, an aging relationship between lifetime and the thermal impedance matrix is ​​established. This allows for the estimation of the junction temperature of power modules at different lifecycles based on the aging relationship, improving the reliability and stability of the junction temperature estimation and ensuring its accuracy. This, in turn, guarantees the maximum threshold for electric vehicle temperature safety, increases system margin, and enables the vehicle to operate safely and reliably.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0018] Figure 1 This is a schematic diagram illustrating the implementation environment of a chip junction temperature estimation method for a power module, as shown in an exemplary embodiment of this application.

[0019] Figure 2 This is a flowchart illustrating a chip junction temperature estimation method for a power module, as shown in an exemplary embodiment of this application.

[0020] Figure 3 This is a schematic diagram illustrating the heat generation of the simulated chip in a simulated power module, as shown in a specific embodiment of this application.

[0021] Figure 4 This is a flowchart illustrating a specific embodiment of the chip junction temperature estimation and calibration process.

[0022] Figure 5 This is a flowchart illustrating the acquisition of an aging curve, as shown in a specific embodiment of this application;

[0023] Figure 6 This is a block diagram illustrating a chip junction temperature estimation device for a power module, as shown in an exemplary embodiment of this application.

[0024] Figure 7 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application is shown. Detailed Implementation

[0025] The embodiments of this application will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be understood that the preferred embodiments are only for illustrating this application and are not intended to limit the scope of protection of this application.

[0026] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] It should be noted that in this application, terms such as "first" and "second" are merely for distinguishing similar objects, and do not limit the order or sequence of similar objects. The variations of "including" and "having" indicate that the scope covered by the subject of the word is not exclusive, except for the examples shown by the word.

[0028] It is understood that the various numerical designations, step numbers, and other identifiers recorded in this application are for descriptive convenience and are not intended to limit the scope of this application. The size of the identifiers in this application does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0029] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.

[0030] It's important to note that the motor controller is one of the three core components of a new energy vehicle's electrical system, directly powering the entire vehicle and determining the overall driving experience. In the early stages of new energy vehicle development, the scale was small and widespread adoption meant that system reliability issues were generally overlooked. However, with the continuous development of new energy vehicles, system safety and reliability have become paramount. As the core component of the motor controller, accurately estimating IGBT junction temperature and improving threshold voltage are crucial research areas. Current technologies lack consideration for the impact of chip aging on junction temperature. With the degradation of power module lifespan, the deviation between the estimated and actual junction temperature increases, and the lack of thermal impedance matrix correction further exacerbates the estimation errors, leading to even more inaccurate junction temperature estimates and ultimately affecting the power module's lifespan.

[0031] To address the aforementioned problems, embodiments of this application propose a method for estimating the junction temperature of a power module chip, a device for estimating the junction temperature of a power module chip, an electronic device, a computer-readable storage medium, and a computer program product, which will be described in detail below.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating the implementation environment of a chip junction temperature estimation method for a power module, as shown in an exemplary embodiment of this application.

[0033] like Figure 1 As shown, the implementation environment can include server 101 and vehicle 102. Server 101 can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. No restrictions are imposed here. Server 101 obtains the simulated junction temperature of the power module through a simulation model, then calculates the self-thermal impedance and mutual thermal impedance of each chip in the power module to obtain a thermal impedance matrix. This is used to establish a thermal network model for estimating the chip junction temperature. The thermal impedance matrix is ​​calibrated, and the lifespan of the power module is predicted. An aging relationship between the lifespan and the thermal impedance matrix is ​​established to estimate the chip junction temperature of the power module at different lifecycles in vehicle 102.

[0034] For example, server 101 obtains the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module; it performs virtual simulation of the power module based on the physical parameters, establishes a simulation model, applies the power loss to the simulated power module in the simulation model, and obtains the simulated junction temperature data of the simulated power module; based on the simulated junction temperature data, power loss, and reference point temperature, it calculates the thermal impedance of the chip to obtain the thermal impedance matrix, and establishes a thermal network model for estimating the junction temperature of the chip based on the thermal impedance matrix. The thermal impedance includes self-heating impedance and mutual heating impedance; it compares the output results of the thermal network model with the actual junction temperature results of the test, calibrates the thermal impedance matrix according to the comparison results, and performs lifetime prediction on the power module to obtain the aging relationship between lifetime and thermal impedance matrix, so as to estimate the junction temperature of the chips of the power module at different life cycles of vehicle 102 according to the aging relationship. As can be seen, the technical solution of this application takes into account the impact of lifetime decay on the thermal impedance matrix and junction temperature, establishes the aging relationship between lifetime and thermal impedance matrix, and can estimate the chip junction temperature of power modules with different life cycles based on the aging relationship, thereby improving the reliability and stability of chip junction temperature estimation, ensuring the accuracy of chip junction temperature estimation, thereby ensuring the maximum threshold for electric vehicle temperature safety, improving system margin, and enabling the vehicle to drive safely and reliably.

[0035] It should be noted that the chip junction temperature estimation method for the power module provided in this application embodiment is generally executed by the server 101, and the corresponding chip junction temperature estimation device for the power module is generally set in the server 101.

[0036] Please see Figure 2 , Figure 2 This is a flowchart illustrating a chip junction temperature estimation method for a power module, as shown in an exemplary embodiment of this application. This method can be applied to... Figure 1 The implementation environment shown is specifically executed by server 101 within that implementation environment. It should be understood that this method can also be applied to other exemplary implementation environments and specifically executed by devices in other implementation environments. This embodiment does not limit the implementation environment to which this method is applicable.

[0037] like Figure 2 As shown, in an exemplary embodiment, the method for estimating the chip junction temperature of the power module includes at least steps S210 to S240, which are described in detail below:

[0038] Step S210: Obtain the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module.

[0039] In one embodiment of this application, the power module is simulated to operate under simulated conditions, and operating data is collected by sensors, including: switching frequency, voltage data, current data, and reference point temperature. The reference point temperature can be the casing temperature of the power module or the cooling water temperature of the power module; no limitation is imposed here. The power loss of each chip in the power module is calculated based on the switching frequency, voltage data, and current data. Physical parameters are obtained from the IGBT user manual of the power module, including the physical structure and material parameters of the power module, such as: the dimensions of each material layer inside the power module, the thermal conductivity of the material, the specific heat capacity of the material, and the density of the material.

[0040] It should be noted that the power module in this embodiment contains multiple chips, such as the upper and lower bridge arm power modules, but is not limited to these.

[0041] In one embodiment of this application, before step S210, the chip junction temperature estimation method of the power module includes: establishing a power loss model for calculating power loss based on switching frequency, voltage data and current data; collecting operating condition data of the power module, including switching frequency, voltage data and current data and reference point temperature; inputting the switching frequency, voltage data and current data in the operating condition data into the power loss model, so as to use the output result of the power loss model as the power loss of each chip.

[0042] In this embodiment, the power loss generally consists of on-state power loss, turn-on power loss, and turn-off power loss. The on-state power loss is related to the threshold voltage drop and collector current; the turn-on power loss is related to the switching frequency, DC-side voltage, and collector current; and the turn-off power loss is related to the switching frequency, DC-side voltage, and collector current. Therefore, a power loss model for calculating the power loss can be established based on the switching frequency, voltage data, and current data. The voltage data includes the threshold voltage drop and DC-side voltage, and the current data is the collector current. The calculation formula for the power loss model is as follows:

[0043]

[0044] Among them, P I P is the average power loss. I_c P is the average on-state power loss. I_on P is the average turn-on loss power. I_off V is the average turn-off power loss. ceo This is the threshold voltage drop. c For collector current, r ce Let f be the on-resistance, δ(n) be the nth switching cycle, and f be the on-resistance. sw E is the switching frequency. sw_on U represents the turn-on energy consumption of the power module under rated conditions. dc U is the DC side voltage. N I is the DC voltage under test conditions. N K represents the on-state current under test conditions. Rg_on K is an empirical coefficient for the turn-on power consumption of the power module gate resistance R. Tj_I E represents the temperature coefficient of the device itself. sw_off K represents the power module's off-state energy consumption under rated conditions. Rg_off R is an empirical coefficient for the power module gate resistance R on its turn-off energy consumption. ce E sw_on U N I N E sw_off K Rg_on K Rg_off K Tj_I Information can be obtained from the IGBT user manual of the power module.

[0045] The power module is simulated to operate under the same conditions, and the operating condition data of the power module is collected by sensors. The switching frequency, voltage data and current data in the operating condition data are input into the power loss model so that the power loss model outputs the average power loss, and the average power loss is used as the power loss of each chip.

[0046] Step S220: Perform virtual simulation of the power module based on physical parameters, establish a simulation model, apply loss power to the simulated power module in the simulation model, and obtain the simulated junction temperature data of the simulated power module.

[0047] In one embodiment of this application, a virtual simulation of the power module is performed based on finite element analysis (FEA) software and physical parameters to establish an FEA simulation model. This model ensures that the simulated power module in the simulation model corresponds to the actual power module, and the simulated chips in the simulated power module correspond one-to-one with the actual chips in the power module. The simulation junction temperature data includes the heat junction temperature of each simulated chip when it heats up itself, and the heat radiation junction temperature of each simulated chip when it is heated by other simulated chips.

[0048] In one embodiment of this application, applying loss power to a simulated power module in a simulation model to obtain simulated junction temperature data of the simulated power module includes: applying loss power to a simulated chip in the simulated power module to cause the simulated chip to heat up and radiate heat to other simulated chips, wherein there is a one-to-one correspondence between the simulated chips in the simulated power module and the chips in the power module; measuring the simulated junction temperature of each simulated chip and configuring a corresponding identifier for the simulated junction temperature to identify the correspondence between the simulated chip that heats up and the simulated chip that is radiated heat; until all simulated chips have completed heating up, the multiple measured simulated junction temperatures are collected into simulated junction temperature data.

[0049] Taking a power module with 6 chips as an example, the corresponding simulation model will include 6 simulated chips in the simulated power module. Please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram illustrating the heat generation of a simulated chip in a simulated power module, as shown in a specific embodiment of this application. Figure 3 As shown, the simulated power module includes six simulated chips: 1#, 2#, 3#, 4#, 5#, and 6#. Simulated chip 2# is adjacent to both 1# and 3#, and simulated chip 5# is adjacent to both 4# and 6#. The power loss P1 corresponding to the 1# chip in the power module is applied to simulated chip 1# to generate heat. Thermal radiation is then applied to simulated chips 2# through 6#. The simulated junction temperature of each chip is measured, including the heat-generating junction temperature of chip 1# and the thermal radiation junction temperatures of chips 2# through 6#. A corresponding identifier is assigned to each group of simulated junction temperatures; the identifier can be a number or a letter, without restriction. For example, a Ti is assigned to each simulated junction temperature. ji_kThe identifier (i or k = 1, 2, 3, 4, 5, 6) represents the simulated junction temperature of chip i when simulated chip k# heats up alone. Therefore, simulated chip k# represents the simulated chip that heats up, and simulated chip i# represents the simulated chip that is subjected to thermal radiation. Based on the above identifier rules, the heating junction temperature of simulated chip 1 is configured as T. j1_1 The thermal radiation junction temperatures of simulation chips #2-#6 are sequentially labeled as follows: T j2_1 T j3_1 T j4_1 T j5_1 T j6_1 .

[0050] Correspondingly, the corresponding power loss P2 of simulation chip #2 is applied to simulation chip #2 to generate heat. Simulation chips #1 and #3-#6 are subjected to thermal radiation. The simulation junction temperature of each simulation chip is measured and corresponding labels are configured, including: the thermal radiation junction temperature T of simulation chip #1. j1_2 The heat-generating junction temperature T of simulation chip #2 j2_2 And the thermal radiation junction temperature T of simulation chips #3-#6 subjected to thermal radiation j3_2 T j4_2 T j5_2 T j6_2 .

[0051] This process is repeated until all simulated chips have completed heating. The measured simulated junction temperatures are then combined into a single simulated junction temperature dataset, as shown below:

[0052]

[0053] Step S230: Calculate the thermal impedance of the chip based on the simulated junction temperature data, power loss and reference point temperature to obtain the thermal impedance matrix, and establish a thermal network model for estimating the chip junction temperature based on the thermal impedance matrix.

[0054] In one embodiment of this application, thermal impedance includes self-thermal impedance and mutual thermal impedance. Considering that each chip has a thermal radiation effect on other chips, the junction temperature of each chip consists of its heat-generating junction temperature and its thermal radiation junction temperature. Therefore, it is necessary to calculate the self-thermal impedance and mutual thermal impedance of each chip. The self-thermal impedance is the thermal impedance of a chip relative to itself, and the mutual thermal impedance is the thermal impedance of the chip relative to other chips. Due to the correlation between thermal impedance and junction temperature, power loss, and reference point temperature, the self-thermal impedance and mutual thermal impedance of the chips can be calculated based on simulated junction temperature data, power loss, and reference point temperature. A thermal impedance matrix is ​​formed based on the self-thermal impedance and mutual thermal impedance of all chips to establish a thermally coupled thermal network model, and the junction temperature of each chip is estimated.

[0055] In one embodiment of this application, step S230 includes: calculating the temperature difference between the simulated junction temperature and the reference point temperature, and matching the first chip and the second chip corresponding to the simulated junction temperature according to the identifier of the simulated junction temperature and the correspondence between the simulated chip and the chip; determining the ratio between the temperature difference and the power loss of the first chip as the thermal impedance of the first chip to the second chip; if the first chip and the second chip are the same, the thermal impedance is the self-thermal impedance; if the first chip and the second chip are different, the thermal impedance is the mutual thermal impedance; after obtaining the self-thermal impedance and mutual thermal impedance of each chip, the self-thermal impedance and mutual thermal impedance of each chip are combined into a thermal impedance matrix, and a thermal network model is established based on the thermal impedance matrix, the reference point temperature, and the power loss.

[0056] In this embodiment, the formula for calculating thermal resistance is as follows:

[0057]

[0058] Among them, Z ki (k or i = 1, 2, 3, 4, 5, 6) represents the thermal resistance of the first chip to the second chip, T ji_k (k or i = 1, 2, 3, 4, 5, 6) represents the simulated junction temperature (T) of the i-th simulated chip when the k-th simulated chip heats up. ref P is the reference point temperature of the selected reference point. k (k = 1, 2, 3, 4, 5, 6) represents the power loss of chip k#. Correspondingly, chip i# represents the chip corresponding to the simulated chip subjected to thermal radiation, i.e., the second chip, and chip k# represents the chip corresponding to the simulated chip that generates heat, i.e., the first chip. When k = i, Z ki This represents the self-thermal resistance of chip k#. When k≠i, it represents the coupling thermal resistance (i.e., mutual thermal resistance) between chip k# and chip i#. Each chip has one self-thermal resistance and at least one mutual thermal resistance. Correspondingly, P... k This represents the power loss of the first chip, k#.

[0059] Taking 6 chips as an example, T j1_1 T ref Substituting P1 into equation (2) yields Z. 11 (Z 11 (For the self-thermal resistance of chip #1), T j1_2 T ref Substituting P2 into equation (2) yields Z. 21 (Z 21 (The mutual thermal resistance between chip #2 and chip #1), T j1_3 T ref Substituting P3 into equation (2) yields Z. 31 (Z 31 (The mutual thermal resistance between chip #3 and chip #1), T j1_4 Tref Substituting P4 into equation (2) yields Z. 41 (Z 41 (This refers to the mutual thermal resistance between chip #4 and chip #1), T j1_5 T ref Substituting P5 into equation (2) yields Z. 51 (Z 51 (The mutual thermal resistance between chip #5 and chip #1), T j1_6 T ref Substituting P6 into equation (2) yields Z. 61 (Z 61 Let's consider the mutual thermal resistance between chip #6 and chip #1, ..., sequentially obtaining one self-thermal resistance and five mutual thermal resistances for each of the six chips. The self-thermal resistances and mutual thermal resistances of all chips are then combined into a thermal resistance matrix, Z. th as follows:

[0060]

[0061] Among them, Z th Z is the thermal impedance matrix. ki (k or i = 1, 2, 3, 4, 5, 6) represents the thermal resistance of chip k# to chip i#.

[0062] Considering that each chip has a thermal radiation effect on the other five chips, and that all chips are thermally coupled, a thermal network model is established based on the thermal impedance matrix, the reference temperature, and the power loss of each chip. The calculation formula for the thermal network model is as follows:

[0063]

[0064] Among them, T ji (i = 1, 2, 3, 4, 5, 6) represents the junction temperature of each chip, Z ki (k or i = 1, 2, 3, 4, 5, 6) represents the thermal resistance of each chip, P k (k = 1, 2, 3, 4, 5, 6) represents the power loss of each chip, T ref This is the reference point temperature.

[0065] Step S240: Compare the output of the thermal network model with the actual junction temperature results of the test, correct the thermal impedance matrix based on the comparison results, and predict the lifetime of the power module to obtain the aging relationship between lifetime and thermal impedance matrix, so as to estimate the junction temperature of the power module chip at different life cycles based on the aging relationship.

[0066] In one embodiment of this application, after obtaining the thermal impedance matrix, deviations in the thermal impedance matrix may occur during actual junction temperature estimation due to uneven current distribution or differences between individual chips. Therefore, the thermal impedance matrix needs to be corrected. The power module can be tested, and the thermal impedance can be calibrated based on the difference between the actual junction temperature and the output of the thermal network model to obtain a corrected thermal impedance matrix, reducing its deviation. Simultaneously, since the thermal impedance matrix is ​​significantly affected by the power module's lifetime decay, thus influencing the junction temperature, the power module can be aged to obtain its lifetime and thermal impedance matrix at different lifecycle stages. This reveals the aging relationship between lifetime and thermal impedance matrix, allowing for junction temperature estimation of power module chips at different lifecycle stages based on this relationship. This improves the reliability and accuracy of the chip junction temperature estimation.

[0067] In one embodiment of this application, the output of the thermal network model is compared with the actual junction temperature result of the test, and the thermal impedance matrix is ​​corrected according to the comparison result. This includes: testing the power module to obtain the actual junction temperature result, which includes the actual junction temperature of each chip; calculating the difference between the estimated junction temperature and the actual junction temperature of the chip as the junction temperature difference of the chip, and obtaining the junction temperature difference of each chip, wherein the output of the thermal network model includes the estimated junction temperature of each chip; dividing the junction temperature difference of the chip into a first junction temperature difference and a second junction temperature difference of the chip according to a preset ratio; calibrating the self-thermal impedance of the chip using the first junction temperature difference of the chip, and calibrating the mutual thermal impedance of adjacent chips using the second junction temperature difference of the chip, to obtain the calibrated self-thermal impedance of the chip and the calibrated mutual thermal impedance of adjacent chips, wherein adjacent chips are chips adjacent to the chip; and correcting the thermal impedance matrix based on the calibrated self-thermal impedance and the calibrated mutual thermal impedance of each chip to obtain the corrected thermal impedance matrix.

[0068] In this embodiment, the reference point temperature, the corrected thermal impedance matrix, and the power loss of each chip are input into the thermal network model so that the thermal network model can estimate the chip junction temperature using equation (4) and output the estimated junction temperature of each chip; a black-box test is performed on the power module to obtain the actual junction temperature of each chip. The difference between the actual junction temperature of a chip and the estimated junction temperature of the chip is calculated to obtain the junction temperature difference ΔT. ji Through the junction temperature difference ΔT ji The self-thermal resistance of the chip and the mutual thermal resistance of adjacent adjacent chips are calibrated and compensated (calibrated).

[0069] Taking chip #2 as an example, the calibration compensation formula is as follows:

[0070]

[0071] Where δ is the self-heating coefficient ratio, ΔTj2 Z represents the junction temperature difference of chip #2, η is the self-thermal resistance coefficient, and Z is the junction temperature difference of chip #2. 22 P2 is the self-thermal resistance of chip #2, P2 is the power loss of chip #2, α and β are the coupling thermal resistance coefficients (mutual thermal resistance coefficients) of adjacent chips, and Z is the self-thermal resistance of chip #2. 12 Z represents the mutual thermal resistance between chip #1 and chip #2, P1 represents the power loss of chip #1, and Z represents the thermal resistance between chip #1 and chip #2. 32 P3 represents the mutual thermal resistance between chip #3 and chip #2, and P3 represents the power loss of chip #3.

[0072] The calibration compensation method specifically involves pre-determining the self-heating coefficient ratio δ as a preset ratio. For example, the self-heating coefficient ratio δ could be 70% or other values. Based on this preset ratio, the junction temperature difference ΔT of chip #2 is adjusted. j2 Assigned as δΔT j2 (first junction temperature difference) and (1-δ)ΔT j2 (Second junction temperature difference), according to δΔT ji2 Adjust the self-heating resistance coefficient η to make ηZ 22 P2 reaches δΔT ji2 And according to (1-δ)ΔT j2 Adjust the coupling thermal resistance coefficients α and β to make αZ 12 P1 and βZ 32 The sum of P3 reaches (1-δ)ΔT j2 That is, adjust η, α and β to satisfy equation (5).

[0073] By analogy, the thermal impedance of other chips is calibrated and compensated until the estimated junction temperature is the same as the actual junction temperature. The self-thermal impedance and mutual thermal impedance of each chip are obtained after calibration, so as to correct the thermal impedance matrix and obtain the corrected thermal impedance matrix.

[0074] In one embodiment of this application, the lifetime prediction of a power module is performed to obtain the aging relationship between lifetime and thermal impedance matrix. This includes: conducting an aging experiment on the power module based on a preset number of cycles until the power module fails; upon completion of each life cycle aging experiment, comparing the output result of the thermal network model corresponding to the current life cycle with the actual junction temperature result of the test corresponding to the current life cycle, iteratively correcting the thermal impedance matrix of the previous life cycle based on the comparison result to obtain the thermal impedance matrix of the current life cycle, and predicting the lifetime of the power module to obtain the lifetime of the current life cycle. Each preset number of cycles corresponds to one life cycle, and the thermal impedance matrix of the previous life cycle is the corrected thermal impedance matrix; after the power module fails, curve fitting is performed based on the lifetime of each life cycle and the thermal impedance matrix of each life cycle to obtain an aging curve, which characterizes the aging relationship between lifetime and thermal impedance matrix.

[0075] In this embodiment, accelerated aging tests are performed on the power module. After n cycles, the power module transitions from the previous lifecycle to the current lifecycle. The corrected thermal impedance matrix is ​​used as the thermal impedance matrix of the previous lifecycle. The thermal impedance matrix of the previous lifecycle, the reference point temperature of the current lifecycle, and the power loss of each chip are input into the thermal network model to obtain the estimated junction temperature of each chip in the current lifecycle. A black-box experiment is then performed on the power module to measure the actual junction temperature of each chip in the current lifecycle, thus obtaining the junction temperature difference of each chip in the current lifecycle. The self-thermal impedance and mutual thermal impedance of each chip are calibrated and compensated using the junction temperature difference of each chip in the current lifecycle to iteratively correct the thermal impedance matrix of the previous lifecycle, obtaining the thermal impedance matrix of the current lifecycle. Furthermore, the lifecycle of the power module is predicted. As the lifecycle of the current lifecycle, the iteratively corrected thermal impedance matrix of the current lifecycle, the reference point temperature of the current lifecycle, and the power loss of each chip are input into the thermal network model to obtain the optimized estimated junction temperature of each chip in the current lifecycle. The highest optimized estimated junction temperature is used as the junction temperature of the entire power module for lifecycle prediction. The value of n can be modified according to the actual operating conditions, where n is the preset number of cycles. The initial preset number of cycles can be 5000 or other values. Then, n cycles of aging tests are performed to obtain the thermal impedance matrix and lifespan for the next life cycle, until the power module meets the failure condition, i.e., the power module fails, thus obtaining the thermal impedance matrix for the entire life cycle.

[0076] After the power module fails, curve fitting is performed based on the lifetime of each life cycle and the thermal impedance matrix of each life cycle to obtain the aging curve, thereby accurately estimating the junction temperature of each chip in the power module at different life cycles.

[0077] In one embodiment of this application, after obtaining the aging relationship between lifetime and thermal impedance matrix, the chip junction temperature estimation method for the power module includes: acquiring the current operating condition data and current lifetime of the target power module, the target power module including multiple target chips; calculating the current power loss of each target chip based on the power loss model and the switching frequency, voltage data and current data in the current operating condition data; matching the current thermal impedance matrix corresponding to the current lifetime according to the aging relationship, and inputting the reference point temperature, thermal impedance matrix and current power loss in the current operating condition data into the thermal network model so that the thermal network model outputs the current estimated junction temperature of each target chip.

[0078] In this embodiment, the current operating condition data and current lifespan of the target power module in the vehicle terminal 102 are acquired. The target power module is of the same model as the power module. The current power loss of each target chip in the target power module is calculated through a power loss model. Based on the aging relationship between lifespan and thermal impedance matrix, the current thermal impedance matrix corresponding to the current lifespan is matched, so that the junction temperature of each target chip can be estimated through a thermal network model. This enables the estimation of chip junction temperature for power modules with different lifespans or at different life cycles, ensuring the accuracy of the chip junction temperature estimation.

[0079] Please see Figure 4 , Figure 4 This is a flowchart illustrating a specific embodiment of the chip junction temperature estimation and calibration process. (See attached diagram.) Figure 4 As shown, the chip junction temperature estimation and calibration process is as follows:

[0080] 1. Establish a power loss model based on switching frequency, voltage data, and current data.

[0081] 2. Determine the input operating conditions, i.e., the switching frequency f in the operating condition data. sw Collector current I c Threshold voltage drop V ceo and DC side voltage U dc and reference point temperature T ref .

[0082] 3. Calculate the power loss of a single chip using a power loss model, i.e., the power loss of each chip.

[0083] 4. Establish an FEA simulation model based on the physical parameters of the power module. Apply the corresponding power loss to each simulation chip to generate heat, and record the simulated junction temperature of each chip to obtain the simulated junction temperature data. Based on the simulated junction temperature data, obtain the thermal impedance matrix Z. th A thermal network model was established based on the actual parallel connection of IGBT chips.

[0084] 5. Based on the obtained thermal impedance matrix Z th and the power loss P of each chip k and reference point temperature T ref The estimated junction temperature of each chip is obtained through a thermal network model.

[0085] 6. Calculate the difference between the actual junction temperature of each chip obtained from the actual black-box junction temperature test and the estimated junction temperature to obtain ΔT. jiThe junction temperature is divided into two parts according to a preset ratio (i.e., the self-heating coefficient ratio δ) using equation (5). Following the rule of first adjusting the self-heating impedance and then adjusting the adjacent coupling thermal impedance, the estimated junction temperature is made the same as the actual junction temperature. After final calibration, the highest estimated junction temperature among the chips is used as the junction temperature of the entire power module in actual application to predict the lifespan of the power module.

[0086] Please see Figure 5 , Figure 5 This is a flowchart illustrating the acquisition of an aging curve, as shown in a specific embodiment of this application. Figure 5 As shown, since the lifespan of the power module has a significant impact on the thermal impedance, the thermal impedance matrix needs to be calibrated (corrected) according to different lifespans. Accelerated aging tests are conducted on the power module to verify the accuracy of the thermal impedance matrix. The thermal impedance matrix is ​​iteratively corrected continuously according to a certain number of aging tests (preset number of cycles), and the lifespan of the power module is predicted (lifespan calculation) until the failure condition is reached, at which point the aging test is stopped, and finally the aging curve of the thermal impedance matrix with the lifespan is output.

[0087] Figure 4 and Figure 5 For detailed information on the process, please refer to the descriptions in the aforementioned embodiments; they will not be repeated here.

[0088] Please see Figure 6 , Figure 6 This is a block diagram illustrating a chip junction temperature estimation device for a power module, as shown in an exemplary embodiment of this application. The device can be applied to... Figure 1 The implementation environment shown is specifically configured in server 101. This device can also be applied to other exemplary implementation environments and specifically configured in other devices. This embodiment does not limit the implementation environment to which this device is applicable.

[0089] like Figure 6 As shown, the exemplary power module's chip junction temperature estimation device includes:

[0090] The acquisition module 610 is configured to acquire the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module; the simulation module 620 is configured to perform virtual simulation of the power module based on the physical parameters, establish a simulation model, apply the power loss to the simulated power module in the simulation model, and obtain the simulated junction temperature data of the simulated power module; the thermal network module 630 is configured to calculate the thermal impedance of the chip based on the simulated junction temperature data, power loss, and reference point temperature to obtain the thermal impedance matrix, and establish a thermal network model for estimating the chip junction temperature based on the thermal impedance matrix, wherein the thermal impedance includes self-heating impedance and mutual heating impedance; the correction module 640 is configured to compare the output results of the thermal network model with the actual junction temperature results of the test, correct the thermal impedance matrix according to the comparison results, and perform lifetime prediction of the power module to obtain the aging relationship between lifetime and thermal impedance matrix, so as to estimate the junction temperature of the chips of the power module at different life cycles according to the aging relationship.

[0091] It should be noted that the chip junction temperature estimation device for the power module provided in the above embodiments and the chip junction temperature estimation method for the power module provided in the above embodiments belong to the same concept. The specific ways in which each module and unit performs its operation have been described in detail in the method embodiments, and will not be repeated here. In practical applications, the chip junction temperature estimation device for the power module provided in the above embodiments can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above, and this is not a limitation here.

[0092] Embodiments of this application also provide an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the chip junction temperature estimation method for the power module provided in the above embodiments.

[0093] Please see Figure 7 , Figure 7 A schematic diagram of a computer system suitable for implementing the embodiments of this application is shown. It should be noted that... Figure 7 The computer system 700 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0094] like Figure 7As shown, the computer system 700 includes a Central Processing Unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 702 or programs loaded from storage portion 708 into Random Access Memory (RAM) 703, such as performing the methods described in the above embodiments. The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An Input / Output (I / O) interface 705 is also connected to the bus 704.

[0095] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0096] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by central processing unit (CPU) 701, it performs various functions defined in the system of this application.

[0097] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0099] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0100] Another aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a computer's processor, causes the computer to perform the chip junction temperature estimation method for the power module as described above. This computer-readable storage medium may be included in the electronic device described in the above embodiments, or it may exist independently and not assembled into the electronic device.

[0101] Another aspect of this application provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the chip junction temperature estimation method for the power module provided in the various embodiments above.

[0102] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for estimating the junction temperature of a power module chip, characterized in that, The method for estimating the chip junction temperature of the power module includes: Obtain the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module; Based on the physical parameters, a virtual simulation of the power module is performed to establish a simulation model. The loss power is then applied to the simulated power module in the simulation model to obtain the simulated junction temperature data of the simulated power module. The thermal impedance of the chip is calculated based on the simulated junction temperature data, the power loss and the reference point temperature to obtain a thermal impedance matrix, and a thermal network model for estimating the chip junction temperature is established based on the thermal impedance matrix. The thermal impedance includes self-heating impedance and mutual heating impedance. The output of the thermal network model is compared with the actual junction temperature results from the test. Based on the comparison results, the thermal impedance matrix is ​​corrected, and the lifespan of the power module is predicted to obtain the aging relationship between the lifespan and the thermal impedance matrix. This aging relationship is then used to estimate the junction temperature of the power module chips at different lifespans. Specifically, comparing the output of the thermal network model with the actual junction temperature results from the test and correcting the thermal impedance matrix based on the comparison results includes testing the power module to obtain the actual junction temperature results, which include the actual junction temperature of each chip. The difference between the estimated junction temperature and the actual junction temperature of the chip is calculated as the estimated junction temperature. The junction temperature difference of the chips is calculated to obtain the junction temperature difference of each chip. The output of the thermal network model includes the estimated junction temperature of each chip. The junction temperature difference of the chips is divided into a first junction temperature difference and a second junction temperature difference according to a preset ratio. The self-thermal resistance of the chip is calibrated using the first junction temperature difference, and the mutual thermal resistance of adjacent chips is calibrated using the second junction temperature difference, resulting in the calibrated self-thermal resistance of the chip and the calibrated mutual thermal resistance of the adjacent chips. The adjacent chips are those adjacent to the first chip. The thermal resistance matrix is ​​corrected based on the calibrated self-thermal resistance and the calibrated mutual thermal resistance of each chip to obtain the corrected thermal resistance matrix.

2. The method for estimating the chip junction temperature of a power module according to claim 1, characterized in that, Before obtaining the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module, the chip junction temperature estimation method of the power module includes: A power loss model for calculating power loss is established based on switching frequency, voltage data, and current data. The operating condition data of the power module is collected, including switching frequency, voltage data, current data, and the reference point temperature; The switching frequency, voltage data, and current data from the operating condition data are input into the power loss model, and the output of the power loss model is used as the power loss of each chip.

3. The method for estimating the chip junction temperature of a power module according to claim 2, characterized in that, The loss power is applied to the simulated power module in the simulation model to obtain the simulated junction temperature data of the simulated power module, including: The power loss of a corresponding chip is applied to a simulation chip in the simulation power module so that the simulation chip heats up and radiates heat to other simulation chips. The simulation chips in the simulation power module correspond one-to-one with the chips in the power module. The simulated junction temperature of each simulated chip is measured, and a corresponding label is configured for the simulated junction temperature. The label represents the correspondence between the simulated chip that generates heat and the simulated chip that is subjected to thermal radiation. Until all the simulated chips have finished heating up, the multiple simulated junction temperatures measured are collected into the simulated junction temperature data.

4. The method for estimating the chip junction temperature of a power module according to claim 3, characterized in that, Based on the simulated junction temperature data, the power loss, and the reference point temperature, the thermal impedance of the chip is calculated to obtain a thermal impedance matrix. A thermal network model for estimating the chip junction temperature is then established based on the thermal impedance matrix, including: Calculate the temperature difference between the simulated junction temperature and the reference point temperature, and match the first chip and the second chip corresponding to the simulated junction temperature according to the identifier of the simulated junction temperature and the correspondence between the simulated chip and the chip. The ratio between the temperature difference and the power loss of the first chip is determined as the thermal resistance of the first chip to the second chip. If the first chip and the second chip are the same, the thermal resistance is the self-heating resistance. If the first chip and the second chip are different, the thermal resistance is the mutual heating resistance. After obtaining the self-thermal impedance and mutual thermal impedance of each chip, the self-thermal impedance and mutual thermal impedance of each chip are combined into the thermal impedance matrix, and the thermal network model is established based on the thermal impedance matrix, the reference point temperature and the power loss.

5. The method for estimating the chip junction temperature of a power module according to claim 1, characterized in that, The power module's lifetime is predicted to obtain the aging relationship between lifetime and thermal impedance matrix, including: The power module is subjected to an aging test based on a preset number of cycles until the power module fails. When an aging experiment for each life cycle is completed, the output result of the thermal network model corresponding to the current life cycle is compared with the actual junction temperature result of the test corresponding to the current life cycle. The thermal impedance matrix of the previous life cycle is iteratively corrected based on the comparison result to obtain the thermal impedance matrix of the current life cycle. The life cycle of the power module is then predicted to obtain the life cycle of the current life cycle. Each preset number of cycles corresponds to one life cycle, and the thermal impedance matrix of the previous life cycle is the corrected thermal impedance matrix. After the power module fails, an aging curve is obtained by curve fitting based on the lifetime of each life cycle and the thermal impedance matrix of each life cycle. The aging curve characterizes the aging relationship between the lifetime and the thermal impedance matrix.

6. The method for estimating the chip junction temperature of a power module according to any one of claims 2-4, characterized in that, After obtaining the aging relationship between lifetime and thermal impedance matrix, the method for estimating the chip junction temperature of the power module includes: Acquire the current operating condition data and current lifespan of the target power module, which includes multiple target chips; Based on the power loss model and the switching frequency, voltage data and current data in the current operating condition data, calculate the current power loss of each target chip. Based on the aging relationship, the current thermal impedance matrix corresponding to the current lifetime is matched, and the reference point temperature in the current operating data, the thermal impedance matrix, and the current power loss are input into the thermal network model so that the thermal network model outputs the current estimated junction temperature of each target chip.

7. A chip junction temperature estimation device for a power module, characterized in that, The chip junction temperature estimation device for the power module includes: The acquisition module is used to acquire the physical parameters of the power module, the reference point temperature, and the power loss of each chip in the power module. The simulation module is used to perform virtual simulation of the power module based on the physical parameters, establish a simulation model, apply the loss power to the simulated power module in the simulation model, and obtain the simulated junction temperature data of the simulated power module. A thermal network module is used to calculate the thermal impedance of the chip based on the simulated junction temperature data, the power loss and the reference point temperature to obtain a thermal impedance matrix, and to establish a thermal network model for estimating the chip junction temperature based on the thermal impedance matrix. The thermal impedance includes self-heating impedance and mutual heating impedance. The correction module is used to compare the output of the thermal network model with the actual junction temperature results from the test, correct the thermal impedance matrix based on the comparison results, and predict the lifetime of the power module to obtain the aging relationship between the lifetime and the thermal impedance matrix. This aging relationship is then used to estimate the junction temperature of the power module chips at different lifecycles. Specifically, comparing the output of the thermal network model with the actual junction temperature results from the test and correcting the thermal impedance matrix based on the comparison results includes testing the power module to obtain the actual junction temperature results, which include the actual junction temperature of each chip; and calculating the difference between the estimated junction temperature and the actual junction temperature of the chip. The junction temperature difference of each chip is obtained as the junction temperature difference of the chip. The output of the thermal network model includes the estimated junction temperature of each chip. The junction temperature difference of the chip is divided into a first junction temperature difference and a second junction temperature difference according to a preset ratio. The self-thermal resistance of the chip is calibrated by the first junction temperature difference, and the mutual thermal resistance of adjacent chips is calibrated by the second junction temperature difference, so as to obtain the calibrated self-thermal resistance of the chip and the calibrated mutual thermal resistance of the adjacent chip. The adjacent chip is the chip adjacent to the chip. The thermal resistance matrix is ​​corrected based on the calibrated self-thermal resistance and the calibrated mutual thermal resistance of each chip to obtain the corrected thermal resistance matrix.

8. An electronic device, characterized in that, The electronic device includes: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the electronic device to implement the chip junction temperature estimation method for the power module as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the chip junction temperature estimation method for the power module as described in any one of claims 1-6.

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