A planar gallium nitride power device with single event effect resistance

Abstract

The present invention discloses a planar gallium nitride power device with single-event effect resistance. The planar gallium nitride power device comprises, from bottom to top, a substrate, a first semiconductor layer, and a second semiconductor layer. A source and a drain are provided at either end of the second semiconductor layer, respectively. A third semiconductor cap layer is provided near the source in the second semiconductor layer, and a gate is provided on the third semiconductor cap layer. A second source is provided near the source to form a hybrid source. The hybrid source is deposited within the second semiconductor layer and forms gold-semiconductor contacts on the sidewalls and bottom to extract excess holes induced by radiation and reduce the accumulation of holes in the area below the gate. The present invention can effectively reduce transient currents caused by radiation to avoid single-event burnout of the device, improve the radiation resistance of HEMT devices, and enable holes below the gate, which would otherwise take a long time to recombine, to recombine more efficiently after radiation.

Description

Technical Field

[0001] The present invention belongs to the field of power electronics and relates to a gallium nitride power device, in particular to a planar gallium nitride power device with single event effect resistance capability. Background Art

[0002] Gallium nitride (GaN), a third-generation semiconductor material emerging after silicon, germanium, and gallium arsenide, boasts a wide bandgap, high thermal conductivity, excellent chemical stability, and superior radiation resistance. GaN HEMT devices, which have been extensively researched and commercialized on a large scale, are widely recognized for their potential for use in harsh radiation environments. However, their practical application in the complex and hazardous conditions of space still faces numerous challenges.

[0003] The incidence of high-energy particles can instantly introduce a large number of electron-hole pairs inside the device, causing the device to mistakenly turn on in the off state and potentially lead to a failure known as single-event burnout (SEB). Research on related reinforcement methods is still relatively lacking.

[0004] Related existing technology: A method of introducing a doped region in the buffer layer below the source has been proposed to enhance the radiation resistance of GaN MISFETs. However, due to the difficulty of selective doping in GaN, this method is difficult to apply in actual devices, and the design limitations of the structure are also large. Summary of the Invention

[0005] The present invention aims to address the above-mentioned deficiencies by providing a novel planar gallium nitride power device with SEE resistance. This invention employs a method in which an ohmic contact is formed between the source electrode and the two-dimensional electron gas, while a gold semi-contact is formed on the sidewall or surface of the buffer layer to collect radiation-induced excess holes. This method eliminates the need for additional doping regions and complex process steps, thereby improving the SEE resistance of HEMT devices.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A planar gallium nitride power device with single-event effect resistance comprises, from bottom to top, a substrate, a first semiconductor layer, and a second semiconductor layer. A source and a drain are provided at each end of the second semiconductor layer, and a third semiconductor cap layer is provided near the source in the second semiconductor layer. A gate is provided on the third semiconductor cap layer. A second source is provided on the left side of the source to form a hybrid source. The hybrid source is deposited into the interior of the second semiconductor layer and forms gold-semiconductor contacts on the sidewalls and bottom to extract excess holes induced by radiation and reduce the accumulation of holes in the area below the gate.

[0008] In this invention, the sensitive region of a HEMT device to single-particle impact is defined as the region between the gate and drain. Heavy ions incident between the gate and drain generate a large number of electron-hole pairs, which, under the influence of the electric field, converge toward the gate and drain, respectively. However, because the mobility of holes is much lower than that of electrons, holes accumulate in the region below the gate. These holes can cause the channel to open incorrectly, resulting in leakage, and can also cause electrons to be injected from the source, generating additional leakage current.

[0009] The present invention forms a gold semi-contact by depositing a source electrode on the sidewall or above the buffer layer. The formed gold semi-contact can efficiently extract excess holes induced by radiation and weaken the accumulation of holes in the area below the gate, thereby avoiding channel punch-through and reducing device leakage. It does not affect the electrical performance of the device itself and does not add any additional complex process steps, even if the device has the ability to resist radiation.

[0010] As a preferred solution of the present invention, the first semiconductor layer has the same length as the substrate, the second semiconductor layer is shorter than the first semiconductor layer, and a recessed portion for supporting the second source is provided on one end of the first semiconductor layer close to the source.

[0011] As a preferred solution of the present invention, the contact between the second source electrode and the first semiconductor layer is stepped from deep to shallow; or, a third source electrode is further provided at the end of the second source electrode, and the third source electrode extends horizontally into the first semiconductor layer.

[0012] As a preferred solution of the present invention, the third source terminal is located directly below the source and the gate or directly below the gate and the drain; or, the second semiconductor layer penetrates through the first semiconductor layer into the substrate layer, and the middle part contacts the surface of the first semiconductor layer and the surface of the substrate layer.

[0013] As a preferred solution of the present invention, a gap is provided between the source electrode and the second source electrode.

[0014] As a preferred embodiment of the present invention, the second source electrode is in contact with the first semiconductor layer; or, a third source electrode is further provided at the end of the second source electrode, the third source electrode extends horizontally into the first semiconductor layer, and the end of the third source electrode is located directly below the source electrode and the gate electrode or directly below the gate electrode and the drain electrode; or, the second semiconductor layer passes through the first semiconductor layer and extends into the substrate layer, and the middle part contacts the surface of the first semiconductor layer and the surface of the substrate layer.

[0015] As a preferred solution of the present invention, it further includes a source field plate, a gate field plate, or a drain field plate; wherein the source field plate is arranged above the hybrid source.

[0016] As a preferred solution of the present invention, a second drain is provided on the right side of the drain to form a mixed drain.

[0017] As a preferred embodiment of the present invention, the first semiconductor layer is composed of AlN with a thickness of 10 nm to 500 nm, AlGaN with an Al composition of 0 to 0.30 and a thickness of 500 to 5000 nm, and GaN with a thickness of 200 nm to 3000 nm; the second semiconductor layer is AlGaN with an Al composition of 0.05 to 0.50 and a thickness of 5 to 50 nm; the third semiconductor cap layer is composed of a doping concentration of 1×10 15 cm -3 to 1×10 19 cm -3 , P-type doped GaN with a thickness of 0μm to 0.5μm and a length of 0 to 4μm.

[0018] As a preferred solution of the present invention, the first source and the drain are made of one or a combination of materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, etc., and the materials of the source and the second source may be the same or different.

[0019] As a preferred embodiment of the present invention, the gate comprises one or a combination of MIS gate, recessed gate, Schottky gate, ohmic gate, PGaN gate, or a complex gate structure having the above gate characteristics.

[0020] As a preferred solution of the present invention, the length of the third semiconductor cap layer is 0 and the thickness is 0, and the gate is in contact with the surface of the second semiconductor layer; or, the gate penetrates into the second semiconductor layer, and the middle part is in contact with the second semiconductor layer; or, the gate passes through the second semiconductor layer and is in contact with the surface of the first semiconductor layer, and the middle part is in contact with the second semiconductor layer.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] 1) The present invention can effectively reduce the transient current caused by irradiation to avoid single-particle burnout of the device and improve the radiation resistance of the HEMT device.

[0023] 2) The present invention can make the holes under the gate, which originally took a long time to recombine after irradiation, recombine more effectively, so that the device can recover to the state before irradiation more quickly.

[0024] 3) The hybrid source manufacturing process in the device structure of the present invention is fully compatible with the traditional process.

[0025] 4) The present invention improves the radiation resistance of the device without sacrificing the forward conduction performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of a conventional source device.

[0027] Figure 2 Schematic diagram of a hybrid source device of the present invention.

[0028] Figure 3 It is a schematic diagram of transient leakage current changes of the hybrid source device of the present invention and the conventional source device.

[0029] Figure 4 This is a schematic diagram of the hole concentration distribution of a conventional source device after 1μs of irradiation.

[0030] Figure 5 It is a schematic diagram of the hole concentration distribution of the hybrid source device of the present invention after irradiation for 1 μs.

[0031] Figure 6 This is the hole concentration distribution curve on the source side of the conventional source device and the hybrid source device 1μs after irradiation.

[0032] Figure 7 This is a graph showing the current-voltage transfer characteristics of conventional devices and hybrid source device structures of GaN HEMT.

[0033] Figure 8 This is a graph showing the current-voltage output of conventional and hybrid-source GaN HEMT devices.

[0034] Figure 9 Schematic diagram of steps 1-4 of preparing a hybrid source device according to the present invention.

[0035] Figure 10 Schematic diagram of steps 5-7 of preparing the hybrid source device of the present invention.

[0036] Figure 11 Schematic diagram of the preparation of the hybrid source device in steps 8-9 of the present invention.

[0037] Figure 12 Schematic diagram of the preparation of the hybrid source device in steps 10-11 of the present invention.

[0038] Figure 13 Schematic diagram of the hybrid source device of Examples 2 to 6 of the present invention.

[0039] Figure 14 This is a schematic diagram of the hybrid source device of Examples 7 to 9 of the present invention.

[0040] Figure 15 Schematic diagram of a hybrid source device according to embodiment 10 of the present invention.

[0041] Figure 16Schematic diagram of the hybrid source device of Examples 11-13 of the present invention.

[0042] Figure 17 Schematic diagram of a hybrid source device according to embodiments 14-15 of the present invention.

[0043] Figure 18 Schematic diagram of the hybrid source device of Examples 16-18 of the present invention.

[0044] In the figure, 1. substrate; 2. first semiconductor layer; 3. second semiconductor layer; 4. third semiconductor cap layer; 5. source; 6. drain; 7. gate; 8. second source. DETAILED DESCRIPTION

[0045] In order to make the technical means, creative features, purpose and efficacy of the present invention easy to understand, the present invention is further described below in conjunction with specific examples, but the following examples are only preferred embodiments of the present invention, not all. Based on the examples in the embodiments, other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. The experimental methods in the following examples, unless otherwise specified, are conventional methods, and the materials, reagents, etc. used in the following examples, unless otherwise specified, can be obtained from commercial channels.

[0046] See also Figure 1 The conventional source device comprises, from bottom to top, a substrate 1, a first semiconductor layer 2, a second semiconductor layer 3, a source 5 and a drain 6 at both ends of the second semiconductor layer 3, a third semiconductor cap layer 4 close to the source 1, and a gate 7 on the third semiconductor cap layer 4.

[0047] The sensitive region of a HEMT device to single-particle impacts has been identified as the region between the gate and drain. Heavy ions incident between the gate and drain generate a large number of electron-hole pairs, which, under the influence of the electric field, converge toward the gate and drain, respectively. However, because the mobility of holes is much lower than that of electrons, holes accumulate in the region below the gate. These holes can cause the channel to open incorrectly, resulting in leakage, and can also cause electrons to be injected from the source, generating additional leakage current.

[0048] Device stability and reliability are crucial in deep space exploration applications. In recent years, single-event effects (SEEs) caused by high-energy particle impacts have been shown to significantly impact device performance, yet relevant reinforcement methods are still relatively lacking. my country's aerospace sector, while relatively late to the game, is making rapid progress. The research and development of radiation-hardened power devices, along with this invention, will provide significant support for space station projects and manned lunar landings.

[0049] When high-energy particles from space strike semiconductor devices, they generate a large number of electron-hole pairs along their path. These sudden additions can cause dramatic, short-term changes in the electric field and carrier distribution within the device. This can lead to a rapid increase in leakage current. The internal electric field can also excite even more carriers, ultimately causing device breakdown or burnout, manifested as a sharp increase in leakage current below the rated reverse blocking voltage.

[0050] Existing solutions to this problem often increase the device's withstand voltage. However, there's often a trade-off between the device's forward conduction performance and reverse blocking performance: increasing the withstand voltage often sacrifices the device's forward conduction capability. While some SEE reinforcement methods exist, they often require complex processing, making them unsuitable for cost and efficiency reasons.

[0051] Therefore, the present invention deposits a source electrode on the side wall or above the buffer layer to form a gold semi-contact. The formed gold semi-contact can efficiently extract excess holes induced by radiation and weaken the accumulation of holes in the area below the gate, thereby avoiding channel punch-through and reducing device leakage. It does not affect the electrical performance of the device itself and does not add any additional complex process steps, even if the device has the ability to resist radiation.

[0052] See also Figure 2 The planar gallium nitride power device of the present invention includes, from bottom to top, a substrate 1, a first semiconductor layer 2, and a second semiconductor layer 3. A source 5 and a drain 6 are provided at both ends of the second semiconductor layer 3, respectively. A third semiconductor cap layer 4 is provided on the second semiconductor layer 3 near the source 5, and a gate 7 is provided on the third semiconductor cap layer 4. A second source 8 is provided on the left side of the source 5 to form a hybrid source. The hybrid source is deposited into the interior of the second semiconductor layer 3 and forms gold-semiconductor contacts on the sidewalls and bottom to extract excess holes induced by radiation and weaken the accumulation of holes in the area below the gate.

[0053] The substrate material of the device of the present invention includes but is not limited to one of sapphire, silicon carbide, silicon, diamond and gallium nitride, or several of them, or other complex materials with the above material components. In this illustrative structure, we choose Si as the substrate.

[0054] The first semiconductor layer of the device of the present invention includes but is not limited to one of the group III nitrides such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride or two-dimensional materials, or several of these materials, or other complex materials with the above material components. The first semiconductor layer structure of the device of the present invention is composed of at least one layer of material, and also includes but is not limited to one of various complex structural designs such as AlGaN stress release layer with gradient Al composition, superlattice structure, low temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures with the above structural features. In this illustrative structure, we selected AlN with a thickness of 10 to 500 nm, AlGaN with an Al composition of 0 to 0.3 and a thickness of 500 nm to 5000 nm, and GaN with a thickness of 200 to 3000 nm as the first semiconductor layer.

[0055] The second semiconductor layer of the device of the present invention includes, but is not limited to, one of Group III nitrides such as gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or two-dimensional materials, or a combination thereof, or other complex materials having the aforementioned compositions. The second semiconductor layer is composed of at least one layer of semiconductor material and may include, but is not limited to, various complex structural designs. In this illustrative structure, AlGaN with an Al composition of 0.05 to 0.50 and a thickness of 5 to 50 nm is selected as the second semiconductor layer.

[0056] The third semiconductor capping layer of the device of the present invention includes but is not limited to one of the materials of group III nitrides such as gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride or two-dimensional materials, or several of them, or other complex materials with the above material components. The third semiconductor capping layer is composed of at least one layer of semiconductor material and includes but is not limited to various complex structural designs. In this illustrative structure, we choose a doping concentration of 1×10 15 ~1×10 19 cm -3 , P-type doped GaN with a thickness of 0 to 0.5 μm and a length of 0 to 4 μm.

[0057] The gate materials of the device of the present invention include, but are not limited to, one or more of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, and the like, or other complex materials comprising the aforementioned materials. The gate structures of the device of the present invention include, but are not limited to, one or more of the following: recessed gate, MIS gate, Schottky gate, ohmic gate, PGaN gate, or other complex gate structures having the aforementioned gate features. In this illustrative structure, a PGaN Schottky gate with a thickness of 0.1 to 3 μm and a length of 0.1 to 4 μm is used.

[0058] The device of the present invention has drain and source electrodes on both sides. The drain electrode materials include, but are not limited to, one or more of the following materials: Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or other complex materials with the above-mentioned composition. The drain electrode structure of the device of the present invention includes, but is not limited to, one or a combination of Schottky drain, ohmic drain, or other complex drain structures with the characteristics of Schottky drain and ohmic drain. In this illustrative structure, an ohmic drain with a thickness of 0.1 to 3 μm is selected.

[0059] The source electrode materials of the device of the present invention include, but are not limited to, one or more of Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, and the like, or other complex materials having the above-mentioned material components. The structure of the source electrode of the device of the present invention includes, but is not limited to, one or a combination of Schottky source and ohmic source, or other complex source structures having the characteristics of Schottky source and ohmic source. In this illustrative structure, a portion of the source electrode is deposited into the second semiconductor layer and forms gold semiconductor contacts on the sidewalls and bottom.

[0060] The preparation method of the present invention is the same as the existing preparation method, and only the structure is improved. Therefore, the corresponding steps are changed.

[0061] The preparation method of the present invention comprises the following steps:

[0062] 1) Select a substrate layer. The substrate layer material includes but is not limited to one of sapphire, silicon carbide, silicon, diamond, and gallium nitride, or several of these materials, or other complex materials with the above material components. The size of the substrate layer includes but is not limited to two inches, four inches, and six inches.

[0063] 2) The first semiconductor layer growth method includes, but is not limited to, one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process for the first semiconductor layer includes, but is not limited to, growing a group III nitride such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride, or a two-dimensional material, or several of these materials, or other complex materials having the above-mentioned material components as the first semiconductor layer of the device, under conditions of a temperature of 0-1500°C and a pressure of 0-300 Torr. The first semiconductor layer structure is composed of at least one layer of material and includes, but is not limited to, one of various complex structural designs, such as an AlGaN stress relief layer with a gradient Al composition, a superlattice structure, a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures having the above-mentioned structural features.

[0064] 3) The second semiconductor layer growth method includes but is not limited to one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The second semiconductor layer growth process includes but is not limited to growing one of the following group III nitrides, such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride, or two-dimensional materials, or several of these materials, or other complex materials having the above-mentioned material components as the second semiconductor layer of the device, at a temperature of 0-1500°C and a pressure of 0-300 Torr. The second semiconductor layer is composed of at least one layer of semiconductor material and includes but is not limited to various complex structural designs.

[0065] 4) The third semiconductor cap layer growth method includes but is not limited to one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process flow for the third semiconductor cap layer includes but is not limited to growing one of the group III nitrides such as gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or two-dimensional materials, or several of these materials, or other complex materials with the above-mentioned material components as the third semiconductor cap layer of the device under the conditions of temperature of 0-1500°C and pressure of 0-300 Torr. The third semiconductor cap layer is composed of at least one layer of semiconductor material and includes but is not limited to various complex structural designs.

[0066] 5) The etching method for the third semiconductor cap layer includes, but is not limited to, one of the following etching methods: RIE, ICP, hydrogen fluoride release etching, wet etching, or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process for the third semiconductor cap layer includes, but is not limited to, etching the third semiconductor cap layer at an RF power of 0 to 600 W and a pressure of 0 to 100 mTorr.

[0067] 6) The etching method for the first and second semiconductor layers includes, but is not limited to, one of RIE, ICP, hydrogen fluoride release etching, wet etching, or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process for the first and second semiconductor layers includes, but is not limited to, etching the first and second semiconductor layers at an RF power of 0 to 600 W and a pressure of 0 to 100 mTorr.

[0068] 7) The growth methods for the drain and first source include, but are not limited to, one of the following coating methods: Ebeam, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process for the drain and first source includes, but is not limited to, growing one of, but not limited to, Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of these materials, or other complex materials with the aforementioned compositions as the device drain and first source at a temperature of 0-1200°C and a pressure of 0-300 Torr. The annealing method includes, but is not limited to, annealing at 95-1500°C.

[0069] 8) Gate and second source electrode growth methods include, but are not limited to, one of Ebeam, Sputter, LPCVD, PLD, ALD, PEALD, and other coating methods, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The gate and second source electrode growth process includes, but is not limited to, growing one of, but not limited to, Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, and other materials, or several of these materials, or other complex materials with the aforementioned compositions as the device gate and second source electrodes at a temperature of 0-1200°C and a pressure of 0-300 Torr. Annealing methods include, but are not limited to, annealing at 95-1500°C.

[0070] 9) The deposition method of the passivation layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the passivation layer includes but is not limited to deposition at a temperature of 0 to 1500°C and a pressure of 0 to 300 Torr, including but not limited to (Al x Ga 1-x )2O3、Al2O3、AlN、SiN x The device passivation layer may be made of one of the materials, SiO2, or several of them, or a composite material composed of multiple other passivation layer materials having the above-mentioned material components. The passivation layer structure consists of at least one layer and includes but is not limited to various complex structural designs.

[0071] The present invention will be further described below with reference to specific examples:

[0072] Example 1

[0073] See also Figures 9-12The present embodiment provides a planar gallium nitride power device with single event effect resistance, and its preparation method includes:

[0074] 1) Select a substrate layer. The substrate layer material includes but is not limited to sapphire, silicon carbide, silicon, diamond and gallium nitride, or several of these materials, or other complex materials with the above material components. The size of the substrate layer includes but is not limited to two inches, four inches, and six inches. Before using the substrate, it is chemically cleaned using acetone, isopropyl alcohol, hydrochloric acid, hydrofluoric acid, sulfuric acid, hydrogen peroxide, water and other solutions, or a solution containing one of them, or several of these solutions, or a mixture of several of these solutions for wet cleaning, blown dry and placed in a reaction chamber for high temperature treatment. In this embodiment, a two-inch Si (111) substrate is used as the substrate. First, it is placed in a mixed solution of three parts sulfuric acid, one part hydrogen peroxide and one part water for pickling, then placed in a 5% hydrofluoric acid solution to remove surface oxides, and finally the substrate surface is cleaned in sequence using acetone, isopropyl alcohol, and anhydrous ethanol. Finally, it is placed in water, taken out and blown dry.

[0075] 2) The first semiconductor layer growth method includes, but is not limited to, one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth conditions for the first semiconductor layer include, but are not limited to, growing a group III nitride such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride, or a two-dimensional material, or several of these materials, or a composite material of several of these materials, at a temperature of 0-1500°C and a pressure of 0-300 Torr as the first semiconductor layer of the device. The first semiconductor layer is composed of at least one layer of semiconductor material and may include, but is not limited to, one of various complex structural designs, such as an AlGaN stress relief layer with a gradient Al composition, a superlattice structure, a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures having the aforementioned structural features. In this embodiment, trimethylaluminum (TMAl) and NH3 are introduced into the MOCVD reaction chamber to grow an AlN layer with a thickness of 10 to 500 nm at a temperature of 1120°C and a pressure of 70 Torr. The introduction of TMAl is stopped, and the introduction of NH3 is continued to raise the temperature to 1200°C for high-temperature treatment.

[0076] 3) The first semiconductor layer growth method includes, but is not limited to, one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth conditions for the first semiconductor layer include, but are not limited to, growing a group III nitride such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride, or a two-dimensional material, or several of these materials, or a composite of several of these materials, at a temperature of 0-1500°C and a pressure of 0-300 Torr as the first semiconductor layer of the device. The first semiconductor layer is composed of at least one layer of semiconductor material and may include, but is not limited to, one of various complex structural designs, such as an AlGaN stress relief layer with a gradient Al composition, a superlattice structure, a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures having the aforementioned structural features. In this embodiment, after the AlN layer is grown, trimethylgallium (TMGa), TMAl, and NH3 are introduced into the MOCVD reaction chamber to grow an AlGaN layer with an Al composition of 0 to 0.30 and a thickness of 500 nm to 5000 nm at a temperature of 960°C and a pressure of 70 Torr. During the growth process, the flow rate of TMAl gradually decreases, and the flow rate of TMGa gradually increases, gradually transitioning to the growth conditions for growing GaN.

[0077] 4) The first semiconductor layer growth method includes, but is not limited to, one of the following growth methods: MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth conditions for the first semiconductor layer include, but are not limited to, growing a group III nitride such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride, or a two-dimensional material, or several of these materials, or a composite of several of these materials, at a temperature of 0-1500°C and a pressure of 0-300 Torr as the first semiconductor layer of the device. The first semiconductor layer is composed of at least one layer of semiconductor material and may include, but is not limited to, one of various complex structural designs, such as an AlGaN stress relief layer with a gradient Al composition, a superlattice structure, a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures having the aforementioned structural features. In this embodiment, after the AlGaN layer is grown, TMGa, TMAl and NH3 are introduced into the MOCVD reaction chamber to grow a GaN layer with a thickness of 200 to 3000 nm at a temperature of 900° C. and a pressure of 70 Torr.

[0078] 5) The second semiconductor layer growth method includes, but is not limited to, one of MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The second semiconductor layer growth process includes, but is not limited to, growing a Group III nitride (such as aluminum nitride, aluminum gallium nitride, gallium nitride, indium nitride, indium gallium nitride, indium aluminum nitride), or a two-dimensional material, or several of these materials, or other complex materials with the aforementioned compositions, as the device's second semiconductor layer. The second semiconductor layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structural designs. In this embodiment, after growing the GaN layer, TMAl is gradually introduced into the MOCVD reaction chamber, while TMGa is reduced. An AlGaN layer with an Al composition of 0.05 to 0.50 and a thickness of 5 to 50 nm is grown at a temperature of 960°C and a pressure of 70 Torr.

[0079] 6) The growth method of the third semiconductor cap layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the third semiconductor cap layer includes but is not limited to growing one of the group III nitrides such as gallium nitride, aluminum nitride, indium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride or two-dimensional materials, or several of these materials, or other complex materials with the above material components as the third semiconductor cap layer of the device under the conditions of temperature of 0-1500°C and pressure of 0-300 Torr. The third semiconductor cap layer is composed of at least one layer of semiconductor material and includes but is not limited to various complex structural designs. In this embodiment, a p-GaN layer is epitaxially grown after the AlGaN layer is grown. TMGa, dipentyl magnesium (Cp2Mg), NH3 and H2 are introduced into the MOCVD reaction chamber to grow a doping concentration of 1×10 15 ~1×10 19 cm -3 , a p-GaN layer with a thickness of 0 to 0.5 μm, and annealing at a temperature of 700°C.

[0080] 7) The etching method for the third semiconductor cap layer includes but is not limited to one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process for the third semiconductor cap layer includes but is not limited to etching the third semiconductor cap layer under conditions of RF power of 0 to 600 W and pressure of 0 to 100 mTorr. In this embodiment, ICP etching is performed after the p-GaN layer is grown to partially remove the p-GaN. The ICP power is set to 100 W, the pressure is set to 5 mTorr, and Cl2, O2, and Ar are introduced.

[0081] 8) The etching method for the first semiconductor layer and the second semiconductor layer includes, but is not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process for the first and second semiconductor layers includes, but is not limited to, etching the first and second semiconductor layers at an RF power of 0 to 600 W and a pressure of 0 to 100 mTorr. In this embodiment, ICP etching is performed to partially remove the first and second semiconductor layers, with the ICP power set to 100 W, the pressure set to 5 mTorr, and the introduction of Cl2, O2, and Ar.

[0082] 9) The growth method of the drain and the first source includes but is not limited to one of the coating methods such as Ebeam, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The growth process of the drain and the first source includes but is not limited to growing one of the materials including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or several of them, or other complex materials with the above-mentioned material components as the device drain and the first source at a temperature of 0-1200°C and a pressure of 0-300Torr. The annealing method includes but is not limited to annealing at 95-1500°C. In this embodiment, Ebeam coating of Ti / Al / Ni / Au is used, and part of the metal is selectively removed by stripping, and annealing is performed at 830°C.

[0083] 10) Gate and source electrode growth methods include, but are not limited to, one of the following coating methods: E-beam, Sputter, LPCVD, PLD, ALD, PEALD, or a combination of several coating methods, or other complex process flows involving multiple coating methods. The gate and source electrode growth process includes, but is not limited to, growing materials including, but not limited to, Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, or other complex materials with the aforementioned compositions at temperatures between 0 and 1200°C and pressures between 0 and 300 Torr. Annealing methods include, but are not limited to, annealing at 95 to 1500°C. In this embodiment, Ni / Au was deposited using E-beam, with selective removal of some metal by lift-off, followed by annealing at 300°C.

[0084] 11) The deposition method of the passivation layer includes but is not limited to one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the passivation layer includes but is not limited to deposition at a temperature of 0 to 1500°C and a pressure of 0 to 300 Torr, including but not limited to (Al x Ga 1-x )2O3、Al2O3、AlN、SiN x , SiO2, or a combination of these materials, or a composite material composed of multiple other passivation layer materials with the above-mentioned material components as the device passivation layer. The passivation layer structure consists of at least one layer and includes but is not limited to various complex structural designs. In this embodiment, PECVD is used at a temperature of 300°C and a pressure of 850mTorr to pass NH3, N2O, and 5% SiH4 / N2 to deposit 0 to 4000nm of SiN x as a passivation layer.

[0085] See also Figure 2 , including a substrate 1, a first semiconductor layer 2 and a second semiconductor layer 3, wherein a source 5 and a drain 6 are respectively provided at both ends of the second semiconductor layer 3, a third semiconductor cap layer 4 is provided near the source 5 on the second semiconductor layer 3, and a gate 7 is provided on the third semiconductor cap layer 4; a second source 8 is provided on the left side of the source 5 to form a hybrid source, and the hybrid source is deposited into the interior of the second semiconductor layer 3 and forms a gold semiconductor contact on the side wall and the bottom, which is used to extract excess holes induced by radiation and weaken the accumulation of holes in the area below the gate.

[0086] Figure 3This figure shows the transient leakage current changes of a conventional GaN HEMT and a hybrid source device after irradiation. The conventional structure experiences burnout after heavy ion implantation at this energy, and the leakage current rises rapidly. However, the hybrid source structure does not experience breakdown and recovers quickly after irradiation. This demonstrates that the hybrid source structure effectively reduces the device's transient current after irradiation, thereby preventing single-event burnout and improving the device's radiation resistance.

[0087] Figure 4 This is a schematic diagram of the hole concentration distribution of a conventional source device after irradiation. Figure 5 is a schematic diagram of the hole concentration distribution of the hybrid source device of the present invention after irradiation, Figure 6 Figure 2 shows the hole concentration distribution curves on the source side of a conventional source device and a hybrid source device after irradiation. It can be seen that compared to the peak hole concentration on the source side of the conventional structure, the peak hole concentration on the source side of the variable doping structure decreases by more than two orders of magnitude. This shows that the hybrid source structure effectively promotes more efficient recombination of accumulated holes in the region below the gate, thereby improving the device's radiation resistance.

[0088] Figure 7 This is the current-voltage transfer characteristic curve of conventional devices and hybrid source device structure gallium nitride HEMT. Figure 8 The current-voltage output curves for a conventional GaN HEMT and a hybrid-source device are shown below. As can be seen, the two devices have nearly identical on-resistances, with no loss in forward conduction performance.

[0089] Example 2

[0090] See also Figure 13 In (a), in this embodiment, the contact between the second source electrode and the first semiconductor layer is stepped from deep to shallow, and the preparation method is referred to Example 1.

[0091] Example 3

[0092] See also Figure 13 In (b), in this embodiment, the end of the second source electrode penetrates into the first semiconductor layer, and a third source electrode is further provided at the end of the second source electrode. The third source electrode penetrates horizontally into the first semiconductor layer, and the end of the third source electrode is located directly below the middle position between the source electrode and the gate electrode. The preparation method refers to Example 1.

[0093] Example 4

[0094] See also Figure 13 In (c), in this embodiment, a third source electrode is further provided at the end of the second source electrode, the third source electrode horizontally penetrates into the first semiconductor layer, and the end of the third source electrode does not exceed the right side of the source electrode. The preparation method refers to Example 1.

[0095] Example 5

[0096] See also Figure 13 In (d), in this embodiment, a gap is provided between the source electrode and the second source electrode, and the preparation method is referred to that in Example 1.

[0097] Example 6

[0098] See also Figure 13 In (e), a gap is provided between the source electrode and the second source electrode in this embodiment, and a third source electrode is also provided. The third source electrode extends horizontally into the first semiconductor layer. The preparation method is referred to Example 1.

[0099] Example 7

[0100] See also Figure 14 In (f), an active field plate is provided above the hybrid source electrode of this embodiment, and the preparation method is referred to that of Example 1.

[0101] Example 8

[0102] See also Figure 14 In (g), a gate field plate is provided on the gate of this embodiment, and the preparation method is referred to Example 1.

[0103] Example 9

[0104] See also Figure 14 In (h), a drain field plate is provided on the drain electrode of this embodiment, and the preparation method is referred to Example 1.

[0105] Example 10

[0106] See also Figure 15 A second drain is also provided on the right side of the drain in this embodiment. The preparation method is referred to Example 1. The preparation method is referred to Example 1.

[0107] Example 11

[0108] See also Figure 16 In (i), in this embodiment, the third semiconductor cap layer is removed, and the gate is in direct contact with the second semiconductor layer. The preparation method is similar to that of Example 1.

[0109] Example 12

[0110] See also Figure 16 In (j), in this embodiment, the third semiconductor cap layer is removed, and a dielectric layer is provided on the outside of the gate. The preparation method is referred to Example 1.

[0111] Example 13

[0112] See also Figure 16 In (j), in this embodiment, the third semiconductor cap layer is removed, and the gate is deposited into the second semiconductor layer. The preparation method is referred to Example 1.

[0113] Example 14

[0114] See also Figure 17 In (L), in this embodiment, the second source electrode passes through the second semiconductor layer and the first semiconductor layer and contacts the substrate layer. The preparation method refers to Example 1.

[0115] Example 15

[0116] See also Figure 17 (m) in the figure, in this embodiment, a third source electrode is further provided at the end of the second source electrode, the third source electrode horizontally penetrates into the first semiconductor layer, and the end of the third source electrode is located below between the gate electrode and the drain electrode. The preparation method refers to Example 1.

[0117] Example 16

[0118] See also Figure 18 In (n), in this embodiment, the third semiconductor cap layer is removed, a dielectric layer is provided outside the gate, the gate and the dielectric layer penetrate into the second semiconductor layer but do not reach the first semiconductor layer. The preparation method refers to Example 1.

[0119] Example 17

[0120] See also Figure 18 In (o), in this embodiment, the third semiconductor cap layer is removed, a dielectric layer is provided outside the gate, the gate and the dielectric layer penetrate into the second semiconductor layer and contact the first semiconductor layer. The preparation method is referred to Example 1.

[0121] Example 18

[0122] See also Figure 18 In (p), the third semiconductor cap layer is removed in this embodiment, a dielectric layer is provided outside the gate, the gate and the dielectric layer pass through the second semiconductor layer and penetrate into the first semiconductor layer. The preparation method is referred to Example 1.

[0123] The present invention introduces a hybrid source structure, which effectively improves the radiation resistance of HEMT devices without introducing additional processing steps or sacrificing the device's forward conduction performance. This method modulates the accumulated holes in the region below the gate caused by contact radiation between the source and the device buffer layer, thereby enhancing the device's radiation resistance. The above embodiment is only one possible structure of the present invention. In actual applications, parameters such as the material selection, thickness, and doping concentration design of each layer, the specific HEMT structure design (such as whether other semiconductor layers are between the first and second semiconductor layers, whether other semiconductor layers are between the substrate and the first semiconductor layer, other gate types, SOI devices, graded semiconductor layer compositions, and similar drain designs), the specific source shape and dimensions, the specific shapes and dimensions of other key structures, the type of gold-semiconductor contact, and the location, depth, and shape of the gold-semiconductor contact formation can vary appropriately depending on application conditions. Furthermore, the first / second semiconductor layer refers to a layer having at least one structure, not just a single structure. These variations are also considered within the scope of protection of the present invention without departing from the principles of the present invention.

[0124] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form or substance. It should be pointed out that ordinary technicians in this technical field can make several combinations, improvements and supplements without departing from the method of the present invention. These combinations, improvements and supplements should also be regarded as the scope of protection of the present invention. Any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the spirit and scope of the present invention by using the technical content disclosed above are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A planar gallium nitride power device with single event effect resistance, characterized in that: The planar gallium nitride power device comprises, from bottom to top, a substrate, a first semiconductor layer, and a second semiconductor layer. A source electrode and a drain electrode are provided at both ends of the second semiconductor layer, respectively. A third semiconductor cap layer is provided near the source electrode of the second semiconductor layer, and a gate electrode is provided on the third semiconductor cap layer. A second source electrode is provided near the source electrode to form a hybrid source electrode. The hybrid source electrode is deposited inside the second semiconductor layer and forms gold-semiconductor contacts on the sidewalls and bottom to extract excess holes induced by radiation and reduce the accumulation of holes in the area below the gate electrode. The contact portion between the second source electrode and the first semiconductor layer is stepped from deep to shallow.

2. A planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: The first semiconductor layer has the same length as the substrate, the second semiconductor layer has a length less than or equal to the first semiconductor layer, and a recessed portion for supporting the second source is provided on one end of the first semiconductor layer close to the source.

3. A planar gallium nitride power device with single event effect resistance according to claim 1 or 2, characterized in that: A third source electrode is further provided at the end of the second source electrode, and the third source electrode extends horizontally into the first semiconductor layer.

4. The planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: A third source electrode is further provided at the end of the second source electrode, the third source electrode extends horizontally into the first semiconductor layer, and the end of the third source electrode is located directly below the source electrode and the gate electrode or directly below the gate electrode and the drain electrode; Alternatively, the second source electrode penetrates through the first semiconductor layer and extends deep into the substrate, with a middle portion thereof in contact with the surface of the first semiconductor layer and the surface of the substrate.

5. A planar gallium nitride power device with single event effect resistance according to claim 1 or 2, characterized in that: A gap is provided between the source electrode and the second source electrode.

6. The planar gallium nitride power device with single event effect resistance according to claim 5, characterized in that: The second source electrode is in contact with the first semiconductor layer; or a third source electrode is further provided at the end of the second source electrode, the third source electrode extends horizontally into the first semiconductor layer, and the end of the third source electrode is located directly below the source electrode and the gate electrode or directly below the gate electrode and the drain electrode; Alternatively, the second source electrode penetrates through the first semiconductor layer and extends deep into the substrate, with a middle portion thereof in contact with the surface of the first semiconductor layer and the surface of the substrate.

7. The planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: It also includes a source field plate, a gate field plate, or a drain field plate; wherein the source field plate is arranged above the hybrid source.

8. The planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: A second drain is provided on the right side of the drain to form a mixed drain.

9. The planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: The gate comprises at least one of a MIS gate, a recessed gate, a Schottky gate, an ohmic gate, and a PGaN gate, or a combination of several of the above.

10. The planar gallium nitride power device with single event effect resistance according to claim 1, characterized in that: The length of the third semiconductor cap layer is 0 and the thickness is 0, and the gate contacts the surface of the second semiconductor layer; or, the gate penetrates into the second semiconductor layer, and the middle part contacts the second semiconductor layer; or, the gate passes through the second semiconductor layer and contacts the surface of the first semiconductor layer, and the middle part contacts the second semiconductor layer.

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