Split-gate memory array and method of operating the same

Abstract

A split-gate memory array and its operating method, wherein the array comprises: a memory array composed of a plurality of memory cell groups, each memory cell group comprising a first memory cell and a second memory cell, the first memory cell comprising a first memory tube and a first select tube in a split-gate structure, and the second memory cell comprising a second memory tube and a second select tube in a split-gate structure; the gates of the first memory tubes in the same row are connected together; the gates of the second memory tubes in the same row are connected together; the gates of the first select tubes in the same row are connected together, and the gates of the second select tubes in the same row are connected together; the gates of the first select tubes and the second select tubes in the memory cell group are connected together; all the sources are connected together; the drains of the first memory tubes in the same column are connected together; and the drains of the second memory tubes in the same column are connected together. Since the select tubes and the memory tubes adopt the split-gate structure, the gates of the adjacent select tubes are connected together to reduce the number of external connection holes, thereby reducing the area of the memory cell.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gated memory array and its operation method. Background Technology

[0002] With the rapid popularization of electronic products, flash memory has become the mainstream storage medium and its technology has developed rapidly. Non-volatile memory (NVM) technology can be categorized by storage medium into floating gate technology and SONOS technology (Silicon-Oxide-Nitride-Oxide-Silicon), and by structure into single-gate technology (1-transistor), split-gate technology, and dual-gate technology (2-transistor). Due to its long lifespan, non-volatility, low price, and ease of programming and erasing, Flash memory is increasingly widely used in various embedded electronic products such as financial IC cards and automotive electronics. Increasing storage integration density helps save chip area and reduce manufacturing costs.

[0003] Currently, with the development of mainstream process technologies and the urgent demand for flash devices, gate-splitting flash memory based on a gate-splitting structure has attracted widespread attention. Compared to traditional flash memory, gate-splitting flash memory, as a type of flash memory, has gained more attention in both standalone and embedded products due to its high programming speed and ability to completely avoid over-erasure. Currently, gate-splitting flash memory is widely used in personal computers, digital devices, mobile terminals, smart cards, and other products. This novel gate-splitting flash memory exhibits superior performance in terms of reliability and over-erasure prevention. Moreover, due to its compact structure, more storage cells can be integrated within the same chip area, thus achieving better optimization of capacity.

[0004] However, due to the dramatic increase in data volume in the current information age, further optimization of memory structure to achieve higher capacity has always been the industry's pursuit. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a gated memory array and its operation method, which effectively reduces the area of ​​the memory cell.

[0006] To address the aforementioned problems, this invention provides a segmented memory array, comprising: a plurality of memory cell groups, wherein the plurality of memory cell groups are respectively distributed along a first direction and a second direction to form a memory array placed in the same well region, the first direction being perpendicular to the second direction; wherein each memory cell group includes a first memory cell and a second memory cell arranged and connected along the second direction, the first memory cell including a first memory transistor and a first select transistor configured with a segmented gate structure, the second memory cell including a second memory transistor and a second select transistor configured with a segmented gate structure, the first select transistor and the second select transistor being connected together and located between the first memory transistor and the second memory transistor, the first select transistor and the second select transistor sharing a source terminal such that the first memory cell and the second memory cell share a source terminal; along the first direction, bit The gates of multiple first memory transistors in the same row are connected and connected by a memory gate word line WLSna; the gates of multiple second memory transistors in the same row are connected and connected by a memory gate word line WLSnb; the gates of multiple first select transistors in the same row are connected, the gates of multiple second select transistors in the same row are connected, and the gates of the first select transistor and the second select transistor in each memory cell group are connected and connected by a select gate word line WLn; and the sources of multiple memory cell groups in the same row are connected and simultaneously connected to a source line SL; along the second direction, the drains of multiple first memory transistors in the same column are connected and connected by a bit line BLna; the drains of multiple second memory transistors in the same column are connected and connected by a bit line BLnb.

[0007] Optionally, in the storage cell group, the channels of the first storage tube and the second storage tube are in the horizontal direction; the channels of the first selection tube and the second selection tube are in the vertical direction.

[0008] Optionally, in the storage cell group, the first storage transistor, the first selection transistor, the second storage transistor, and the second selection transistor share a source.

[0009] Optionally, the first storage tube includes a SONOS storage tube; the second storage tube includes a SONOS storage tube.

[0010] Optionally, the first selector is a MOS transistor device comprising a stacked gate oxide layer and a polysilicon gate layer; the second selector is a MOS transistor device comprising a stacked gate oxide layer and a polysilicon gate layer.

[0011] Accordingly, the present invention also proposes an operation method based on the above-described gated memory array structure, wherein the memory array adopts a row operation mode when erasing and writing data, that is, the target memory cells located in the same row are simultaneously erased and written.

[0012] Optionally, when erasing data in the storage array, a negative voltage Vneg is applied to the storage gate word line WLSna or storage gate word line WLSnb corresponding to the row where the selected target storage cell is located; a positive voltage Vpos is applied to the storage gate word lines WLSna and WLSnb in the non-selected storage cells in the storage array; a positive voltage Vpos is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; and a positive voltage Vpos is applied to all bit lines BLna and BLnb in the storage array.

[0013] Optionally, when writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSna corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word lines WLSna and WLSnb in the non-selected storage cells in the storage array; a negative voltage Vneg is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; when writing data "1" to the selected target storage cell, a negative voltage Vneg is applied to the bit line BLna corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected storage cell; when writing data "0" to the selected target storage cell, a positive voltage Vp0 is applied to the bit line BLna corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected storage cell.

[0014] Optionally, when writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSnb corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word lines WLSna and WLSnb in the currently unselected storage cells in the storage array; a negative voltage Vneg is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; when writing data "1" to the selected target storage cell, a negative voltage Vneg is applied to the bit line BLnb corresponding to the selected target storage cell; a negative voltage Vneg is applied to the bit line BLna corresponding to the unselected storage cell; when writing data "0" to the selected target storage cell, a positive voltage Vp0 is applied to the bit line BLnb corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLna corresponding to the unselected storage cell.

[0015] Optionally, when reading data from the memory array, a positive voltage Vpwr greater than the select transistor turn-on voltage is applied to the select gate word line WLn corresponding to the selected target memory cell; a positive voltage Vpos1 is applied to the bit line BLna or bit line BLnb corresponding to the selected target memory cell; and the remaining terminals in the memory array are grounded to Vgnd.

[0016] Optionally, different voltage values ​​are applied to the well region when erasing, writing, and reading data from the storage array.

[0017] Optionally, when performing an erase operation on the selected target memory cell, the voltage applied to the well region is a positive voltage Vpos; when performing a write operation on the selected target memory cell, the voltage applied to the well region is a negative voltage Vneg; when performing a read operation on the selected target memory cell, the well region is grounded Vgnd.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the gate-splitting memory array of the present invention, several memory cell groups are distributed along a first direction and a second direction to form a memory array placed in a well region. Each memory cell group includes two sets of select transistors and memory transistors formed with a gate-splitting structure. Since the select transistors and memory transistors adopt a gate-splitting structure and adjacent select transistor gates are connected together, the number of external vias is reduced. Under the same process node, the gate-splitting memory array effectively reduces the area of ​​the memory cells.

[0020] Furthermore, the memory cell group adopts a 3D structure, meaning that the channels of the first and second memory transistors are horizontal, while the channels of the first and second select transistors are vertical, saving horizontal area. Additionally, the first and second select transistors share a common gate, saving the area of ​​external vias. Therefore, at the same process node, the use of a 3D memory cell group in the gate-splitting memory array can effectively reduce area. Attached Figure Description

[0021] Figure 1 This is a partial structural schematic diagram of the gate-division memory array in an embodiment of the present invention;

[0022] Figure 2 yes Figure 1 A schematic diagram of the structure of the storage cell group;

[0023] Figures 3 to 12 This is a schematic diagram of the local potential during the erasure, writing, and reading operations of the gated memory array in an embodiment of the present invention. Detailed Implementation

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a partial structural schematic diagram of the gate-division memory array in an embodiment of the present invention; Figure 2 yes Figure 1 A schematic diagram of the structure of the storage unit group.

[0026] Please refer to Figure 1 and Figure 2 A gate-based memory array includes: a plurality of memory cell groups 100, wherein the plurality of memory cell groups 100 are respectively distributed along a first direction X and a second direction Y to form a memory array placed in the same well region 101, wherein the first direction X is perpendicular to the second direction Y; wherein each memory cell group 100 includes a first memory cell A1 and a second memory cell B1 (or may also be) arranged and connected along the second direction. Figure 1(As shown in A2 and B2, C1 and D2, C2 and D2), the first memory cell A1 includes a first memory transistor 102 and a first select transistor 103 configured with a split-gate structure, and the second memory cell B1 includes a second memory transistor 104 and a second select transistor 105 configured with a split-gate structure. The first select transistor 103 and the second select transistor 105 are connected together and located between the first memory transistor 102 and the second memory transistor 104. The first select transistor 103 and the second select transistor 105 share a source, so that the first memory cell A1 and the second memory cell B1 share a source. Along the first direction X, the gates of a plurality of first memory transistors 102 located in the same row are connected and connected by a memory gate word line WLSna. Figure 1 Specifically shown are WLS1a and WLS2a); the gates of multiple second memory transistors 104 located in the same row are connected and connected by a memory gate word line WLSnb. Figure 1 Specifically, WLS1b and WLS2b are shown as outputs; the gates of multiple first select transistors 103 located in the same row are connected, the gates of multiple second select transistors 105 located in the same row are connected, and the gates of the first select transistors 103 and the second select transistors 105 in each memory cell group are connected, and connected by a select gate word line WLn. Figure 1 Specifically, WL1 and WL2 are shown connected out; and the sources of multiple memory cell groups 100 located in the same row are connected out and simultaneously connected to a source line SL; along the second direction Y, the drains of multiple first memory cells 102 located in the same column are connected and connected to a bit line BLna ( Figure 1 Specifically, BL1a and BL2a are shown as outputs; the drains of multiple second memory transistors 104 located in the same column are connected together by a bit line BLnb. Figure 1 Specifically, BL1b and BL2b are shown as outputs.

[0027] In this embodiment, several memory cell groups are distributed along the first direction X and the second direction Y to form a memory array placed in the well region 101. Each memory cell group 100 includes two groups of select transistors and memory transistors formed with a gate-splitting structure. Since the select transistors and memory transistors adopt a gate-splitting structure and the gates of adjacent select transistors are connected together, the number of external vias is reduced. Under the same process node, the gate-splitting memory array effectively reduces the area of ​​the memory cells.

[0028] In this embodiment, the memory cell group 100 adopts a 3D structure, that is, the channels of the first memory transistor 102 and the second memory transistor 104 are horizontal; the channels of the first select transistor 103 and the second select transistor 105 are vertical, which can save the area in the horizontal direction. Furthermore, the first select transistor 103 and the second select transistor 105 share a common gate, which can save the area of ​​external vias. Therefore, at the same process node, the use of a 3D memory cell group in the gate-divided memory array can effectively reduce the area of ​​the memory cells.

[0029] In this embodiment, the first storage tube 102 is a SONOS storage tube; the second storage tube 104 is a SONOS storage tube.

[0030] In this embodiment, the first select transistor 103 is a MOS transistor device including a stacked gate oxide layer and a polysilicon gate layer; the second select transistor 105 is a MOS transistor device including a stacked gate oxide layer and a polysilicon gate layer.

[0031] Figures 3 to 12 This is a schematic diagram of the local potential during the erasure, writing, and reading operations of the gated memory array in an embodiment of the present invention.

[0032] Accordingly, this embodiment of the invention also provides an operation method based on the above-described grid-based memory array structure, wherein the memory array adopts a row operation mode when erasing and writing data, that is, the target memory cells located in the same row are simultaneously erased and written.

[0033] When erasing data in the memory array, a negative voltage Vneg is applied to the memory gate word line WLSna or WLSnb corresponding to the row containing the selected target memory cell; a positive voltage Vpos is applied to the memory gate word lines WLSna and WLSnb of the non-selected memory cells in the memory array; a positive voltage Vpos is applied to all selected gate word lines WLn in the memory array; the source line SL in the memory array is set to a floating state; and a positive voltage Vpos is applied to all bit lines BLna and BLnb in the memory array.

[0034] When writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSna corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word lines WLSna and WLSnb in the non-selected storage cells in the storage array; a negative voltage Vneg is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; when writing data "1" to the selected target storage cell, a negative voltage Vneg is applied to the bit line BLna corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected storage cell; when writing data "0" to the selected target storage cell, a positive voltage Vp0 is applied to the bit line BLna corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected storage cell.

[0035] When writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSnb corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word lines WLSna and WLSnb in the non-selected storage cells in the storage array; a negative voltage Vneg is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; when writing data "1" to the selected target storage cell, a negative voltage Vneg is applied to the bit line BLnb corresponding to the selected target storage cell; a negative voltage Vneg is applied to the bit line BLna corresponding to the non-selected storage cell; when writing data "0" to the selected target storage cell, a positive voltage Vp0 is applied to the bit line BLnb corresponding to the selected target storage cell, and a negative voltage Vneg is applied to the bit line BLna corresponding to the non-selected storage cell.

[0036] When reading data from the memory array, a positive voltage Vpwr greater than the select transistor turn-on voltage is applied to the select gate word line WLn corresponding to the selected target memory cell; a positive voltage Vpos1 is applied to the bit line BLna or bit line BLnb corresponding to the selected target memory cell; and the remaining terminals in the memory array are grounded to Vgnd.

[0037] When erasing, writing, and reading data from the storage array, different voltage values ​​are applied to the well region 101. When erasing a selected target storage cell, a positive voltage Vpos is applied to the well region 101. When writing to a selected target storage cell, a negative voltage Vneg is applied to the well region 101. When reading from a selected target storage cell, the well region 101 is grounded to Vgnd.

[0038] In one specific embodiment, Table 1 shows the table of voltages applied for reading, erasing, and writing data to the storage array provided in this embodiment of the invention.

[0039]

[0040]

[0041] Table 1

[0042] As shown in Table 1, "Erase" represents the data erasure operation of the memory cell, "Program" represents the data writing operation of the memory cell, and "Read" represents the data reading operation of the memory cell; "Vwl" represents the voltage value applied to the select gate word line WLn of the memory cell; "Vwls" represents the voltage value applied to the memory gate word line WLSna or WLSnb of the memory cell; "Vbl" represents the voltage value applied to the bit line BLna or BLnb of the memory cell; "Vsl" represents the voltage value applied to the source line SL of the memory cell; and "Vpw" represents the voltage value applied to the well region of the memory cell.

[0043] Refer to Table 1 and other relevant information. Figure 3 and Figure 4 In one specific embodiment, when erasing data in the storage array, a negative voltage Vneg is applied to the storage gate word line WLS1a corresponding to the row where the selected first storage cells A1 and A2 are located; a positive voltage Vpos is applied to the storage gate word lines WLS1a, WLS2a and WLS1b, WLS2b of the rows where the non-selected first storage cells and second storage cells B1 to D2 are located; a positive voltage Vpos is applied to all selected gate word lines WL1 and WL2 in the storage array; the source line SL in the storage array is set to a floating state; a positive voltage Vpos is applied to all bit lines BL1a, BL2a and BL1b, BL2b in the storage array; and a positive voltage Vpos is applied to the well region 101.

[0044] Refer to Table 1 and other relevant information. Figure 5 and Figure 6In one specific embodiment, when the storage array performs data writing, a positive voltage Vpos is applied to the storage gate word line WLS1a corresponding to the row containing the selected first storage cells A1 and A2; a negative voltage Vneg is applied to the storage gate word lines WLS1a, WLS2a and WLS1b, WLS2b of the rows containing the currently unselected first storage cells C1 and C2 and the second storage cells B1, B2, D1, D2; a negative voltage Vneg is applied to all selected gate word lines WL1 and WL2 in the storage array; and the source line SL in the storage array is set... The state is floating. When writing data "1" into the selected first memory cell A1, a negative voltage Vneg is applied to the bit line BL1a corresponding to the selected first memory cell A1, and a negative voltage Vneg is applied to the bit line BL1b corresponding to the unselected second memory cell B1. When writing data "0" into the selected first memory cell A2, a positive voltage Vp0 is applied to the bit line BL2a corresponding to the selected first memory cell A2, and a negative voltage Vneg is applied to the bit line BL2b corresponding to the unselected second memory cell B2. The voltage applied to the well region 101 is a negative voltage Vneg.

[0045] Refer to Table 1 and other relevant information. Figure 7 and Figure 8 In one specific embodiment, when the storage array performs data writing, a positive voltage Vpos is applied to the storage gate word line WLS1b corresponding to the row containing the selected second storage cells B1 and B2; a negative voltage Vneg is applied to the storage gate word lines WLS1a, WLS2a and WLS1b, WLS2b of the rows containing the currently unselected first storage cells A1, A2, C1, C2 and the second storage cells D1, D2; a negative voltage Vneg is applied to all selected gate word lines WL1 and WL2 in the storage array; and the source line SL in the storage array is set to floating. Empty state (Float); When writing data "1" to the selected second memory cell B1, a negative voltage Vneg is applied to the bit line BL1b corresponding to the selected second memory cell B1, and a negative voltage Vneg is applied to the bit line BL1a corresponding to the unselected first memory cell A1; When writing data "0" to the selected second memory cell B2, a positive voltage Vp0 is applied to the bit line BL2b corresponding to the selected second memory cell B2, and a negative voltage Vneg is applied to the bit line BL2a corresponding to the unselected first memory cell A2; The voltage applied to the well region 101 is a negative voltage Vneg.

[0046] Refer to Table 1 and other relevant information. Figure 9 and Figure 10, in a specific embodiment, when the storage array reads data, a positive voltage Vpwr greater than the turn-on voltage of the first selection transistor 103 is applied to the selected selection gate word line WL1 corresponding to the first storage cell A1; a positive voltage Vpos1 is applied to the selected bit line BL1a corresponding to the first storage cell A1; and the remaining terminals in the storage array are grounded to Vgnd.

[0047] Refer to Table 1 and Figure 11 and Figure 12 , in a specific embodiment, when the storage array reads data, a positive voltage Vpwr greater than the turn-on voltage of the first selection transistor 103 is applied to the selected selection gate word line WL1 corresponding to the second storage cell B1; a positive voltage Vpos1 is applied to the selected bit line BL1b corresponding to the second storage cell B1; and the remaining terminals in the storage array are grounded to Vgnd.

[0048] It should be noted that in this embodiment, the relationship between the voltages Vneg, Vpos1, Vgnd, Vp0, Vpwr, and Vpos can be Vneg < Vgnd = 0V < Vpos1 < Vp0 < Vpwr < Vpos. Specifically, the voltage values of the voltages Vneg, Vpos1, Vp0, Vpwr, and Vpos are only示例性 shown in the embodiments of the present invention, that is: voltage Vneg = -4V, voltage Vpos1 = 0.8V, voltage Vp0 = 1.2V, Vpwr = 1.8V, voltage Vpos = 7V, and in other cases, different voltage values can be set according to actual situations, and no specific limitations are made compared with the embodiments of the present invention.

[0049] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A gated memory array, characterized in that, include: A plurality of memory cell groups are distributed along a first direction and a second direction respectively to form a memory array placed in the same well region, wherein the first direction is perpendicular to the second direction; wherein, Each of the memory cell groups includes a first memory cell and a second memory cell arranged and connected along the second direction. The first memory cell includes a first memory transistor and a first select transistor with a split gate structure. The second memory cell includes a second memory transistor and a second select transistor with a split gate structure. The first select transistor and the second select transistor are connected together and located between the first memory transistor and the second memory cell. The first select transistor and the second select transistor share a source terminal so that the first memory cell and the second memory cell share a source terminal. Along the first direction, the gates of a plurality of first memory transistors located in the same row are connected and connected by a memory gate word line WLSna; the gates of a plurality of second memory transistors located in the same row are connected and connected by a memory gate word line WLSnb; the gates of a plurality of first select transistors located in the same row are connected, the gates of a plurality of second select transistors located in the same row are connected, and the gates of the first select transistor and the second select transistor in each memory cell group are connected and connected by a select gate word line WLn; and the sources of the plurality of memory cell groups located in the same row are connected together and simultaneously connected to a source line SL. Along the second direction, the drains of multiple first memory transistors located in the same column are connected together and connected by a bit line BLna; the drains of multiple second memory transistors located in the same column are connected together and connected by a bit line BLnb.

2. The gated memory array as described in claim 1, characterized in that, In the memory cell group, the channels of the first memory cell and the second memory cell are horizontal; the channels of the first select cell and the second select cell are vertical.

3. The gated memory array as described in claim 1, characterized in that, The first storage tube includes: The second storage tube includes: a SONOS storage tube.

4. The gated memory array as described in claim 1, characterized in that, The first selector is a MOS transistor device comprising a stacked gate oxide layer and a polysilicon gate layer; the second selector is a MOS transistor device comprising a stacked gate oxide layer and a polysilicon gate layer.

5. An operation method based on the segmented memory array structure according to any one of claims 1 to 4, characterized in that, The storage array uses a row operation mode when erasing and writing data, that is, data is erased and written simultaneously in the same target storage unit in the same row.

6. The method for operating a segmented memory array as described in claim 5, characterized in that, When erasing data in the storage array, a negative voltage Vneg is applied to the storage gate word line WLSna or storage gate word line WLSnb corresponding to the row where the selected target storage cell is located; a positive voltage Vpos is applied to the storage gate word lines WLSna and WLSnb of the non-selected storage cells in the storage array; a positive voltage Vpos is applied to all selected gate word lines WLn in the storage array; the source line SL in the storage array is set to a floating state; and a positive voltage Vpos is applied to all bit lines BLna and BLnb in the storage array.

7. The method for operating a grid-splitter memory array as described in claim 5, characterized in that, When writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSna corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word line WLSna and the storage gate word line WLSnb in the storage cell that is not selected in this storage array. A negative voltage Vneg is applied to all selected gate word lines WLn in the memory array; the source lines SL in the memory array are set to a floating state; when writing data "1" to the selected target memory cell, a negative voltage Vneg is applied to the bit line BLna corresponding to the selected target memory cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected memory cell; when writing data "0" to the selected target memory cell, a positive voltage Vp0 is applied to the bit line BLna corresponding to the selected target memory cell, and a negative voltage Vneg is applied to the bit line BLnb corresponding to the non-selected memory cell.

8. The method for operating a grid-connected memory array as described in claim 5, characterized in that, When writing data to the storage array, a positive voltage Vpos is applied to the storage gate word line WLSnb corresponding to the row where the selected target storage cell is located; a negative voltage Vneg is applied to both the storage gate word line WLSna and the storage gate word line WLSnb in the storage cells that are not selected in this storage array. A negative voltage Vneg is applied to all selected gate word lines WLn in the memory array; the source lines SL in the memory array are set to a floating state; when writing data "1" to the selected target memory cell, a negative voltage Vneg is applied to the bit line BLnb corresponding to the selected target memory cell; a negative voltage Vneg is applied to the bit line BLna corresponding to the non-selected memory cell; when writing data "0" to the selected target memory cell, a positive voltage Vp0 is applied to the bit line BLnb corresponding to the selected target memory cell, and a negative voltage Vneg is applied to the bit line BLna corresponding to the non-selected memory cell.

9. The method for operating a grid-splitter memory array as described in claim 5, characterized in that, When reading data from the memory array, a positive voltage Vpwr greater than the turn-on voltage of the select transistor is applied to the select gate word line WLn corresponding to the selected target memory cell; a positive voltage Vpos1 is applied to the bit line BLna or bit line BLnb corresponding to the selected target memory cell; and the remaining terminals in the memory array are grounded to Vgnd.

10. The method of operating a grid-connected memory array as described in claim 5, characterized in that, Different voltage values ​​are applied to the well region when erasing, writing, and reading data from the storage array.

11. The method of operating a grid-connected memory array as described in claim 10, characterized in that, When an erase operation is performed on the selected target memory cell, a positive voltage Vpos is applied to the well region; when a write operation is performed on the selected target memory cell, a negative voltage Vneg is applied to the well region; when a read operation is performed on the selected target memory cell, the well region is grounded Vgnd.

Images